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-rw-r--r--gas/ChangeLog9
-rw-r--r--gas/config/tc-arm.c44
-rw-r--r--gas/testsuite/ChangeLog6
-rw-r--r--gas/testsuite/gas/arm/arch5tej.d15
-rw-r--r--gas/testsuite/gas/arm/arch5tej.s9
-rw-r--r--gas/testsuite/gas/arm/arm.exp2
6 files changed, 79 insertions, 6 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 3ff9266..1e2eaa1 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,4 +1,13 @@
2002-01-18 Richard Earnshaw <rearnsha@arm.com>
+ Keith Walker <keith.walker@arm.com>
+
+ * tc-arm.c (ARM_EXT_V5J, ARM_ARCH_V5TEJ): Define.
+ (insns): Add pattern for bxj instruction.
+ (do_bxj): New function.
+ (arm_cpus): Add arm926ej.
+ (arm_archs): Add armv5tej.
+
+2002-01-18 Richard Earnshaw <rearnsha@arm.com>
* doc/c-arm.texi: Add new fpe options to list of supported flags.
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 1c7f6be..7dfb5ec 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -54,6 +54,7 @@
#define ARM_EXT_V5T 0x00000100 /* Thumb v2. */
#define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */
#define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */
+#define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */
/* Co-processor space extensions. */
#define ARM_CEXT_XSCALE 0x00800000 /* Allow MIA etc. */
@@ -79,6 +80,7 @@
#define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_EXT_V4T | ARM_EXT_V5T)
#define ARM_ARCH_V5TExP (ARM_ARCH_V5T | ARM_EXT_V5ExP)
#define ARM_ARCH_V5TE (ARM_ARCH_V5TExP | ARM_EXT_V5E)
+#define ARM_ARCH_V5TEJ (ARM_ARCH_V5TE | ARM_EXT_V5J)
/* Processors with specific extensions in the co-processor space. */
#define ARM_ARCH_XSCALE (ARM_ARCH_V5TE | ARM_CEXT_XSCALE)
@@ -746,7 +748,7 @@ static void do_ldstv4 PARAMS ((char *));
/* ARM v4T. */
static void do_bx PARAMS ((char *));
-/* ARM v5. */
+/* ARM v5T. */
static void do_blx PARAMS ((char *));
static void do_bkpt PARAMS ((char *));
static void do_clz PARAMS ((char *));
@@ -754,17 +756,20 @@ static void do_lstc2 PARAMS ((char *));
static void do_cdp2 PARAMS ((char *));
static void do_co_reg2 PARAMS ((char *));
-/* ARM v5ExP. */
+/* ARM v5TExP. */
static void do_smla PARAMS ((char *));
static void do_smlal PARAMS ((char *));
static void do_smul PARAMS ((char *));
static void do_qadd PARAMS ((char *));
-/* ARM v5E. */
+/* ARM v5TE. */
static void do_pld PARAMS ((char *));
static void do_ldrd PARAMS ((char *));
static void do_co_reg2c PARAMS ((char *));
+/* ARM v5TEJ. */
+static void do_bxj PARAMS ((char *));
+
/* Coprocessor Instructions. */
static void do_cdp PARAMS ((char *));
static void do_lstc PARAMS ((char *));
@@ -1105,7 +1110,7 @@ static const struct asm_opcode insns[] =
not support Thumb. */
{"bx", 0xe12fff10, 2, ARM_EXT_V4T | ARM_EXT_V5, do_bx},
- /* ARM Architecture 5. */
+ /* ARM Architecture 5T. */
/* Note: blx has 2 variants, so the .value is set dynamically.
Only one of the variants has conditional execution. */
{"blx", 0xe0000000, 3, ARM_EXT_V5, do_blx},
@@ -1119,7 +1124,7 @@ static const struct asm_opcode insns[] =
{"mcr2", 0xfe000010, 0, ARM_EXT_V5, do_co_reg2},
{"mrc2", 0xfe100010, 0, ARM_EXT_V5, do_co_reg2},
- /* ARM Architecture 5ExP. */
+ /* ARM Architecture 5TExP. */
{"smlabb", 0xe1000080, 6, ARM_EXT_V5ExP, do_smla},
{"smlatb", 0xe10000a0, 6, ARM_EXT_V5ExP, do_smla},
{"smlabt", 0xe10000c0, 6, ARM_EXT_V5ExP, do_smla},
@@ -1146,7 +1151,7 @@ static const struct asm_opcode insns[] =
{"qsub", 0xe1200050, 4, ARM_EXT_V5ExP, do_qadd},
{"qdsub", 0xe1600050, 5, ARM_EXT_V5ExP, do_qadd},
- /* ARM Architecture 5E. */
+ /* ARM Architecture 5TE. */
{"pld", 0xf450f000, 0, ARM_EXT_V5E, do_pld},
{"ldrd", 0xe00000d0, 3, ARM_EXT_V5E, do_ldrd},
{"strd", 0xe00000f0, 3, ARM_EXT_V5E, do_ldrd},
@@ -1154,6 +1159,9 @@ static const struct asm_opcode insns[] =
{"mcrr", 0xec400000, 4, ARM_EXT_V5E, do_co_reg2c},
{"mrrc", 0xec500000, 4, ARM_EXT_V5E, do_co_reg2c},
+ /* ARM Architecture 5TEJ. */
+ {"bxj", 0xe12fff20, 3, ARM_EXT_V5J, do_bxj},
+
/* Core FPA instruction set (V1). */
{"wfs", 0xee200110, 3, FPU_FPA_EXT_V1, do_fpa_ctrl},
{"rfs", 0xee300110, 3, FPU_FPA_EXT_V1, do_fpa_ctrl},
@@ -3876,6 +3884,28 @@ do_co_reg2 (str)
end_of_line (str);
}
+/* ARM v5TEJ. Jump to Jazelle code. */
+static void
+do_bxj (str)
+ char * str;
+{
+ int reg;
+
+ skip_whitespace (str);
+
+ if ((reg = reg_required_here (&str, 0)) == FAIL)
+ {
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ /* Note - it is not illegal to do a "bxj pc". Useless, but not illegal. */
+ if (reg == REG_PC)
+ as_tsktsk (_("use of r15 in bxj is not really useful"));
+
+ end_of_line (str);
+}
+
/* THUMB V5 breakpoint instruction (argument parse)
BKPT <immed_8>. */
@@ -10741,6 +10771,7 @@ static struct arm_cpu_option_table arm_cpus[] =
should really set the FPU type explicitly. */
{"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2},
{"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
+ {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
{"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2},
{"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
{"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2},
@@ -10785,6 +10816,7 @@ static struct arm_arch_option_table arm_archs[] =
{"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP},
{"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP},
{"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP},
+ {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP},
{"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP},
{NULL, 0, 0}
};
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index db08e51..a26c5ae 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,4 +1,10 @@
2002-01-18 Richard Earnshaw <rearnsha@arm.com>
+ Keith Walker <keith.walker@arm.com>
+
+ * gas/arm/arch5tej.s gas/arm/arch5tej.d: New files.
+ * gas/arm/arm.exp (arch5tej): New dump test.
+
+2002-01-18 Richard Earnshaw <rearnsha@arm.com>
* gas/arm/vfp1.d: Use new command-line options.
* gas/arm/vfp1xD.d: Likewise.
diff --git a/gas/testsuite/gas/arm/arch5tej.d b/gas/testsuite/gas/arm/arch5tej.d
new file mode 100644
index 0000000..a4bcdde
--- /dev/null
+++ b/gas/testsuite/gas/arm/arch5tej.d
@@ -0,0 +1,15 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: ARM Architecture v5TEJ instructions
+#as: -march=armv5tej
+
+# Test the ARM Architecture v5TEJ instructions
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+00 <[^>]*> e12fff20 ? bxj r0
+0+04 <[^>]*> e12fff21 ? bxj r1
+0+08 <[^>]*> e12fff2e ? bxj lr
+0+0c <[^>]*> 012fff20 ? bxjeq r0
+0+10 <[^>]*> 412fff20 ? bxjmi r0
+0+14 <[^>]*> 512fff27 ? bxjpl r7
diff --git a/gas/testsuite/gas/arm/arch5tej.s b/gas/testsuite/gas/arm/arch5tej.s
new file mode 100644
index 0000000..f4735ff
--- /dev/null
+++ b/gas/testsuite/gas/arm/arch5tej.s
@@ -0,0 +1,9 @@
+ .text
+ .align 0
+label:
+ bxj r0
+ bxj r1
+ bxj r14
+ bxjeq r0
+ bxjmi r0
+ bxjpl r7
diff --git a/gas/testsuite/gas/arm/arm.exp b/gas/testsuite/gas/arm/arm.exp
index 4faa8ce..0f6d8f0 100644
--- a/gas/testsuite/gas/arm/arm.exp
+++ b/gas/testsuite/gas/arm/arm.exp
@@ -35,6 +35,8 @@ if {[istarget *arm*-*-*] || [istarget "xscale-*-*"]} then {
gas_test "arch4t.s" "-marmv4t" $stdoptlist "Arm architecture 4t instructions"
+ run_dump_test "arch5tej"
+
gas_test "copro.s" "" $stdoptlist "Co processor instructions"
gas_test "immed.s" "" $stdoptlist "immediate expressions"
generated by cgit v1.1 at 2024-12-01 11:07:01 +0000