diff options
| -rw-r--r-- | gas/ChangeLog | 5 | ||||
| -rw-r--r-- | gas/config/tc-microblaze.c | 7 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/microblaze-dis.c | 4 | ||||
| -rw-r--r-- | opcodes/microblaze-opc.h | 10 |
5 files changed, 21 insertions, 11 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index a419017..5ce145f 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2012-11-29 David Holsgrove <david.holsgrove@xilinx.com> + + * config/tc-microblaze.c: Rename INST_TYPE_RD_R1_SPECIAL to + INST_TYPE_R1_R2_SPECIAL, don't set RD for wic. + 2012-11-28 Julian Brown <julian@codesourcery.com> * config/tc-arm.c (md_apply_fix): Fix conversion of BL to BLX for diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c index 5a427a0..e9c7846 100644 --- a/gas/config/tc-microblaze.c +++ b/gas/config/tc-microblaze.c @@ -1358,16 +1358,16 @@ md_assemble (char * str) output = frag_more (isize); break; - case INST_TYPE_RD_R1_SPECIAL: + case INST_TYPE_R1_R2_SPECIAL: if (strcmp (op_end, "")) - op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ + op_end = parse_reg (op_end + 1, ®1); /* Get r1. */ else { as_fatal (_("Error in statement syntax")); reg1 = 0; } if (strcmp (op_end, "")) - op_end = parse_reg (op_end + 1, ®2); /* Get r1. */ + op_end = parse_reg (op_end + 1, ®2); /* Get r2. */ else { as_fatal (_("Error in statement syntax")); @@ -1381,7 +1381,6 @@ md_assemble (char * str) as_fatal (_("Cannot use special register with this instruction")); /* insn wic ra, rb => wic ra, ra, rb. */ - inst |= (reg1 << RD_LOW) & RD_MASK; inst |= (reg1 << RA_LOW) & RA_MASK; inst |= (reg2 << RB_LOW) & RB_MASK; diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 8a4634d..c367b15 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2012-11-29 David Holsgrove <david.holsgrove@xilinx.com> + + * microblaze-opc.h: Rename INST_TYPE_RD_R1_SPECIAL to + INST_TYPE_R1_R2_SPECIAL + * microblaze-dis.c (print_insn_microblaze): Same. + 2012-11-23 Alan Modra <amodra@gmail.com> * ppc-dis.c (ppc_parse_cpu): Add "sticky" param. Track bits diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c index 7e3a546..bf028c4 100644 --- a/opcodes/microblaze-dis.c +++ b/opcodes/microblaze-dis.c @@ -383,8 +383,8 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) case INST_TYPE_R1: print_func (stream, "\t%s", get_field_r1 (inst)); break; - case INST_TYPE_RD_R1_SPECIAL: - print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_r2 (inst)); + case INST_TYPE_R1_R2_SPECIAL: + print_func (stream, "\t%s, %s", get_field_r1 (inst), get_field_r2 (inst)); break; case INST_TYPE_RD_IMM15: print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_imm15 (inst)); diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h index 404985b..e9da12a 100644 --- a/opcodes/microblaze-opc.h +++ b/opcodes/microblaze-opc.h @@ -45,7 +45,7 @@ #define INST_TYPE_R1_RFSL 15 /* New insn type for insn cache. */ -#define INST_TYPE_RD_R1_SPECIAL 16 +#define INST_TYPE_R1_R2_SPECIAL 16 /* New insn type for msrclr, msrset insns. */ #define INST_TYPE_RD_IMM15 17 @@ -171,10 +171,10 @@ struct op_code_struct {"srl", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000041, OPCODE_MASK_H34, srl, logical_inst }, {"sext8", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000060, OPCODE_MASK_H34, sext8, logical_inst }, {"sext16",INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000061, OPCODE_MASK_H34, sext16, logical_inst }, - {"wic", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst }, - {"wdc", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst }, - {"wdc.clear", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst }, - {"wdc.flush", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst }, + {"wic", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst }, + {"wdc", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst }, + {"wdc.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst }, + {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst }, {"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst }, {"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst }, {"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst }, |