diff options
| -rw-r--r-- | gas/ChangeLog | 6 | ||||
| -rw-r--r-- | gas/config/tc-aarch64.c | 2 | ||||
| -rw-r--r-- | gas/doc/c-aarch64.texi | 2 | ||||
| -rw-r--r-- | include/ChangeLog | 4 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 2 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/aarch64-tbl.h | 5 |
7 files changed, 26 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index aafc95c..2986f0d 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,9 @@ +2018-11-12 Sudakshina Das <sudi.das@arm.com> + + * config/tc-aarch64.c (aarch64_features): Add "memtag" + as a new option. + * doc/c-aarch64.texi: Document the same. + 2018-11-09 Alan Modra <amodra@gmail.com> * config/tc-ppc.c (fixup_size): New function. diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 4ae27f7..b9aceb2 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -8829,6 +8829,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { AARCH64_ARCH_NONE}, {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS, 0), AARCH64_ARCH_NONE}, + {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG, 0), + AARCH64_ARCH_NONE}, {NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE}, }; diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index 4941c57..f38fdf5 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -189,6 +189,8 @@ automatically cause those extensions to be disabled. @tab Enable ARMv8.5-A random number instructions. @item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later @tab Enable Speculative Store Bypassing Safe state read and write. +@item @code{memtag} @tab ARMv8.5-A @tab No + @tab Enable ARMv8.5-A Memory Tagging Extensions. @end multitable @node AArch64 Syntax diff --git a/include/ChangeLog b/include/ChangeLog index cd31f1c..08057ef 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,7 @@ +2018-11-12 Sudakshina Das <sudi.das@arm.com> + + * opcode/aarch64.h (AARCH64_FEATURE_MEMTAG): New. + 2018-11-07 Roman Bolshakov <r.bolshakov@yadro.com> Saagar Jha <saagar@saagarjha.com> diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 8487767..813c36a 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -84,6 +84,8 @@ typedef uint32_t aarch64_insn; #define AARCH64_FEATURE_ID_PFR2 0x400000000000ULL /* SSBS mechanism enabled. */ #define AARCH64_FEATURE_SSBS 0x800000000000ULL +/* Memory Tagging Extension. */ +#define AARCH64_FEATURE_MEMTAG 0x1000000000000ULL /* Architectures are the sum of the base and extensions. */ diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index bac6294..4fc11f7 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2018-11-12 Sudakshina Das <sudi.das@arm.com> + + * aarch64-tbl.h (aarch64_feature_memtag): New. + (MEMTAG, MEMTAG_INSN): New. + 2018-11-06 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (select_arm_features): Update bfd_mach_arm_8 diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index b73007d..5a4eaea 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2171,6 +2171,8 @@ static const aarch64_feature_set aarch64_feature_predres = AARCH64_FEATURE (AARCH64_FEATURE_PREDRES, 0); static const aarch64_feature_set aarch64_feature_bti = AARCH64_FEATURE (AARCH64_FEATURE_BTI, 0); +static const aarch64_feature_set aarch64_feature_memtag = + AARCH64_FEATURE (AARCH64_FEATURE_V8_5 | AARCH64_FEATURE_MEMTAG, 0); #define CORE &aarch64_feature_v8 @@ -2205,6 +2207,7 @@ static const aarch64_feature_set aarch64_feature_bti = #define SB &aarch64_feature_sb #define PREDRES &aarch64_feature_predres #define BTI &aarch64_feature_bti +#define MEMTAG &aarch64_feature_memtag #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } @@ -2268,6 +2271,8 @@ static const aarch64_feature_set aarch64_feature_bti = { NAME, OPCODE, MASK, CLASS, 0, PREDRES, OPS, QUALS, FLAGS, 0, 0, NULL } #define BTI_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, BTI, OPS, QUALS, FLAGS, 0, 0, NULL } +#define MEMTAG_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, CLASS, 0, MEMTAG, OPS, QUALS, FLAGS, 0, 0, NULL } struct aarch64_opcode aarch64_opcode_table[] = { |