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-rw-r--r--opcodes/ChangeLog5
-rw-r--r--opcodes/m32r-asm.c21
-rw-r--r--opcodes/m32r-desc.c6
-rw-r--r--opcodes/m32r-desc.h14
-rw-r--r--opcodes/m32r-dis.c8
-rw-r--r--opcodes/m32r-ibld.c23
-rw-r--r--opcodes/m32r-opc.h1
7 files changed, 54 insertions, 24 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 7ab14ee..9726b03 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2000-02-23 Andrew Haley <aph@cygnus.com>
+
+ * m32r-asm.c, m32r-desc.c, m32r-desc.h, m32r-dis.c,
+ m32r-ibld.c,m32r-opc.h: Rebuild.
+
2000-02-23 Linas Vepstas <linas@linas.org>
* i370-dis.c, i370-opc.c: New.
diff --git a/opcodes/m32r-asm.c b/opcodes/m32r-asm.c
index 2d3bd96..0aa62ce 100644
--- a/opcodes/m32r-asm.c
+++ b/opcodes/m32r-asm.c
@@ -486,6 +486,7 @@ m32r_cgen_assemble_insn (cd, str, fields, buf, errmsg)
{
const char *start;
CGEN_INSN_LIST *ilist;
+ const char *tmp_errmsg;
/* Skip leading white space. */
while (isspace (* str))
@@ -502,7 +503,8 @@ m32r_cgen_assemble_insn (cd, str, fields, buf, errmsg)
{
const CGEN_INSN *insn = ilist->insn;
-#if 0 /* not needed as unsupported opcodes shouldn't be in the hash lists */
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* not usually needed as unsupported opcodes shouldn't be in the hash lists */
/* Is this insn supported by the selected cpu? */
if (! m32r_cgen_insn_supported (cd, insn))
continue;
@@ -519,7 +521,7 @@ m32r_cgen_assemble_insn (cd, str, fields, buf, errmsg)
/* Allow parse/insert handlers to obtain length of insn. */
CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
- if (! CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields))
+ if (!(tmp_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields)))
{
/* ??? 0 is passed for `pc' */
if (CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, (bfd_vma) 0)
@@ -533,16 +535,25 @@ m32r_cgen_assemble_insn (cd, str, fields, buf, errmsg)
/* Try the next entry. */
}
- /* FIXME: We can return a better error message than this.
- Need to track why it failed and pick the right one. */
{
- static char errbuf[100];
+ static char errbuf[150];
+
+#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS
+ /* if verbose error messages, use errmsg from CGEN_PARSE_FN */
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
+ else
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
+#else
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s...'"), start);
else
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s'"), start);
+#endif
*errmsg = errbuf;
return NULL;
diff --git a/opcodes/m32r-desc.c b/opcodes/m32r-desc.c
index ee1cfa9..1502e74 100644
--- a/opcodes/m32r-desc.c
+++ b/opcodes/m32r-desc.c
@@ -252,6 +252,7 @@ const CGEN_HW_ENTRY m32r_cgen_hw_table[] =
const CGEN_IFLD m32r_cgen_ifld_table[] =
{
{ M32R_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
+ { M32R_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
{ M32R_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { (1<<MACH_BASE) } } },
{ M32R_F_OP2, "f-op2", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } },
{ M32R_F_COND, "f-cond", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } } },
@@ -1015,7 +1016,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
/* pcmpbz $src2 */
{
M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz", 16,
- { 0, { (1<<MACH_M32RX), PIPE_OS } }
+ { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_OS } }
},
/* sadd */
{
@@ -1337,6 +1338,9 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
cd->rebuild_tables = m32r_cgen_rebuild_tables;
m32r_cgen_rebuild_tables (cd);
+ /* Initialise flags. */
+ cd->flags = 0;
+
return (CGEN_CPU_DESC) cd;
}
diff --git a/opcodes/m32r-desc.h b/opcodes/m32r-desc.h
index 6a0fac6..7d42807 100644
--- a/opcodes/m32r-desc.h
+++ b/opcodes/m32r-desc.h
@@ -133,13 +133,13 @@ typedef enum cgen_ifld_attr {
/* Enum declaration for m32r ifield types. */
typedef enum ifield_type {
- M32R_F_NIL, M32R_F_OP1, M32R_F_OP2, M32R_F_COND
- , M32R_F_R1, M32R_F_R2, M32R_F_SIMM8, M32R_F_SIMM16
- , M32R_F_SHIFT_OP2, M32R_F_UIMM4, M32R_F_UIMM5, M32R_F_UIMM16
- , M32R_F_UIMM24, M32R_F_HI16, M32R_F_DISP8, M32R_F_DISP16
- , M32R_F_DISP24, M32R_F_OP23, M32R_F_OP3, M32R_F_ACC
- , M32R_F_ACCS, M32R_F_ACCD, M32R_F_BITS67, M32R_F_BIT14
- , M32R_F_IMM1, M32R_F_MAX
+ M32R_F_NIL, M32R_F_ANYOF, M32R_F_OP1, M32R_F_OP2
+ , M32R_F_COND, M32R_F_R1, M32R_F_R2, M32R_F_SIMM8
+ , M32R_F_SIMM16, M32R_F_SHIFT_OP2, M32R_F_UIMM4, M32R_F_UIMM5
+ , M32R_F_UIMM16, M32R_F_UIMM24, M32R_F_HI16, M32R_F_DISP8
+ , M32R_F_DISP16, M32R_F_DISP24, M32R_F_OP23, M32R_F_OP3
+ , M32R_F_ACC, M32R_F_ACCS, M32R_F_ACCD, M32R_F_BITS67
+ , M32R_F_BIT14, M32R_F_IMM1, M32R_F_MAX
} IFIELD_TYPE;
#define MAX_IFLD ((int) M32R_F_MAX)
diff --git a/opcodes/m32r-dis.c b/opcodes/m32r-dis.c
index f880784..d6d5377 100644
--- a/opcodes/m32r-dis.c
+++ b/opcodes/m32r-dis.c
@@ -421,10 +421,14 @@ print_insn (cd, pc, info, buf, buflen)
CGEN_FIELDS fields;
int length;
-#if 0 /* not needed as insn shouldn't be in hash lists if not supported */
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* not needed as insn shouldn't be in hash lists if not supported */
/* Supported by this cpu? */
if (! m32r_cgen_insn_supported (cd, insn))
- continue;
+ {
+ insn_list = CGEN_DIS_NEXT_INSN (insn_list);
+ continue;
+ }
#endif
/* Basic bit mask must be correct. */
diff --git a/opcodes/m32r-ibld.c b/opcodes/m32r-ibld.c
index 48dc73f..30c3c6a 100644
--- a/opcodes/m32r-ibld.c
+++ b/opcodes/m32r-ibld.c
@@ -3,7 +3,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
- the resultant file is machine generated, cgen-ibld.in isn't
-Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
@@ -203,6 +203,7 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length,
if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
{
unsigned long maxval = mask;
+
if ((unsigned long) value > maxval)
{
/* xgettext:c-format */
@@ -214,15 +215,19 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length,
}
else
{
- long minval = - (1L << (length - 1));
- long maxval = (1L << (length - 1)) - 1;
- if (value < minval || value > maxval)
+ if (! cgen_signed_overflow_ok_p (cd))
{
- sprintf
- /* xgettext:c-format */
- (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
- value, minval, maxval);
- return errbuf;
+ long minval = - (1L << (length - 1));
+ long maxval = (1L << (length - 1)) - 1;
+
+ if (value < minval || value > maxval)
+ {
+ sprintf
+ /* xgettext:c-format */
+ (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
+ value, minval, maxval);
+ return errbuf;
+ }
}
}
diff --git a/opcodes/m32r-opc.h b/opcodes/m32r-opc.h
index f92a332..b98c5f9 100644
--- a/opcodes/m32r-opc.h
+++ b/opcodes/m32r-opc.h
@@ -88,6 +88,7 @@ struct cgen_fields
{
int length;
long f_nil;
+ long f_anyof;
long f_op1;
long f_op2;
long f_cond;
generated by cgit v1.1 at 2024-11-22 15:23:31 +0000