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-rw-r--r--bfd/ChangeLog4
-rw-r--r--bfd/elfxx-mips.c2
-rw-r--r--binutils/ChangeLog4
-rw-r--r--binutils/readelf.c2
-rw-r--r--gas/ChangeLog18
-rw-r--r--gas/config/tc-mips.c16
-rw-r--r--gas/doc/as.texinfo10
-rw-r--r--gas/doc/c-mips.texi18
-rw-r--r--gas/testsuite/gas/mips/mips.exp1
-rw-r--r--gas/testsuite/gas/mips/mips32-dspr3.d22
-rw-r--r--gas/testsuite/gas/mips/mips32-dspr3.s12
-rw-r--r--include/ChangeLog6
-rw-r--r--include/elf/mips.h3
-rw-r--r--include/opcode/mips.h1
-rw-r--r--opcodes/ChangeLog7
-rw-r--r--opcodes/mips-dis.c4
-rw-r--r--opcodes/mips-opc.c2
17 files changed, 126 insertions, 6 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 25d1db6..333b882 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,7 @@
+2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
+
+ * elfxx-mips.c (print_mips_ases): Add DSPR3.
+
2016-05-11 Alan Modra <amodra@gmail.com>
* elf32-hppa.c (elf32_hppa_init_stub_bfd): New function.
diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index 3c2de4e..f9e8f76 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -15565,6 +15565,8 @@ print_mips_ases (FILE *file, unsigned int mask)
fputs ("\n\tDSP ASE", file);
if (mask & AFL_ASE_DSPR2)
fputs ("\n\tDSP R2 ASE", file);
+ if (mask & AFL_ASE_DSPR3)
+ fputs ("\n\tDSP R3 ASE", file);
if (mask & AFL_ASE_EVA)
fputs ("\n\tEnhanced VA Scheme", file);
if (mask & AFL_ASE_MCU)
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index bed9119..9170c00 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,7 @@
+2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
+
+ * readelf.c (print_mips_ases): Add DSPR3.
+
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
* readelf.c (display_arm_attribute): Add output for Tag_DSP_extension.
diff --git a/binutils/readelf.c b/binutils/readelf.c
index 0935507..61f2939 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -14229,6 +14229,8 @@ print_mips_ases (unsigned int mask)
fputs ("\n\tDSP ASE", stdout);
if (mask & AFL_ASE_DSPR2)
fputs ("\n\tDSP R2 ASE", stdout);
+ if (mask & AFL_ASE_DSPR3)
+ fputs ("\n\tDSP R3 ASE", stdout);
if (mask & AFL_ASE_EVA)
fputs ("\n\tEnhanced VA Scheme", stdout);
if (mask & AFL_ASE_MCU)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 6a059e7..22558dd 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,21 @@
+2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
+ Matthew Fortune <matthew.fortune@imgtec.com>
+
+ * config/tc-mips.c (options): Add OPTION_DSPR3 and
+ OPTION_NO_DSPR3.
+ (md_longopts): Likewise.
+ (md_show_usage): Add help for -mdspr3 and -mno-dspr3.
+ (mips_ases): Define availability for DSPr3.
+ (mips_ase_groups): Add ASE_DSPR3 to the DSP group.
+ (mips_convert_ase_flags): Map ASE_DSPR3 to AFL_ASE_DSPR3.
+ * doc/as.texinfo: Document -mdspr3, -mno-dspr3. Fix -mdspr2
+ formatting.
+ * doc/c-mips.texi: Document -mdspr3, -mno-dspr3, .set dspr3 and
+ .set nodspr3. Fix -mdspr2 formatting.
+ * testsuite/gas/mips/mips32-dspr3.d: New file.
+ * testsuite/gas/mips/mips32-dspr3.s: Likewise.
+ * testsuite/gas/mips/mips.exp: Run mips32-dspr3 test.
+
2016-05-11 Nick Clifton <nickc@redhat.com>
PR target/20068
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index daceef1..b538ff0 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -1410,6 +1410,8 @@ enum options
OPTION_NO_SMARTMIPS,
OPTION_DSPR2,
OPTION_NO_DSPR2,
+ OPTION_DSPR3,
+ OPTION_NO_DSPR3,
OPTION_EVA,
OPTION_NO_EVA,
OPTION_XPA,
@@ -1522,6 +1524,8 @@ struct option md_longopts[] =
{"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
{"mdspr2", no_argument, NULL, OPTION_DSPR2},
{"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
+ {"mdspr3", no_argument, NULL, OPTION_DSPR3},
+ {"mno-dspr3", no_argument, NULL, OPTION_NO_DSPR3},
{"meva", no_argument, NULL, OPTION_EVA},
{"mno-eva", no_argument, NULL, OPTION_NO_EVA},
{"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
@@ -1663,6 +1667,11 @@ static const struct mips_ase mips_ases[] = {
2, 2, 2, 2,
-1 },
+ { "dspr3", ASE_DSP | ASE_DSPR2 | ASE_DSPR3, 0,
+ OPTION_DSPR3, OPTION_NO_DSPR3,
+ 6, 6, -1, -1,
+ -1 },
+
{ "eva", ASE_EVA, 0,
OPTION_EVA, OPTION_NO_EVA,
2, 2, 2, 2,
@@ -1716,7 +1725,7 @@ static const struct mips_ase mips_ases[] = {
/* Groups of ASE_* flags that represent different revisions of an ASE. */
static const unsigned int mips_ase_groups[] = {
- ASE_DSP | ASE_DSPR2
+ ASE_DSP | ASE_DSPR2 | ASE_DSPR3
};
/* Pseudo-op table.
@@ -17954,6 +17963,8 @@ mips_convert_ase_flags (int ase)
ext_ases |= AFL_ASE_DSP;
if (ase & ASE_DSPR2)
ext_ases |= AFL_ASE_DSPR2;
+ if (ase & ASE_DSPR3)
+ ext_ases |= AFL_ASE_DSPR3;
if (ase & ASE_EVA)
ext_ases |= AFL_ASE_EVA;
if (ase & ASE_MCU)
@@ -18963,6 +18974,9 @@ MIPS options:\n\
-mdspr2 generate DSP R2 instructions\n\
-mno-dspr2 do not generate DSP R2 instructions\n"));
fprintf (stream, _("\
+-mdspr3 generate DSP R3 instructions\n\
+-mno-dspr3 do not generate DSP R3 instructions\n"));
+ fprintf (stream, _("\
-mmt generate MT instructions\n\
-mno-mt do not generate MT instructions\n"));
fprintf (stream, _("\
diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index e2e744e..1cd60ed 100644
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -424,6 +424,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
[@b{-mdmx}] [@b{-no-mdmx}]
[@b{-mdsp}] [@b{-mno-dsp}]
[@b{-mdspr2}] [@b{-mno-dspr2}]
+ [@b{-mdspr3}] [@b{-mno-dspr3}]
[@b{-mmsa}] [@b{-mno-msa}]
[@b{-mxpa}] [@b{-mno-xpa}]
[@b{-mmt}] [@b{-mno-mt}]
@@ -1438,10 +1439,17 @@ This tells the assembler to accept DSP Release 1 instructions.
@item -mdspr2
@itemx -mno-dspr2
Generate code for the DSP Release 2 Application Specific Extension.
-This option implies -mdsp.
+This option implies @samp{-mdsp}.
This tells the assembler to accept DSP Release 2 instructions.
@samp{-mno-dspr2} turns off this option.
+@item -mdspr3
+@itemx -mno-dspr3
+Generate code for the DSP Release 3 Application Specific Extension.
+This option implies @samp{-mdsp} and @samp{-mdspr2}.
+This tells the assembler to accept DSP Release 3 instructions.
+@samp{-mno-dspr3} turns off this option.
+
@item -mmsa
@itemx -mno-msa
Generate code for the MIPS SIMD Architecture Extension.
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 30544db..5fa64cb 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -187,10 +187,17 @@ This tells the assembler to accept DSP Release 1 instructions.
@item -mdspr2
@itemx -mno-dspr2
Generate code for the DSP Release 2 Application Specific Extension.
-This option implies -mdsp.
+This option implies @samp{-mdsp}.
This tells the assembler to accept DSP Release 2 instructions.
@samp{-mno-dspr2} turns off this option.
+@item -mdspr3
+@itemx -mno-dspr3
+Generate code for the DSP Release 3 Application Specific Extension.
+This option implies @samp{-mdsp} and @samp{-mdspr2}.
+This tells the assembler to accept DSP Release 3 instructions.
+@samp{-mno-dspr3} turns off this option.
+
@item -mmt
@itemx -mno-mt
Generate code for the MT Application Specific Extension.
@@ -1007,6 +1014,15 @@ on in the assembly. This directive implies @code{.set dsp}. The
@code{.set nodspr2} directive prevents DSP Release 2 instructions from
being accepted.
+@cindex MIPS DSP Release 3 instruction generation override
+@kindex @code{.set dspr3}
+@kindex @code{.set nodspr3}
+The directive @code{.set dspr3} makes the assembler accept instructions
+from the DSP Release 3 Application Specific Extension from that point
+on in the assembly. This directive implies @code{.set dsp} and
+@code{.set dspr2}. The @code{.set nodspr3} directive prevents DSP
+Release 3 instructions from being accepted.
+
@cindex MIPS MT instruction generation override
@kindex @code{.set mt}
@kindex @code{.set nomt}
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 8ee0b31..88d15c8 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -1153,6 +1153,7 @@ if { [istarget mips*-*-vxworks*] } {
!octeon]
run_dump_test_arches "mips32-dspr2" [mips_arch_list_matching mips32r2 \
!octeon]
+ run_dump_test_arches "mips32-dspr3" [mips_arch_list_matching mips32r6]
run_dump_test "mips64-dsp"
run_dump_test "mips32-mt"
diff --git a/gas/testsuite/gas/mips/mips32-dspr3.d b/gas/testsuite/gas/mips/mips32-dspr3.d
new file mode 100644
index 0000000..28b093a
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips32-dspr3.d
@@ -0,0 +1,22 @@
+#objdump: -pdr --prefix-addresses --show-raw-insn
+#name: MIPS DSP ASE Rev3 for MIPS32
+#as: -mdspr3 -32
+
+# Check MIPS DSP ASE Rev3 for MIPS32 Instruction Assembly
+
+.*: +file format .*mips.*
+#...
+ASEs:
+#...
+ DSP ASE
+ DSP R2 ASE
+ DSP R3 ASE
+#...
+FLAGS 1: .*
+FLAGS 2: .*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 0418ffff bposge32c 00000000 <text_label>
+.*0: R_MIPS_PC16 text_label
+
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/mips32-dspr3.s b/gas/testsuite/gas/mips/mips32-dspr3.s
new file mode 100644
index 0000000..691bb95
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips32-dspr3.s
@@ -0,0 +1,12 @@
+# source file to test assembly of MIPS DSP ASE Rev3 for MIPS32 instructions
+
+ .set noreorder
+ .set noat
+
+ .text
+text_label:
+ bposge32c text_label
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
diff --git a/include/ChangeLog b/include/ChangeLog
index 3d17849..af061b4 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,9 @@
+2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
+
+ * elf/mips.h (AFL_ASE_DSPR3): New macro.
+ (AFL_ASE_MASK): Update to include AFL_ASE_DSPR3.
+ * opcode/mips.h (ASE_DSPR3): New macro.
+
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
Nick Clifton <nickc@redhat.com>
diff --git a/include/elf/mips.h b/include/elf/mips.h
index 46f63fe..70ea43e 100644
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -1227,7 +1227,8 @@ extern void bfd_mips_elf_swap_abiflags_v0_out
#define AFL_ASE_MIPS16 0x00000400 /* MIPS16 ASE. */
#define AFL_ASE_MICROMIPS 0x00000800 /* MICROMIPS ASE. */
#define AFL_ASE_XPA 0x00001000 /* XPA ASE. */
-#define AFL_ASE_MASK 0x00001fff /* All ASEs. */
+#define AFL_ASE_DSPR3 0x00002000 /* DSP R3 ASE. */
+#define AFL_ASE_MASK 0x00003fff /* All ASEs. */
/* Values for the isa_ext word of an ABI flags structure. */
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 88bf8f8..0af3ed5 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -1256,6 +1256,7 @@ static const unsigned int mips_isa_table[] = {
#define ASE_MSA64 0x00001000
/* eXtended Physical Address (XPA) Extension. */
#define ASE_XPA 0x00002000
+#define ASE_DSPR3 0x00004000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 89ea01a..da823ac 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
+
+ * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
+ mips64r6.
+ * mips-opc.c (D34): New macro.
+ (mips_builtin_opcodes): Define bposge32c for DSPr3.
+
2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
* i386-dis.c (prefix_table): Add RDPID instruction.
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 7822295..535c14a 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -563,7 +563,7 @@ const struct mips_arch_choice mips_arch_choices[] =
{ "mips32r6", 1, bfd_mach_mipsisa32r6, CPU_MIPS32R6,
ISA_MIPS32R6,
(ASE_EVA | ASE_MSA | ASE_VIRT | ASE_XPA | ASE_MCU | ASE_MT | ASE_DSP
- | ASE_DSPR2),
+ | ASE_DSPR2 | ASE_DSPR3),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
@@ -602,7 +602,7 @@ const struct mips_arch_choice mips_arch_choices[] =
{ "mips64r6", 1, bfd_mach_mipsisa64r6, CPU_MIPS64R6,
ISA_MIPS64R6,
(ASE_EVA | ASE_MSA | ASE_MSA64 | ASE_XPA | ASE_VIRT | ASE_VIRT64
- | ASE_MCU | ASE_MT | ASE_DSP | ASE_DSPR2),
+ | ASE_MCU | ASE_MT | ASE_DSP | ASE_DSPR2 | ASE_DSPR3),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 79a8417..a95eff1 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -374,6 +374,7 @@ decode_mips_operand (const char *p)
#define DSP_VOLA INSN_NO_DELAY_SLOT
#define D32 ASE_DSP
#define D33 ASE_DSPR2
+#define D34 ASE_DSPR3
#define D64 ASE_DSP64
/* MIPS MT ASE support. */
@@ -2149,6 +2150,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"addwc", "d,s,t", 0x7c000450, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 },
{"bitrev", "d,t", 0x7c0006d2, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 },
{"bposge32", "p", 0x041c0000, 0xffff0000, CBD, 0, 0, D32, 0 },
+{"bposge32c", "p", 0x04180000, 0xffff0000, NODS, FS, 0, D34, 0 },
{"bposge64", "p", 0x041d0000, 0xffff0000, CBD, 0, 0, D64, 0 },
{"cmp.eq.ph", "s,t", 0x7c000211, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 },
{"cmp.eq.pw", "s,t", 0x7c000415, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 },
generated by cgit v1.1 at 2024-11-25 18:09:36 +0000