aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--sim/testsuite/mips64vr5900el-elf/ChangeLog4
-rw-r--r--sim/testsuite/mips64vr5900el-elf/t-pdivuw.s14
2 files changed, 18 insertions, 0 deletions
diff --git a/sim/testsuite/mips64vr5900el-elf/ChangeLog b/sim/testsuite/mips64vr5900el-elf/ChangeLog
index 03f5fbb..a6ad061 100644
--- a/sim/testsuite/mips64vr5900el-elf/ChangeLog
+++ b/sim/testsuite/mips64vr5900el-elf/ChangeLog
@@ -1,3 +1,7 @@
+Mon Jul 28 20:51:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * t-pdivuw.s: Also check normal cases.
+
Tue Jul 15 13:34:07 1997 Andrew Cagney <cagney@sendai.cygnus.com>
ChangeLog: Create
diff --git a/sim/testsuite/mips64vr5900el-elf/t-pdivuw.s b/sim/testsuite/mips64vr5900el-elf/t-pdivuw.s
index 3391871..f183b9a 100644
--- a/sim/testsuite/mips64vr5900el-elf/t-pdivuw.s
+++ b/sim/testsuite/mips64vr5900el-elf/t-pdivuw.s
@@ -9,6 +9,20 @@ test_pdivuw:
checkHI 0x000000007fffffff 0xffffffff80000000
checkLO 0x0000000000000000 0x0000000000000000
+test_pdivuw1:
+ load $7 0x7fffffff00000000 0x80000000ffffffff
+ load $8 0xffffffffffffffff 0xffffffffffffffff
+ pdivuw $7,$8 #Expectation:
+ checkHI 0x0000000000000000 0x0000000000000000
+ checkLO 0x0000000000000000 0x0000000000000001
+
+test_pdivuw2:
+ load $7 0x0000000000001000 0x0000000000001fff
+ load $8 0x0000000000000100 0x0000000000000100
+ pdivuw $7,$8 #Expectation:
+ checkHI 0x0000000000000000 0x00000000000000ff
+ checkLO 0x0000000000000010 0x000000000000001f
+
test_pdivuw_0:
load $7 0x000000007fffffff 0xffffffff80000000
load $8 0x0000000000000000 0x0000000000000000