diff options
| -rw-r--r-- | gas/ChangeLog | 11 | ||||
| -rw-r--r-- | gas/config/tc-i386.c | 31 | ||||
| -rw-r--r-- | gas/testsuite/ChangeLog | 6 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/intelok.s | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/x86_64.s | 8 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/i386-opc.h | 2 | ||||
| -rw-r--r-- | opcodes/i386-reg.tbl | 1 | ||||
| -rw-r--r-- | opcodes/i386-tbl.h | 5 |
9 files changed, 57 insertions, 17 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 952ee07..cd82737 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,16 @@ 2008-02-13 Jan Beulich <jbeulich@novell.com> + * config/tc-i386.c (parse_real_register): Don't return 'FLAT' + if not in Intel mode. + (i386_intel_operand): Ignore segment overrides in immediate and + offset operands. + (intel_e11): Range-check i.mem_operands before use as array + index. Filter out FLAT for uses other than as segment override. + (intel_get_token): Remove broken promotion of "FLAT:" to mean + "offset FLAT:". + +2008-02-13 Jan Beulich <jbeulich@novell.com> + * config/tc-i386.c (intel_e09): Also special-case 'bound'. 2008-02-13 Jan Beulich <jbeulich@novell.com> diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index ccb46ae..cc5b200 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -7076,6 +7076,9 @@ parse_real_register (char *reg_string, char **end_op) && flag_code != CODE_64BIT) return (const reg_entry *) NULL; + if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax) + return (const reg_entry *) NULL; + return r; } @@ -8133,7 +8136,15 @@ i386_intel_operand (char *operand_string, int got_a_float) /* Constant and OFFSET expressions are handled by i386_immediate. */ else if ((intel_parser.op_modifier & (1 << T_OFFSET)) || intel_parser.reg == NULL) - ret = i386_immediate (intel_parser.disp); + { + if (i.mem_operands < 2 && i.seg[i.mem_operands]) + { + if (!(intel_parser.op_modifier & (1 << T_OFFSET))) + as_warn (_("Segment override ignored")); + i.seg[i.mem_operands] = NULL; + } + ret = i386_immediate (intel_parser.disp); + } if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1) ret = 0; @@ -8667,6 +8678,8 @@ intel_e11 (void) reg->reg_name); return 0; } + else if (i.mem_operands >= 2) + as_warn (_("Segment override ignored")); else if (i.seg[i.mem_operands]) as_warn (_("Extra segment override ignored")); else @@ -8697,6 +8710,12 @@ intel_e11 (void) } } + else if (reg->reg_type.bitfield.sreg3 && reg->reg_num == RegFlat) + { + as_bad (_("cannot use `FLAT' here")); + return 0; + } + /* Not a segment register. Check for register scaling. */ else if (cur_token.code == '*') { @@ -9088,16 +9107,6 @@ intel_get_token (void) strcat (new_token.str, " FLAT:"); } - /* ??? This is not mentioned in the MASM grammar. */ - else if (strcasecmp (new_token.str, "FLAT") == 0) - { - new_token.code = T_OFFSET; - if (*q == ':') - strcat (new_token.str, ":"); - else - as_bad (_("`:' expected")); - } - else new_token.code = T_ID; } diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index c924af1..da2e733 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,5 +1,11 @@ 2008-02-13 Jan Beulich <jbeulich@novell.com> + * gas/i386/intelok.s: Replace invalid offset expression with + valid ones. + * gas/i386/x86_64.s: Likewise. + +2008-02-13 Jan Beulich <jbeulich@novell.com> + * gas/i386/intelbad.s, gas/i386/intelok.s: Add 'bound' tests. * gas/i386/intelbad.l, gas/i386/intelok.l, gas/i386/intelok.e, gas/i386/opcode-intel.d: Adjust. diff --git a/gas/testsuite/gas/i386/intelok.s b/gas/testsuite/gas/i386/intelok.s index 5916b03..2f78929 100644 --- a/gas/testsuite/gas/i386/intelok.s +++ b/gas/testsuite/gas/i386/intelok.s @@ -168,10 +168,10 @@ start: mov eax, offset x mov eax, offset flat:x - mov eax, flat:x + mov eax, offset gs:x mov eax, offset [x] mov eax, offset flat:[x] - mov eax, flat:[x] + mov eax, offset gs:[x] mov eax, [offset x] mov eax, [eax + offset x] mov eax, [eax + offset 1] diff --git a/gas/testsuite/gas/i386/x86_64.s b/gas/testsuite/gas/i386/x86_64.s index 75d055a..34c8cdf 100644 --- a/gas/testsuite/gas/i386/x86_64.s +++ b/gas/testsuite/gas/i386/x86_64.s @@ -127,10 +127,10 @@ mov symbol(%rip), %eax .intel_syntax noprefix #immediates - various sizes: -mov al, flat:symbol -mov ax, flat:symbol -mov eax, flat:symbol -mov rax, flat:symbol +mov al, offset flat:symbol +mov ax, offset flat:symbol +mov eax, offset flat:symbol +mov rax, offset flat:symbol #parts aren't supported by the parser, yet (and not at all for symbol refs) #mov eax, high part symbol diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index a2d9646..d6a245a 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,11 @@ 2008-02-13 Jan Beulich <jbeulich@novell.com> + * i386-opc.h (RegFlat): New. + * i386-reg.tbl (flat): Add. + * i386-tbl.h: Re-generate. + +2008-02-13 Jan Beulich <jbeulich@novell.com> + * i386-dis.c (a_mode): New. (cond_jump_mode): Adjust. (Ma): Change to a_mode. diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 95c315b..d66f02b 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -501,6 +501,8 @@ typedef struct /* EIZ and RIZ are fake index registers. */ #define RegEiz (RegEip - 1) #define RegRiz (RegEiz - 1) +/* FLAT is a fake segment register (Intel mode). */ +#define RegFlat ((unsigned char) ~0) signed char dw2_regnum[2]; #define Dw2Inval (-1) } diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl index 11f2ee7..6aa89fc 100644 --- a/opcodes/i386-reg.tbl +++ b/opcodes/i386-reg.tbl @@ -103,6 +103,7 @@ ss, SReg2, 0, 2, 42, 52 ds, SReg2, 0, 3, 43, 53 fs, SReg3, 0, 4, 44, 54 gs, SReg3, 0, 5, 45, 55 +flat, SReg3, 0, RegFlat, Dw2Inval, Dw2Inval // Control registers. cr0, Control, 0, 0, Dw2Inval, Dw2Inval cr1, Control, 0, 1, Dw2Inval, Dw2Inval diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index 13ad14f..36399b5 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -17385,6 +17385,11 @@ const reg_entry i386_regtab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, 0, 5, { 45, 55 } }, + { "flat", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 } }, + 0, RegFlat, { Dw2Inval, Dw2Inval } }, { "cr0", { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |