diff options
| -rw-r--r-- | opcodes/ChangeLog | 10 | ||||
| -rw-r--r-- | opcodes/m10300-opc.c | 585 |
2 files changed, 550 insertions, 45 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 6be16b0..b960bcf 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,4 +1,14 @@ start-sanitize-am33 +Mon Jun 22 13:36:27 1998 Jeffrey A Law (law@cygnus.com) + + * m10300-opc.c: Support 4 byte DSP instructions. + +end-sanitize-am33 +Sat Jun 20 14:46:20 1998 Frank Ch. Eigler <fche@cygnus.com> + + * mips-dis.c (_print_insn_mips): Fix argument interchange typo. + +start-sanitize-am33 Fri Jun 19 16:47:06 1998 Jeffrey A Law (law@cygnus.com) * m10300-opc.c: Support 6 and 7 byte am33 instructions. diff --git a/opcodes/m10300-opc.c b/opcodes/m10300-opc.c index 2812d01..8e07bc6 100644 --- a/opcodes/m10300-opc.c +++ b/opcodes/m10300-opc.c @@ -235,19 +235,19 @@ const struct mn10300_operand mn10300_operands[] = { #define EPSW (IMM4+1) {0, 0, MN10300_OPERAND_EPSW}, -/* rn register in the third register operand position. */ +/* rn register in the first register operand position. */ #define RN0 (EPSW+1) {4, 0, MN10300_OPERAND_RREG}, -/* rn register in the third register operand position. */ +/* rn register in the fourth register operand position. */ #define RN2 (RN0+1) {4, 4, MN10300_OPERAND_RREG}, -/* rm register in the third register operand position. */ +/* rm register in the first register operand position. */ #define RM0 (RN2+1) {4, 0, MN10300_OPERAND_RREG}, -/* rm register in the third register operand position. */ +/* rm register in the second register operand position. */ #define RM1 (RM0+1) {4, 2, MN10300_OPERAND_RREG}, @@ -287,6 +287,51 @@ const struct mn10300_operand mn10300_operands[] = { #define RI (IMM8_MEM+1) {4, 4, MN10300_OPERAND_RREG}, +/* 24 bit signed displacement, may promote to 32bit dispacement. */ +#define SD24 (RI+1) + {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, + +/* 24 bit unsigned immediate which may promote to a 32bit + unsigned immediate. */ +#define IMM24 (SD24+1) + {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE}, + +/* 24 bit signed immediate which may promote to a 32bit + signed immediate. */ +#define SIMM24 (IMM24+1) + {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_SIGNED}, + +/* 16bit unsigned dispacement in a memory operation which + may promote to a 32bit displacement. */ +#define IMM24_MEM (SIMM24+1) + {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR}, +/* 32bit immediate, high 24 bits in the main instruction + word, 8 in the extension word. + + The "bits" field indicates how many bits are in the + main instruction word for MN10300_OPERAND_SPLIT! */ +#define IMM32_HIGH8 (IMM24_MEM+1) + {8, 0, MN10300_OPERAND_SPLIT}, + +/* rm register in the seventh register operand position. */ +#define RM6 (IMM32_HIGH8+1) + {4, 12, MN10300_OPERAND_RREG}, + +/* rm register in the fifth register operand position. */ +#define RN4 (RM6+1) + {4, 8, MN10300_OPERAND_RREG}, + +/* 4 bit immediate for dsp instructions. */ +#define IMM4_2 (RN4+1) + {4, 4, 0}, + +/* 4 bit immediate for dsp instructions. */ +#define SIMM4_2 (IMM4_2+1) + {4, 4, MN10300_OPERAND_SIGNED}, + +/* 4 bit immediate for dsp instructions. */ +#define SIMM4_6 (SIMM4_2+1) + {4, 12, MN10300_OPERAND_SIGNED}, /* end-sanitize-am33 */ } ; @@ -313,6 +358,56 @@ const struct mn10300_operand mn10300_operands[] = { sorted by major opcode. */ const struct mn10300_opcode mn10300_opcodes[] = { +/* start-sanitize-am33 */ +{ "mov", 0xf020, 0xfffc, FMT_D0, {USP, AN0}}, +{ "mov", 0xf024, 0xfffc, FMT_D0, {SSP, AN0}}, +{ "mov", 0xf028, 0xfffc, FMT_D0, {MSP, AN0}}, +{ "mov", 0xf02c, 0xfffc, FMT_D0, {PC, AN0}}, +{ "mov", 0xf030, 0xfff3, FMT_D0, {AN1, USP}}, +{ "mov", 0xf031, 0xfff3, FMT_D0, {AN1, SSP}}, +{ "mov", 0xf032, 0xfff3, FMT_D0, {AN1, MSP}}, +{ "mov", 0xf2ec, 0xfffc, FMT_D0, {EPSW, DN0}}, +{ "mov", 0xf2f1, 0xfff3, FMT_D0, {DM1, EPSW}}, +{ "mov", 0xf500, 0xffc0, FMT_D0, {AM2, RN0}}, +{ "mov", 0xf540, 0xffc0, FMT_D0, {DM2, RN0}}, +{ "mov", 0xf580, 0xffc0, FMT_D0, {RM1, AN0}}, +{ "mov", 0xf5c0, 0xffc0, FMT_D0, {RM1, DN0}}, +{ "mov", 0xf90800, 0xffff00, FMT_D6, {RM2, RN0}}, +{ "mov", 0xf9e800, 0xffff00, FMT_D6, {XRM2, RN0}}, +{ "mov", 0xf9f800, 0xffff00, FMT_D6, {RM2, XRN0}}, +{ "mov", 0xf90a00, 0xffff00, FMT_D6, {MEM(RM0), RN2}}, +{ "mov", 0xf91a00, 0xffff00, FMT_D6, {RM2, MEM(RN0)}}, +{ "mov", 0xf96a00, 0xffff00, FMT_D6, {MEMINC(RM0), RN2}}, +{ "mov", 0xf97a00, 0xffff00, FMT_D6, {RM2, MEMINC(RN0)}}, +{ "mov", 0xf98a00, 0xffff0f, FMT_D6, {MEM(SP), RN2}}, +{ "mov", 0xf99a00, 0xffff0f, FMT_D6, {RM2, MEM(SP)}}, +{ "mov", 0xfb0a0000, 0xffff0000, FMT_D7, {MEM2(SD8, RM0), RN2}}, +{ "mov", 0xfd0a0000, 0xffff0000, FMT_D8, {MEM2(SD24, RM0), RN2}}, +{ "mov", 0xfe0a0000, 0xffff0000, FMT_D9, {MEM2(IMM32_HIGH8,RM0), RN2}}, +{ "mov", 0xfb1a0000, 0xffff0000, FMT_D7, {RM2, MEM2(SD8, RN0)}}, +{ "mov", 0xfd1a0000, 0xffff0000, FMT_D8, {RM2, MEM2(SD24, RN0)}}, +{ "mov", 0xfe1a0000, 0xffff0000, FMT_D9, {RM2, MEM2(IMM32_HIGH8,RN0)}}, +{ "mov", 0xfb8a0000, 0xffff0f00, FMT_D7, {MEM2(SD8, SP), RN2}}, +{ "mov", 0xfd8a0000, 0xffff0f00, FMT_D8, {MEM2(SD24, SP), RN2}}, +{ "mov", 0xfe8a0000, 0xffff0f00, FMT_D9, {MEM2(IMM32_HIGH8, SP), RN2}}, +{ "mov", 0xfb9a0000, 0xffff0f00, FMT_D7, {RM2, MEM2(SD8, SP)}}, +{ "mov", 0xfd9a0000, 0xffff0f00, FMT_D8, {RM2, MEM2(SD24, SP)}}, +{ "mov", 0xfe9a0000, 0xffff0f00, FMT_D9, {RM2, MEM2(IMM32_HIGH8, SP)}}, +{ "mov", 0xfb0e0000, 0xffff0f00, FMT_D7, {MEM(IMM8_MEM), RN2}}, +{ "mov", 0xfd0e0000, 0xffff0f00, FMT_D8, {MEM(IMM24_MEM), RN2}}, +{ "mov", 0xfe0e0000, 0xffff0f00, FMT_D9, {MEM(IMM32_HIGH8), RN2}}, +{ "mov", 0xfb1e0000, 0xffff0f00, FMT_D7, {RM2, MEM(IMM8_MEM)}}, +{ "mov", 0xfd1e0000, 0xffff0f00, FMT_D8, {RM2, MEM(IMM24_MEM)}}, +{ "mov", 0xfe1e0000, 0xffff0f00, FMT_D9, {RM2, MEM(IMM32_HIGH8)}}, +{ "mov", 0xfb8e0000, 0xffff000f, FMT_D7, {MEM2(RI, RM0), RD2}}, +{ "mov", 0xfb9e0000, 0xffff000f, FMT_D7, {RD2, MEM2(RI, RN0)}}, +{ "mov", 0xfb080000, 0xffff0000, FMT_D7, {SIMM8, RN02}}, +{ "mov", 0xfd080000, 0xffff0000, FMT_D8, {SIMM24, RN02}}, +{ "mov", 0xfe080000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, +{ "mov", 0xfbf80000, 0xffff0000, FMT_D7, {SIMM8, XRN02}}, +{ "mov", 0xfdf80000, 0xffff0000, FMT_D8, {SIMM24, XRN02}}, +{ "mov", 0xfef80000, 0xffff0000, FMT_D9, {IMM32_HIGH8, XRN02}}, +/* end-sanitize-am33 */ { "mov", 0x8000, 0xf000, FMT_S1, {SIMM8, DN01}}, { "mov", 0x80, 0xf0, FMT_S0, {DM1, DN0}}, { "mov", 0xf1e0, 0xfff0, FMT_D0, {DM1, AN0}}, @@ -371,41 +466,11 @@ const struct mn10300_opcode mn10300_opcodes[] = { { "mov", 0xfccc0000, 0xfffc0000, FMT_D4, {IMM32, DN0}}, { "mov", 0x240000, 0xfc0000, FMT_S2, {IMM16, AN0}}, { "mov", 0xfcdc0000, 0xfffc0000, FMT_D4, {IMM32, AN0}}, -/* start-sanitize-am33 */ -{ "mov", 0xf020, 0xfffc, FMT_D0, {USP, AN0}}, -{ "mov", 0xf024, 0xfffc, FMT_D0, {SSP, AN0}}, -{ "mov", 0xf028, 0xfffc, FMT_D0, {MSP, AN0}}, -{ "mov", 0xf02c, 0xfffc, FMT_D0, {PC, AN0}}, -{ "mov", 0xf030, 0xfff3, FMT_D0, {AN1, USP}}, -{ "mov", 0xf031, 0xfff3, FMT_D0, {AN1, SSP}}, -{ "mov", 0xf032, 0xfff3, FMT_D0, {AN1, MSP}}, -{ "mov", 0xf2ec, 0xfffc, FMT_D0, {EPSW, DN0}}, -{ "mov", 0xf2f1, 0xfff3, FMT_D0, {DM1, EPSW}}, -{ "mov", 0xf500, 0xffc0, FMT_D0, {AM2, RN0}}, -{ "mov", 0xf540, 0xffc0, FMT_D0, {DM2, RN0}}, -{ "mov", 0xf580, 0xffc0, FMT_D0, {RM1, AN0}}, -{ "mov", 0xf5c0, 0xffc0, FMT_D0, {RM1, DN0}}, -{ "mov", 0xf90800, 0xffff00, FMT_D6, {RM2, RN0}}, -{ "mov", 0xf9e800, 0xffff00, FMT_D6, {XRM2, RN0}}, -{ "mov", 0xf9f800, 0xffff00, FMT_D6, {RM2, XRN0}}, -{ "mov", 0xf90a00, 0xffff00, FMT_D6, {MEM(RM0), RN2}}, -{ "mov", 0xf91a00, 0xffff00, FMT_D6, {RM2, MEM(RN0)}}, -{ "mov", 0xf96a00, 0xffff00, FMT_D6, {MEMINC(RM0), RN2}}, -{ "mov", 0xf97a00, 0xffff00, FMT_D6, {RM2, MEMINC(RN0)}}, -{ "mov", 0xf98a00, 0xffff0f, FMT_D6, {MEM(SP), RN2}}, -{ "mov", 0xf99a00, 0xffff0f, FMT_D6, {RM2, MEM(SP)}}, -{ "mov", 0xfb080000, 0xffff0000, FMT_D7, {SIMM8, RN02}}, -{ "mov", 0xfbf80000, 0xffff0000, FMT_D7, {SIMM8, XRN02}}, -{ "mov", 0xfb0a0000, 0xffff0000, FMT_D7, {MEM2(SD8, RM0), RN2}}, -{ "mov", 0xfb1a0000, 0xffff0000, FMT_D7, {RM2, MEM2(SD8, RN0)}}, -{ "mov", 0xfb8a0000, 0xffff0f00, FMT_D7, {MEM2(SD8, SP), RN2}}, -{ "mov", 0xfb9a0000, 0xffff0f00, FMT_D7, {RM2, MEM2(SD8, SP)}}, -{ "mov", 0xfb0e0000, 0xffff0f00, FMT_D7, {MEM(IMM8_MEM), RN2}}, -{ "mov", 0xfb1e0000, 0xffff0f00, FMT_D7, {RM2, MEM(IMM8_MEM)}}, -{ "mov", 0xfb8e0000, 0xffff000f, FMT_D7, {MEM2(RI, RM0), RD2}}, -{ "mov", 0xfb9e0000, 0xffff000f, FMT_D7, {RD2, MEM2(RI, RN0))}}, +/* start-sanitize-am33 */ { "movu", 0xfb180000, 0xffff0000, FMT_D7, {IMM8, RN02}}, +{ "movu", 0xfd180000, 0xffff0000, FMT_D8, {IMM24, RN02}}, +{ "movu", 0xfe180000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, { "mcst9", 0xf630, 0xfff0, FMT_D0, {DN01}}, { "mcst48", 0xf660, 0xfff0, FMT_D0, {DN01}}, @@ -418,29 +483,45 @@ const struct mn10300_opcode mn10300_opcodes[] = { { "mac", 0xfb0f0000, 0xffff0000, FMT_D7, {RM2, RN0, RD2, RD0}}, { "mac", 0xf90b00, 0xffff00, FMT_D6, {RM2, RN0}}, { "mac", 0xfb0b0000, 0xffff0000, FMT_D7, {SIMM8, RN02}}, +{ "mac", 0xfd0b0000, 0xffff0000, FMT_D8, {SIMM24, RN02}}, +{ "mac", 0xfe0b0000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, { "macu", 0xfb1f0000, 0xffff0000, FMT_D7, {RM2, RN0, RD2, RD0}}, { "macu", 0xf91b00, 0xffff00, FMT_D6, {RM2, RN0}}, { "macu", 0xfb1b0000, 0xffff0000, FMT_D7, {IMM8, RN02}}, +{ "macu", 0xfd1b0000, 0xffff0000, FMT_D8, {IMM24, RN02}}, +{ "macu", 0xfe1b0000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, { "macb", 0xfb2f0000, 0xffff0000, FMT_D7, {RM2, RN0, RD2, RD0}}, { "macb", 0xf92b00, 0xffff00, FMT_D6, {RM2, RN0}}, { "macb", 0xfb2b0000, 0xffff0000, FMT_D7, {SIMM8, RN02}}, +{ "macb", 0xfd2b0000, 0xffff0000, FMT_D8, {SIMM24, RN02}}, +{ "macb", 0xfe2b0000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, { "macbu", 0xfb3f0000, 0xffff0000, FMT_D7, {RM2, RN0, RD2, RD0}}, { "macbu", 0xf93b00, 0xffff00, FMT_D6, {RM2, RN0}}, { "macbu", 0xfb3b0000, 0xffff0000, FMT_D7, {IMM8, RN02}}, +{ "macbu", 0xfd3b0000, 0xffff0000, FMT_D8, {IMM24, RN02}}, +{ "macbu", 0xfe3b0000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, { "mach", 0xfb4f0000, 0xffff0000, FMT_D7, {RM2, RN0, RD2, RD0}}, { "mach", 0xf94b00, 0xffff00, FMT_D6, {RM2, RN0}}, { "mach", 0xfb4b0000, 0xffff0000, FMT_D7, {SIMM8, RN02}}, +{ "mach", 0xfd4b0000, 0xffff0000, FMT_D8, {SIMM24, RN02}}, +{ "mach", 0xfe4b0000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, { "machu", 0xfb5f0000, 0xffff0000, FMT_D7, {RM2, RN0, RD2, RD0}}, { "machu", 0xf95b00, 0xffff00, FMT_D6, {RM2, RN0}}, { "machu", 0xfb5b0000, 0xffff0000, FMT_D7, {IMM8, RN02}}, +{ "machu", 0xfd5b0000, 0xffff0000, FMT_D8, {IMM24, RN02}}, +{ "machu", 0xfe5b0000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, { "dmach", 0xfb6f0000, 0xffff000f, FMT_D7, {RM2, RN0, RD2}}, { "dmach", 0xf96b00, 0xffff00, FMT_D6, {RM2, RN0}}, +{ "dmach", 0xfe6b0000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, { "dmachu", 0xfb7f0000, 0xffff000f, FMT_D7, {RM2, RN0, RD2}}, { "dmachu", 0xf97b00, 0xffff00, FMT_D6, {RM2, RN0}}, +{ "dmachu", 0xfe7b0000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, { "dmulh", 0xfb8f0000, 0xffff0000, FMT_D7, {RM2, RN0, RD2, RD0}}, { "dmulh", 0xf98b00, 0xffff00, FMT_D6, {RM2, RN0}}, +{ "dmulh", 0xfe8b0000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, { "dmulhu", 0xfb9f0000, 0xffff0000, FMT_D7, {RM2, RN0, RD2, RD0}}, { "dmulhu", 0xf99b00, 0xffff00, FMT_D6, {RM2, RN0}}, +{ "dmulhu", 0xfe9b0000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, { "mcste", 0xf9bb00, 0xffff00, FMT_D6, {RM2, RN0}}, { "mcste", 0xfbbb0000, 0xffff0000, FMT_D7, {IMM8, RN02}}, { "swhw", 0xf9eb00, 0xffff00, FMT_D6, {RM2, RN0}}, @@ -472,13 +553,25 @@ const struct mn10300_opcode mn10300_opcodes[] = { { "movbu", 0xf9aa00, 0xffff0f, FMT_D6, {MEM(SP), RN2}}, { "movbu", 0xf9ba00, 0xffff0f, FMT_D6, {RM2, MEM(SP)}}, { "movbu", 0xfb2a0000, 0xffff0000, FMT_D7, {MEM2(SD8, RM0), RN2}}, +{ "movbu", 0xfd2a0000, 0xffff0000, FMT_D8, {MEM2(SD24, RM0), RN2}}, +{ "movbu", 0xfe2a0000, 0xffff0000, FMT_D9, {MEM2(IMM32_HIGH8,RM0), RN2}}, { "movbu", 0xfb3a0000, 0xffff0000, FMT_D7, {RM2, MEM2(SD8, RN0)}}, +{ "movbu", 0xfd3a0000, 0xffff0000, FMT_D8, {RM2, MEM2(SD24, RN0)}}, +{ "movbu", 0xfe3a0000, 0xffff0000, FMT_D9, {RM2, MEM2(IMM32_HIGH8,RN0)}}, { "movbu", 0xfbaa0000, 0xffff0f00, FMT_D7, {MEM2(SD8, SP), RN2}}, +{ "movbu", 0xfdaa0000, 0xffff0f00, FMT_D8, {MEM2(SD24, SP), RN2}}, +{ "movbu", 0xfeaa0000, 0xffff0f00, FMT_D9, {MEM2(IMM32_HIGH8,SP), RN2}}, { "movbu", 0xfbba0000, 0xffff0f00, FMT_D7, {RM2, MEM2(SD8, SP)}}, +{ "movbu", 0xfdba0000, 0xffff0f00, FMT_D8, {RM2, MEM2(SD24, SP)}}, +{ "movbu", 0xfeba0000, 0xffff0f00, FMT_D9, {RM2, MEM2(IMM32_HIGH8, SP)}}, { "movbu", 0xfb2e0000, 0xffff0f00, FMT_D7, {MEM(IMM8_MEM), RN2}}, +{ "movbu", 0xfd2e0000, 0xffff0f00, FMT_D8, {MEM(IMM24_MEM), RN2}}, +{ "movbu", 0xfe2e0000, 0xffff0f00, FMT_D9, {MEM(IMM32_HIGH8), RN2}}, { "movbu", 0xfb3e0000, 0xffff0f00, FMT_D7, {RM2, MEM(IMM8_MEM)}}, +{ "movbu", 0xfd3e0000, 0xffff0f00, FMT_D8, {RM2, MEM(IMM24_MEM)}}, +{ "movbu", 0xfe3e0000, 0xffff0f00, FMT_D9, {RM2, MEM(IMM32_HIGH8)}}, { "movbu", 0xfbae0000, 0xffff000f, FMT_D7, {MEM2(RI, RM0), RD2}}, -{ "movbu", 0xfbbe0000, 0xffff000f, FMT_D7, {RD2, MEM2(RI, RN0))}}, +{ "movbu", 0xfbbe0000, 0xffff000f, FMT_D7, {RD2, MEM2(RI, RN0)}}, /* end-sanitize-am33 */ { "movhu", 0xf060, 0xfff0, FMT_D0, {MEM(AM0), DN1}}, @@ -509,13 +602,25 @@ const struct mn10300_opcode mn10300_opcodes[] = { { "movhu", 0xf9ea00, 0xffff00, FMT_D6, {MEMINC(RM0), RN2}}, { "movhu", 0xf9fa00, 0xffff00, FMT_D6, {RM2, MEMINC(RN0)}}, { "movhu", 0xfb4a0000, 0xffff0000, FMT_D7, {MEM2(SD8, RM0), RN2}}, +{ "movhu", 0xfd4a0000, 0xffff0000, FMT_D8, {MEM2(SD24, RM0), RN2}}, +{ "movhu", 0xfe4a0000, 0xffff0000, FMT_D9, {MEM2(IMM32_HIGH8,RM0), RN2}}, { "movhu", 0xfb5a0000, 0xffff0000, FMT_D7, {RM2, MEM2(SD8, RN0)}}, +{ "movhu", 0xfd5a0000, 0xffff0000, FMT_D8, {RM2, MEM2(SD24, RN0)}}, +{ "movhu", 0xfe5a0000, 0xffff0000, FMT_D9, {RM2, MEM2(IMM32_HIGH8,RN0)}}, { "movhu", 0xfbca0000, 0xffff0f00, FMT_D7, {MEM2(SD8, SP), RN2}}, +{ "movhu", 0xfdca0000, 0xffff0f00, FMT_D8, {MEM2(SD24, SP), RN2}}, +{ "movhu", 0xfeca0000, 0xffff0f00, FMT_D9, {MEM2(IMM32_HIGH8, SP), RN2}}, { "movhu", 0xfbda0000, 0xffff0f00, FMT_D7, {RM2, MEM2(SD8, SP)}}, +{ "movhu", 0xfdda0000, 0xffff0f00, FMT_D8, {RM2, MEM2(SD24, SP)}}, +{ "movhu", 0xfeda0000, 0xffff0f00, FMT_D9, {RM2, MEM2(IMM32_HIGH8, SP)}}, { "movhu", 0xfb4e0000, 0xffff0f00, FMT_D7, {MEM(IMM8_MEM), RN2}}, +{ "movhu", 0xfd4e0000, 0xffff0f00, FMT_D8, {MEM(IMM24_MEM), RN2}}, +{ "movhu", 0xfe4e0000, 0xffff0f00, FMT_D9, {MEM(IMM32_HIGH8), RN2}}, { "movhu", 0xfb5e0000, 0xffff0f00, FMT_D7, {RM2, MEM(IMM8_MEM)}}, -{ "movbu", 0xfbce0000, 0xffff000f, FMT_D7, {MEM2(RI, RM0), RD2}}, -{ "movbu", 0xfbde0000, 0xffff000f, FMT_D7, {RD2, MEM2(RI, RN0))}}, +{ "movhu", 0xfd5e0000, 0xffff0f00, FMT_D8, {RM2, MEM(IMM24_MEM)}}, +{ "movhu", 0xfe5e0000, 0xffff0f00, FMT_D9, {RM2, MEM(IMM32_HIGH8)}}, +{ "movhu", 0xfbce0000, 0xffff000f, FMT_D7, {MEM2(RI, RM0), RD2}}, +{ "movhu", 0xfbde0000, 0xffff000f, FMT_D7, {RD2, MEM2(RI, RN0)}}, /* end-sanitize-am33 */ { "ext", 0xf2d0, 0xfffc, FMT_D0, {DN0}}, @@ -570,12 +675,16 @@ const struct mn10300_opcode mn10300_opcodes[] = { /* start-sanitize-am33 */ { "add", 0xf97800, 0xffff00, FMT_D6, {RM2, RN0}}, { "add", 0xfb780000, 0xffff0000, FMT_D7, {SIMM8, RN02}}, +{ "add", 0xfd780000, 0xffff0000, FMT_D8, {SIMM24, RN02}}, +{ "add", 0xfe780000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, { "addc", 0xfb8c0000, 0xffff000f, FMT_D7, {RM2, RN0, RD0}}, /* end-sanitize-am33 */ { "addc", 0xf140, 0xfff0, FMT_D0, {DM1, DN0}}, /* start-sanitize-am33 */ { "addc", 0xf98800, 0xffff00, FMT_D6, {RM2, RN0}}, { "addc", 0xfb880000, 0xffff0000, FMT_D7, {SIMM8, RN02}}, +{ "addc", 0xfd880000, 0xffff0000, FMT_D8, {SIMM24, RN02}}, +{ "addc", 0xfe880000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, /* end-sanitize-am33 */ /* start-sanitize-am33 */ @@ -590,18 +699,24 @@ const struct mn10300_opcode mn10300_opcodes[] = { /* start-sanitize-am33 */ { "sub", 0xf99800, 0xffff00, FMT_D6, {RM2, RN0}}, { "sub", 0xfb980000, 0xffff0000, FMT_D7, {SIMM8, RN02}}, +{ "sub", 0xfd980000, 0xffff0000, FMT_D8, {SIMM24, RN02}}, +{ "sub", 0xfe980000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, { "subc", 0xfa8c0000, 0xffff000f, FMT_D7, {RM2, RN0, RD0}}, /* end-sanitize-am33 */ { "subc", 0xf180, 0xfff0, FMT_D0, {DM1, DN0}}, /* start-sanitize-am33 */ { "subc", 0xf9a800, 0xffff00, FMT_D6, {RM2, RN0}}, { "subc", 0xfba80000, 0xffff0000, FMT_D7, {SIMM8, RN02}}, +{ "subc", 0xfda80000, 0xffff0000, FMT_D8, {SIMM24, RN02}}, +{ "subc", 0xfea80000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, /* end-sanitize-am33 */ /* start-sanitize-am33 */ { "mul", 0xfbab0000, 0xffff0000, FMT_D7, {RM2, RN0, RD2, RD0}}, { "mul", 0xf9a900, 0xffff00, FMT_D6, {RM2, RN0}}, { "mul", 0xfba90000, 0xffff0000, FMT_D7, {SIMM8, RN02}}, +{ "mul", 0xfda90000, 0xffff0000, FMT_D8, {SIMM24, RN02}}, +{ "mul", 0xfea90000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, /* end-sanitize-am33 */ { "mul", 0xf240, 0xfff0, FMT_D0, {DM1, DN0}}, @@ -609,6 +724,8 @@ const struct mn10300_opcode mn10300_opcodes[] = { { "mulu", 0xfbbb0000, 0xffff0000, FMT_D7, {RM2, RN0, RD2, RD0}}, { "mulu", 0xf9b900, 0xffff00, FMT_D6, {RM2, RN0}}, { "mulu", 0xfbb90000, 0xffff0000, FMT_D7, {IMM8, RN02}}, +{ "mulu", 0xfdb90000, 0xffff0000, FMT_D8, {IMM24, RN02}}, +{ "mulu", 0xfeb90000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, /* end-sanitize-am33 */ { "mulu", 0xf250, 0xfff0, FMT_D0, {DM1, DN0}}, @@ -644,6 +761,8 @@ const struct mn10300_opcode mn10300_opcodes[] = { /* start-sanitize-am33 */ { "cmp", 0xf9d800, 0xffff00, FMT_D6, {RM2, RN0}}, { "cmp", 0xfbd80000, 0xffff0000, FMT_D7, {SIMM8, RN02}}, +{ "cmp", 0xfdd80000, 0xffff0000, FMT_D8, {SIMM24, RN02}}, +{ "cmp", 0xfed80000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, /* end-sanitize-am33 */ /* start-sanitize-am33 */ @@ -658,6 +777,8 @@ const struct mn10300_opcode mn10300_opcodes[] = { { "and", 0xfcfc0000, 0xffff0000, FMT_D4, {IMM32, EPSW}}, { "and", 0xf90900, 0xffff00, FMT_D6, {RM2, RN0}}, { "and", 0xfb090000, 0xffff0000, FMT_D7, {IMM8, RN02}}, +{ "and", 0xfd090000, 0xffff0000, FMT_D8, {IMM24, RN02}}, +{ "and", 0xfe090000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, /* end-sanitize-am33 */ /* start-sanitize-am33 */ @@ -672,6 +793,8 @@ const struct mn10300_opcode mn10300_opcodes[] = { { "or", 0xfcfd0000, 0xffff0000, FMT_D4, {IMM32, EPSW}}, { "or", 0xf91900, 0xffff00, FMT_D6, {RM2, RN0}}, { "or", 0xfb190000, 0xffff0000, FMT_D7, {IMM8, RN02}}, +{ "or", 0xfd190000, 0xffff0000, FMT_D8, {IMM24, RN02}}, +{ "or", 0xfe190000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, /* end-sanitize-am33 */ /* start-sanitize-am33 */ @@ -683,12 +806,21 @@ const struct mn10300_opcode mn10300_opcodes[] = { /* start-sanitize-am33 */ { "xor", 0xf92900, 0xffff00, FMT_D6, {RM2, RN0}}, { "xor", 0xfb290000, 0xffff0000, FMT_D7, {IMM8, RN02}}, +{ "xor", 0xfd290000, 0xffff0000, FMT_D8, {IMM24, RN02}}, +{ "xor", 0xfe290000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, /* end-sanitize-am33 */ { "not", 0xf230, 0xfffc, FMT_D0, {DN0}}, /* start-sanitize-am33 */ { "not", 0xf93900, 0xffff00, FMT_D6, {RN02}}, /* end-sanitize-am33 */ +/* start-sanitize-am33 */ +/* Place these before the one with IMM8E since we want the IMM8E to match + last since it does not promote. */ +{ "btst", 0xfbe90000, 0xffff0000, FMT_D7, {IMM8, RN02}}, +{ "btst", 0xfde90000, 0xffff0000, FMT_D8, {IMM24, RN02}}, +{ "btst", 0xfee90000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, +/* end-sanitize-am33 */ { "btst", 0xf8ec00, 0xfffc00, FMT_D1, {IMM8, DN0}}, { "btst", 0xfaec0000, 0xfffc0000, FMT_D2, {IMM16, DN0}}, { "btst", 0xfcec0000, 0xfffc0000, FMT_D4, {IMM32, DN0}}, @@ -696,9 +828,6 @@ const struct mn10300_opcode mn10300_opcodes[] = { MEM(IMM32_LOWSHIFT8)}}, { "btst", 0xfaf80000, 0xfffc0000, FMT_D2, {IMM8, MEM2(SD8N_SHIFT8,AN0)}}, -/* start-sanitize-am33 */ -{ "btst", 0xfbe90000, 0xffff0000, FMT_D7, {IMM8, RN02}}, -/* end-sanitize-am33 */ { "bset", 0xf080, 0xfff0, FMT_D0, {DM1, MEM(AN0)}}, { "bset", 0xfe000000, 0xffff0000, FMT_D5, {IMM8E, MEM(IMM32_LOWSHIFT8)}}, @@ -717,7 +846,9 @@ const struct mn10300_opcode mn10300_opcodes[] = { { "asr", 0xf8c800, 0xfffc00, FMT_D1, {IMM8, DN0}}, /* start-sanitize-am33 */ { "asr", 0xf94900, 0xffff00, FMT_D6, {RM2, RN0}}, -{ "asr", 0xfb490000, 0xffff0000, FMT_D7, {SIMM8, RN02}}, +{ "asr", 0xfb490000, 0xffff0000, FMT_D7, {IMM8, RN02}}, +{ "asr", 0xfd490000, 0xfffc0000, FMT_D8, {IMM24, RN02}}, +{ "asr", 0xfe490000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, /* end-sanitize-am33 */ /* start-sanitize-am33 */ @@ -727,7 +858,9 @@ const struct mn10300_opcode mn10300_opcodes[] = { { "lsr", 0xf8c400, 0xfffc00, FMT_D1, {IMM8, DN0}}, /* start-sanitize-am33 */ { "lsr", 0xf95900, 0xffff00, FMT_D6, {RM2, RN0}}, -{ "lsr", 0xfb590000, 0xffff0000, FMT_D7, {SIMM8, RN02}}, +{ "lsr", 0xfb590000, 0xffff0000, FMT_D7, {IMM8, RN02}}, +{ "lsr", 0xfd590000, 0xfffc0000, FMT_D8, {IMM24, RN02}}, +{ "lsr", 0xfe590000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, /* end-sanitize-am33 */ /* start-sanitize-am33 */ @@ -738,6 +871,8 @@ const struct mn10300_opcode mn10300_opcodes[] = { /* start-sanitize-am33 */ { "asl", 0xf96900, 0xffff00, FMT_D6, {RM2, RN0}}, { "asl", 0xfb690000, 0xffff0000, FMT_D7, {SIMM8, RN02}}, +{ "asl", 0xfd690000, 0xfffc0000, FMT_D8, {IMM24, RN02}}, +{ "asl", 0xfe690000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, /* end-sanitize-am33 */ { "asl2", 0x54, 0xfc, FMT_S0, {DN0}}, /* start-sanitize-am33 */ @@ -841,6 +976,366 @@ const struct mn10300_opcode mn10300_opcodes[] = { mn10x00 the "break" instruction must be one byte. 0xff is available on both mn10x00 architectures. */ { "break", 0xff, 0xff, FMT_S0, {UNUSED}}, + +/* start-sanitize-am33 */ +{ "add_add", 0xf7000000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, +{ "add_add", 0xf7100000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "add_add", 0xf7040000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + RM2, RN0}}, +{ "add_add", 0xf7140000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + SIMM4_2, RN0}}, +{ "add_sub", 0xf7200000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, +{ "add_sub", 0xf7300000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "add_sub", 0xf7240000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + RM2, RN0}}, +{ "add_sub", 0xf7340000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + SIMM4_2, RN0}}, +{ "add_cmp", 0xf7400000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, +{ "add_cmp", 0xf7500000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "add_cmp", 0xf7440000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + RM2, RN0}}, +{ "add_cmp", 0xf7540000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + SIMM4_2, RN0}}, +{ "add_mov", 0xf7600000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, +{ "add_mov", 0xf7700000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "add_mov", 0xf7640000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + RM2, RN0}}, +{ "add_mov", 0xf7740000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + SIMM4_2, RN0}}, +{ "add_asr", 0xf7800000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, +{ "add_asr", 0xf7900000, 0xffff0000, FMT_D10, {RM6, RN4, + IMM4_2, RN0}}, +{ "add_asr", 0xf7840000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + RM2, RN0}}, +{ "add_asr", 0xf7940000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + IMM4_2, RN0}}, +{ "add_lsr", 0xf7a00000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, +{ "add_lsr", 0xf7b00000, 0xffff0000, FMT_D10, {RM6, RN4, + IMM4_2, RN0}}, +{ "add_lsr", 0xf7a40000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + RM2, RN0}}, +{ "add_lsr", 0xf7b40000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + IMM4_2, RN0}}, +{ "add_asl", 0xf7c00000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, +{ "add_asl", 0xf7d00000, 0xffff0000, FMT_D10, {RM6, RN4, + IMM4_2, RN0}}, +{ "add_asl", 0xf7c40000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + RM2, RN0}}, +{ "add_asl", 0xf7d40000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + IMM4_2, RN0}}, +{ "cmp_add", 0xf7010000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, +{ "cmp_add", 0xf7110000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "cmp_add", 0xf7050000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + RM2, RN0}}, +{ "cmp_add", 0xf7150000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + SIMM4_2, RN0}}, +{ "cmp_sub", 0xf7210000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, +{ "cmp_sub", 0xf7310000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "cmp_sub", 0xf7250000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + RM2, RN0}}, +{ "cmp_sub", 0xf7350000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + SIMM4_2, RN0}}, +{ "cmp_mov", 0xf7610000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, +{ "cmp_mov", 0xf7710000, 0xffff0000, FMT_D10, {RM6, RN4, + IMM4_2, RN0}}, +{ "cmp_mov", 0xf7650000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + RM2, RN0}}, +{ "cmp_mov", 0xf7750000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + SIMM4_2, RN0}}, +{ "cmp_asr", 0xf7810000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, +{ "cmp_asr", 0xf7910000, 0xffff0000, FMT_D10, {RM6, RN4, + IMM4_2, RN0}}, +{ "cmp_asr", 0xf7850000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + RM2, RN0}}, +{ "cmp_asr", 0xf7950000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + IMM4_2, RN0}}, +{ "cmp_lsr", 0xf7a10000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, +{ "cmp_lsr", 0xf7b10000, 0xffff0000, FMT_D10, {RM6, RN4, + IMM4_2, RN0}}, +{ "cmp_lsr", 0xf7a50000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + RM2, RN0}}, +{ "cmp_lsr", 0xf7b50000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + IMM4_2, RN0}}, +{ "cmp_asl", 0xf7c10000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, +{ "cmp_asl", 0xf7d10000, 0xffff0000, FMT_D10, {RM6, RN4, IMM4_2, RN0}}, +{ "cmp_asl", 0xf7c50000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + RM2, RN0}}, +{ "cmp_asl", 0xf7d50000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + IMM4_2, RN0}}, +{ "sub_add", 0xf7020000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, +{ "sub_add", 0xf7120000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "sub_add", 0xf7060000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + RM2, RN0}}, +{ "sub_add", 0xf7160000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + SIMM4_2, RN0}}, +{ "sub_sub", 0xf7220000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, +{ "sub_sub", 0xf7320000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "sub_sub", 0xf7260000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + RM2, RN0}}, +{ "sub_sub", 0xf7360000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + SIMM4_2, RN0}}, +{ "sub_cmp", 0xf7420000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, +{ "sub_cmp", 0xf7520000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "sub_cmp", 0xf7460000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + RM2, RN0}}, +{ "sub_cmp", 0xf7560000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + SIMM4_2, RN0}}, +{ "sub_mov", 0xf7620000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, +{ "sub_mov", 0xf7720000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "sub_mov", 0xf7660000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + RM2, RN0}}, +{ "sub_mov", 0xf7760000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + SIMM4_2, RN0}}, +{ "sub_asr", 0xf7820000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, +{ "sub_asr", 0xf7920000, 0xffff0000, FMT_D10, {RM6, RN4, + IMM4_2, RN0}}, +{ "sub_asr", 0xf7860000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + RM2, RN0}}, +{ "sub_asr", 0xf7960000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + IMM4_2, RN0}}, +{ "sub_lsr", 0xf7a20000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, +{ "sub_lsr", 0xf7b20000, 0xffff0000, FMT_D10, {RM6, RN4, + IMM4_2, RN0}}, +{ "sub_lsr", 0xf7a60000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + RM2, RN0}}, +{ "sub_lsr", 0xf7b60000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + IMM4_2, RN0}}, +{ "sub_asl", 0xf7c20000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, +{ "sub_asl", 0xf7d20000, 0xffff0000, FMT_D10, {RM6, RN4, + IMM4_2, RN0}}, +{ "sub_asl", 0xf7c60000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + RM2, RN0}}, +{ "sub_asl", 0xf7d60000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + SIMM4_2, RN0}}, +{ "mov_add", 0xf7030000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, +{ "mov_add", 0xf7130000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "mov_add", 0xf7070000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + RM2, RN0}}, +{ "mov_add", 0xf7170000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + SIMM4_2, RN0}}, +{ "mov_sub", 0xf7230000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, +{ "mov_sub", 0xf7330000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "mov_sub", 0xf7270000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + RM2, RN0}}, +{ "mov_sub", 0xf7370000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + SIMM4_2, RN0}}, +{ "mov_cmp", 0xf7430000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, +{ "mov_cmp", 0xf7530000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "mov_cmp", 0xf7470000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + RM2, RN0}}, +{ "mov_cmp", 0xf7570000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + SIMM4_2, RN0}}, +{ "mov_mov", 0xf7630000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, +{ "mov_mov", 0xf7730000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "mov_mov", 0xf7670000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + RM2, RN0}}, +{ "mov_mov", 0xf7770000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + SIMM4_2, RN0}}, +{ "mov_asr", 0xf7830000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, +{ "mov_asr", 0xf7930000, 0xffff0000, FMT_D10, {RM6, RN4, + IMM4_2, RN0}}, +{ "mov_asr", 0xf7870000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + RM2, RN0}}, +{ "mov_asr", 0xf7970000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + IMM4_2, RN0}}, +{ "mov_lsr", 0xf7a30000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, +{ "mov_lsr", 0xf7b30000, 0xffff0000, FMT_D10, {RM6, RN4, + IMM4_2, RN0}}, +{ "mov_lsr", 0xf7a70000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + RM2, RN0}}, +{ "mov_lsr", 0xf7b70000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + IMM4_2, RN0}}, +{ "mov_asl", 0xf7c30000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, +{ "mov_asl", 0xf7d30000, 0xffff0000, FMT_D10, {RM6, RN4, + IMM4_2, RN0}}, +{ "mov_asl", 0xf7c70000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + RM2, RN0}}, +{ "mov_asl", 0xf7d70000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, + IMM4_2, RN0}}, +{ "and_add", 0xf7080000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "and_add", 0xf7180000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "and_sub", 0xf7280000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "and_sub", 0xf7380000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "and_cmp", 0xf7480000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "and_cmp", 0xf7580000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "and_mov", 0xf7680000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "and_mov", 0xf7780000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "and_asr", 0xf7880000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "and_asr", 0xf7980000, 0xffff0000, FMT_D10, {RM6, RN4, + IMM4_2, RN0}}, +{ "and_lsr", 0xf7a80000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "and_lsr", 0xf7b80000, 0xffff0000, FMT_D10, {RM6, RN4, + IMM4_2, RN0}}, +{ "and_asl", 0xf7c80000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "and_asl", 0xf7d80000, 0xffff0000, FMT_D10, {RM6, RN4, + IMM4_2, RN0}}, +{ "dmach_add", 0xf7090000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "dmach_add", 0xf7190000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "dmach_sub", 0xf7290000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "dmach_sub", 0xf7390000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "dmach_cmp", 0xf7490000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "dmach_cmp", 0xf7590000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "dmach_mov", 0xf7690000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "dmach_mov", 0xf7790000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "dmach_asr", 0xf7890000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "dmach_asr", 0xf7990000, 0xffff0000, FMT_D10, {RM6, RN4, + IMM4_2, RN0}}, +{ "dmach_lsr", 0xf7a90000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "dmach_lsr", 0xf7b90000, 0xffff0000, FMT_D10, {RM6, RN4, + IMM4_2, RN0}}, +{ "dmach_asl", 0xf7c90000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "dmach_asl", 0xf7d90000, 0xffff0000, FMT_D10, {RM6, RN4, + IMM4_2, RN0}}, +{ "xor_add", 0xf70a0000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "xor_add", 0xf71a0000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "xor_sub", 0xf72a0000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "xor_sub", 0xf73a0000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "xor_cmp", 0xf74a0000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "xor_cmp", 0xf75a0000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "xor_mov", 0xf76a0000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "xor_mov", 0xf77a0000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "xor_asr", 0xf78a0000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "xor_asr", 0xf79a0000, 0xffff0000, FMT_D10, {RM6, RN4, + IMM4_2, RN0}}, +{ "xor_lsr", 0xf7aa0000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "xor_lsr", 0xf7ba0000, 0xffff0000, FMT_D10, {RM6, RN4, + IMM4_2, RN0}}, +{ "xor_asl", 0xf7ca0000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "xor_asl", 0xf7da0000, 0xffff0000, FMT_D10, {RM6, RN4, + IMM4_2, RN0}}, +{ "swhw_add", 0xf70b0000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "swhw_add", 0xf71b0000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "swhw_sub", 0xf72b0000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "swhw_sub", 0xf73b0000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "swhw_cmp", 0xf74b0000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "swhw_cmp", 0xf75b0000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "swhw_mov", 0xf76b0000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "swhw_mov", 0xf77b0000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "swhw_asr", 0xf78b0000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "swhw_asr", 0xf79b0000, 0xffff0000, FMT_D10, {RM6, RN4, + IMM4_2, RN0}}, +{ "swhw_lsr", 0xf7ab0000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "swhw_lsr", 0xf7bb0000, 0xffff0000, FMT_D10, {RM6, RN4, + IMM4_2, RN0}}, +{ "swhw_asl", 0xf7cb0000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "swhw_asl", 0xf7db0000, 0xffff0000, FMT_D10, {RM6, RN4, + IMM4_2, RN0}}, +{ "or_add", 0xf70c0000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "or_add", 0xf71c0000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "or_sub", 0xf72c0000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "or_sub", 0xf73c0000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "or_cmp", 0xf74c0000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "or_cmp", 0xf75c0000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "or_mov", 0xf76c0000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "or_mov", 0xf77c0000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "or_asr", 0xf78c0000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "or_asr", 0xf79c0000, 0xffff0000, FMT_D10, {RM6, RN4, + IMM4_2, RN0}}, +{ "or_lsr", 0xf7ac0000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "or_lsr", 0xf7bc0000, 0xffff0000, FMT_D10, {RM6, RN4, + IMM4_2, RN0}}, +{ "or_asl", 0xf7cc0000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "or_asl", 0xf7dc0000, 0xffff0000, FMT_D10, {RM6, RN4, + IMM4_2, RN0}}, +{ "sat16_add", 0xf70d0000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "sat16_add", 0xf71d0000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "sat16_sub", 0xf72d0000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "sat16_sub", 0xf73d0000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "sat16_cmp", 0xf74d0000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "sat16_cmp", 0xf75d0000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "sat16_mov", 0xf76d0000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "sat16_mov", 0xf77d0000, 0xffff0000, FMT_D10, {RM6, RN4, + SIMM4_2, RN0}}, +{ "sat16_asr", 0xf78d0000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "sat16_asr", 0xf79d0000, 0xffff0000, FMT_D10, {RM6, RN4, + IMM4_2, RN0}}, +{ "sat16_lsr", 0xf7ad0000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "sat16_lsr", 0xf7bd0000, 0xffff0000, FMT_D10, {RM6, RN4, + IMM4_2, RN0}}, +{ "sat16_asl", 0xf7cd0000, 0xffff0000, FMT_D10, {RM6, RN4, + RM2, RN0}}, +{ "sat16_asl", 0xf7dd0000, 0xffff0000, FMT_D10, {RM6, RN4, + IMM4_2, RN0}}, +/* end-sanitize-am33 */ + { 0, 0, 0, 0, {0}}, } ; |