diff options
| -rw-r--r-- | bfd/elfxx-riscv.c | 6 | ||||
| -rw-r--r-- | gas/NEWS | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/march-help.l | 1 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/zvfbfmin.d | 12 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/zvfbfmin.s | 7 | ||||
| -rw-r--r-- | include/opcode/riscv-opc.h | 8 | ||||
| -rw-r--r-- | include/opcode/riscv.h | 1 | ||||
| -rw-r--r-- | opcodes/riscv-opc.c | 4 |
8 files changed, 41 insertions, 0 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 1d70139..0131ce8 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1192,6 +1192,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"v", "zve64d", check_implicit_always}, {"v", "zvl128b", check_implicit_always}, {"zabha", "a", check_implicit_always}, + {"zvfbfmin", "zve32f", check_implicit_always}, {"zvfh", "zvfhmin", check_implicit_always}, {"zvfh", "zfhmin", check_implicit_always}, {"zvfhmin", "zve32f", check_implicit_always}, @@ -1393,6 +1394,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2647,6 +2649,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "zvbb"); case INSN_CLASS_ZVBC: return riscv_subset_supports (rps, "zvbc"); + case INSN_CLASS_ZVFBFMIN: + return riscv_subset_supports (rps, "zvfbfmin"); case INSN_CLASS_ZVKB: return riscv_subset_supports (rps, "zvkb"); case INSN_CLASS_ZVKG: @@ -2917,6 +2921,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("zvbb"); case INSN_CLASS_ZVBC: return _("zvbc"); + case INSN_CLASS_ZVFBFMIN: + return "zvfbfmin"; case INSN_CLASS_ZVKB: return _("zvkb"); case INSN_CLASS_ZVKG: @@ -23,6 +23,8 @@ * Add support for RISC-V Zfbfmin extension with version 1.0. +* Add support for RISC-V Zvfbfmin extension with version 1.0. + * The base register operand in D(X,B) and D(L,B) may be explicitly omitted in assembly on s390. It can now be coded as D(X,) or D(L,) instead of D(X,0) D(X,%r0), D(L,0), and D(L,%r0). diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l index 57c73b3..38c70e2 100644 --- a/gas/testsuite/gas/riscv/march-help.l +++ b/gas/testsuite/gas/riscv/march-help.l @@ -58,6 +58,7 @@ All available -march extensions for RISC-V: zve64d 1.0 zvbb 1.0 zvbc 1.0 + zvfbfmin 1.0 zvfh 1.0 zvfhmin 1.0 zvkb 1.0 diff --git a/gas/testsuite/gas/riscv/zvfbfmin.d b/gas/testsuite/gas/riscv/zvfbfmin.d new file mode 100644 index 0000000..ce97381 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvfbfmin.d @@ -0,0 +1,12 @@ +#as: -march=rv64iv_zvfbfmin +#objdump: -d + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+4a8e9257[ ]+vfncvtbf16.f.f.w[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+488e9257[ ]+vfncvtbf16.f.f.w[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+4a869257[ ]+vfwcvtbf16.f.f.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+48869257[ ]+vfwcvtbf16.f.f.v[ ]+v4,v8,v0.t diff --git a/gas/testsuite/gas/riscv/zvfbfmin.s b/gas/testsuite/gas/riscv/zvfbfmin.s new file mode 100644 index 0000000..9a4493d --- /dev/null +++ b/gas/testsuite/gas/riscv/zvfbfmin.s @@ -0,0 +1,7 @@ +target: + # vfncvtbf16.f.f.w + vfncvtbf16.f.f.w v4, v8 + vfncvtbf16.f.f.w v4, v8, v0.t + # vfwcvtbf16.f.f.v + vfwcvtbf16.f.f.v v4, v8 + vfwcvtbf16.f.f.v v4, v8, v0.t diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index ef33aeb..c5270d0 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2370,6 +2370,11 @@ #define MASK_FCVT_BF16_S 0xfff0007f #define MATCH_FCVT_S_BF16 0x40600053 #define MASK_FCVT_S_BF16 0xfff0007f +/* Zvfbfmin intructions. */ +#define MATCH_VFNCVTBF16_F_F_W 0x480e9057 +#define MASK_VFNCVTBF16_F_F_W 0xfc0ff07f +#define MATCH_VFWCVTBF16_F_F_V 0x48069057 +#define MASK_VFWCVTBF16_F_F_V 0xfc0ff07f /* Vendor-specific (CORE-V) Xcvmac instructions. */ #define MATCH_CV_MAC 0x9000302b #define MASK_CV_MAC 0xfe00707f @@ -3977,6 +3982,9 @@ DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) /* Zfbfmin instructions. */ DECLARE_INSN(FCVT_BF16_S, MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S) DECLARE_INSN(FCVT_S_BF16, MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16) +/* Zvfbfmin instructions. */ +DECLARE_INSN(VFNCVTBF16_F_F_W, MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W) +DECLARE_INSN(VFWCVTBF16_F_F_V, MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V) /* Zvbb/Zvkb instructions. */ DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV) DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index dfb8696..0641563 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -474,6 +474,7 @@ enum riscv_insn_class INSN_CLASS_ZVEF, INSN_CLASS_ZVBB, INSN_CLASS_ZVBC, + INSN_CLASS_ZVFBFMIN, INSN_CLASS_ZVKB, INSN_CLASS_ZVKG, INSN_CLASS_ZVKNED, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 1ccf068..eccd3f6 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2017,6 +2017,10 @@ const struct riscv_opcode riscv_opcodes[] = {"vmv4r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV4RV, MASK_VMV4RV, match_opcode, 0}, {"vmv8r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV8RV, MASK_VMV8RV, match_opcode, 0}, +/* Zvfbfmin instructions. */ +{"vfncvtbf16.f.f.w", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W, match_opcode, 0}, +{"vfwcvtbf16.f.f.v", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V, match_opcode, 0}, + /* Zvbb/Zvkb instructions. */ {"vandn.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VANDN_VV, MASK_VANDN_VV, match_opcode, 0}, {"vandn.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VANDN_VX, MASK_VANDN_VX, match_opcode, 0}, |