diff options
| -rw-r--r-- | sim/v850/ChangeLog | 5 | ||||
| -rw-r--r-- | sim/v850/sim-main.h | 20 | ||||
| -rw-r--r-- | sim/v850/simops.c | 18 | ||||
| -rw-r--r-- | sim/v850/v850.igen | 68 |
4 files changed, 77 insertions, 34 deletions
diff --git a/sim/v850/ChangeLog b/sim/v850/ChangeLog index 6474355..cfcf3bb 100644 --- a/sim/v850/ChangeLog +++ b/sim/v850/ChangeLog @@ -1,10 +1,11 @@ Fri Sep 19 10:37:20 1997 Andrew Cagney <cagney@b1.cygnus.com> * simops.c (condition_met): Make global. - * sim-main.h (TRACE_ALU_INPUT3): Define. + + * sim-main.h (TRACE_ALU_INPUT3, TRACE_BRANCH0): Define. start-sanitize-v850e - * simops.c (OP_32007E0): Move "cmov" to v850.igen, fix. + * simops.c: Move "cmov", "cmov imm" to v850.igen, fix. end-sanitize-v850e Wed Sep 17 16:21:08 1997 Andrew Cagney <cagney@b1.cygnus.com> diff --git a/sim/v850/sim-main.h b/sim/v850/sim-main.h index 2d1bf6a..99b508c 100644 --- a/sim/v850/sim-main.h +++ b/sim/v850/sim-main.h @@ -225,7 +225,7 @@ sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \ /* compare cccc field against PSW */ -unsigned int condition_met (unsigned code); +int condition_met (unsigned code); /* Debug/tracing calls */ @@ -334,6 +334,17 @@ do { \ } \ } while (0) +#define TRACE_BRANCH0() \ +do { \ + if (TRACE_BRANCH_P (CPU)) { \ + trace_module = "branch"; \ + trace_pc = cia; \ + trace_name = itable[MY_INDEX].name; \ + trace_num_values = 0; \ + trace_result (1, (nia)); \ + } \ +} while (0) + #define TRACE_BRANCH1(IN1) \ do { \ if (TRACE_BRANCH_P (CPU)) { \ @@ -380,10 +391,13 @@ do { \ #define trace_result(HAS_RESULT, RESULT) #define TRACE_ALU_INPUT0() -#define TRACE_ALU_INPUT1(IN1) -#define TRACE_ALU_INPUT2(IN1, IN2) +#define TRACE_ALU_INPUT1(IN0) +#define TRACE_ALU_INPUT2(IN0, IN1) +#define TRACE_ALU_INPUT2(IN0, IN1) +#define TRACE_ALU_INPUT2(IN0, IN1 INS2) #define TRACE_ALU_RESULT(RESULT) +#define TRACE_BRANCH0() #define TRACE_BRANCH1(IN1) #define TRACE_BRANCH2(IN1, IN2) #define TRACE_BRANCH2(IN1, IN2, IN3) diff --git a/sim/v850/simops.c b/sim/v850/simops.c index b55b430..c739d60 100644 --- a/sim/v850/simops.c +++ b/sim/v850/simops.c @@ -305,7 +305,7 @@ trace_output (result) /* Returns 1 if the specific condition is met, returns 0 otherwise. */ -unsigned int +int condition_met (unsigned code) { unsigned int psw = PSW; @@ -2711,22 +2711,6 @@ OP_24007E0 (void) /* end-sanitize-v850e */ /* start-sanitize-v850e */ -/* cmov imm5, reg2, reg3 */ -int -OP_30007E0 (void) -{ - trace_input ("cmov", OP_IMM_REG_REG, 0); - - State.regs[ OP[2] >> 11 ] = condition_met (OP[0]) ? SEXT5( OP[0] ) : State.regs[ OP[1] ]; - - trace_output (OP_IMM_REG_REG); - - return 4; - -} - -/* end-sanitize-v850e */ -/* start-sanitize-v850e */ /* ld.hu */ int OP_107E0 (void) diff --git a/sim/v850/v850.igen b/sim/v850/v850.igen index 192a302..5ff2dc5 100644 --- a/sim/v850/v850.igen +++ b/sim/v850/v850.igen @@ -121,9 +121,51 @@ rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi +// Map condition code to a string +:%s:::cccc:int cccc +{ + switch (cccc) + { + case 0xf: return "gt"; + case 0xe: return "ge"; + case 0x6: return "lt"; + + case 0x7: return "le"; + + case 0xb: return "h"; + case 0x9: return "nl"; + case 0x1: return "l"; + + case 0x3: return "nh"; + + case 0x2: return "e"; + + case 0xa: return "ne"; + + case 0x0: return "v"; + case 0x8: return "nv"; + case 0x4: return "n"; + case 0xc: return "p"; + /* case 0x1: return "c"; */ + /* case 0x9: return "nc"; */ + /* case 0x2: return "z"; */ + /* case 0xa: return "nz"; */ + case 0x5: return "r"; /* always */ + case 0xd: return "sa"; + } + return "(null)"; +} + + // Bcond // ddddd,1011,ddd,cccc:III:::Bcond -// "b<cond> disp9" +// "b%s<cccc> <disp9>" +// { +// int cond = condition_met (cccc); +// if (cond) +// nia = cia + disp9; +// TRACE_BRANCH1 (cond); +// } ddddd,1011,ddd,0000:III:::bv "bv <disp9>" @@ -351,10 +393,11 @@ rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov // start-sanitize-v850eq *v850eq // end-sanitize-v850eq -"cmov <cccc>, r<reg1>, r<reg2>, r<reg3>" +"cmov %s<cccc>, r<reg1>, r<reg2>, r<reg3>" { - TRACE_ALU_INPUT3 (cccc, GR[reg1], GR[reg2]); - GR[reg3] = condition_met (cccc) ? GR[reg1] : GR[reg2]; + int cond = condition_met (cccc); + TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]); + GR[reg3] = cond ? GR[reg1] : GR[reg2]; TRACE_ALU_RESULT (GR[reg3]); } @@ -365,9 +408,12 @@ rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov // start-sanitize-v850eq *v850eq // end-sanitize-v850eq -"cmov <cccc>, <imm5>, r<reg2>, r<reg3>" +"cmov %s<cccc>, <imm5>, r<reg2>, r<reg3>" { - COMPAT_2 (OP_30007E0 ()); + int cond = condition_met (cccc); + TRACE_ALU_INPUT3 (cond, imm5, GR[reg2]); + GR[reg3] = cond ? imm5 : GR[reg2]; + TRACE_ALU_RESULT (GR[reg3]); } @@ -552,10 +598,8 @@ rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl 00000000011,RRRRR:I:::jmp "jmp [r<reg1>]" { - SAVE_1; - trace_input ("jmp", OP_REG, 0); - nia = State.regs[ reg1 ]; - trace_output (OP_REG); + nia = GR[reg1]; + TRACE_BRANCH0 (); } @@ -933,7 +977,7 @@ rrrrr,1111110,cccc + 0000001000000000:IX:::sasf // start-sanitize-v850eq *v850eq // end-sanitize-v850eq -"sasf <cccc>, r<reg2>" +"sasf %s<cccc>, r<reg2>" { COMPAT_2 (OP_20007E0 ()); } @@ -986,7 +1030,7 @@ rrrrr!0,000100,RRRRR:I:::satsubr // SETF rrrrr,1111110,cccc + 0000000000000000:IX:::setf -"setf <cccc>, r<reg2>" +"setf %s<cccc>, r<reg2>" { COMPAT_2 (OP_7E0 ()); } |