diff options
| -rw-r--r-- | gas/ChangeLog | 5 | ||||
| -rw-r--r-- | gas/config/tc-aarch64.c | 4 | ||||
| -rw-r--r-- | gas/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sysreg-2.d | 3 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sysreg-2.s | 6 | ||||
| -rw-r--r-- | include/opcode/ChangeLog | 4 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 3 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.c | 16 |
9 files changed, 51 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 8b95bdd..aa6454e 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2015-12-10 Matthew Wahab <matthew.wahab@arm.com> + + * config/tc-aarch64.c (parse_sys_ins_reg): Add check of + architectural support for system register. + 2015-12-10 Jose E. Marchesi <jose.marchesi@oracle.com> * doc/c-sparc.texi (Sparc-Regs): Document the %dN and %qN notation diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index d306710..bb2f228 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -3687,6 +3687,10 @@ parse_sys_ins_reg (char **str, struct hash_control *sys_ins_regs) if (!o) return NULL; + if (!aarch64_sys_ins_reg_supported_p (cpu_variant, o)) + as_bad (_("selected processor does not support system register " + "name '%s'"), buf); + *str = q; return o; } diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index aecac6a..1a2f004 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,5 +1,10 @@ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> + * gas/aarch64/sysreg-2.d: Add tests for dc instruction. + * gas/aarch64/sysreg-2.s: Add uses of dc instruction. + +2015-12-10 Matthew Wahab <matthew.wahab@arm.com> + * gas/aarch64/uao-directive.d: New. * gas/aarch64/uao.d: New. * gas/aarch64/uao.s: New. diff --git a/gas/testsuite/gas/aarch64/sysreg-2.d b/gas/testsuite/gas/aarch64/sysreg-2.d index 31b9f33..dffe08f 100644 --- a/gas/testsuite/gas/aarch64/sysreg-2.d +++ b/gas/testsuite/gas/aarch64/sysreg-2.d @@ -27,3 +27,6 @@ Disassembly of section .text: [0-9a-f]+: d518c125 msr disr_el1, x5 [0-9a-f]+: d538c125 mrs x5, disr_el1 [0-9a-f]+: d53cc125 mrs x5, vdisr_el2 + [0-9a-f]+: d50b7a20 dc cvac, x0 + [0-9a-f]+: d50b7b21 dc cvau, x1 + [0-9a-f]+: d50b7c22 dc cvap, x2 diff --git a/gas/testsuite/gas/aarch64/sysreg-2.s b/gas/testsuite/gas/aarch64/sysreg-2.s index 2a6b06c..62b3a5e 100644 --- a/gas/testsuite/gas/aarch64/sysreg-2.s +++ b/gas/testsuite/gas/aarch64/sysreg-2.s @@ -30,3 +30,9 @@ rw_sys_reg sys_reg=vsesr_el2 xreg=x5 r=1 w=0 rw_sys_reg sys_reg=disr_el1 xreg=x5 r=1 w=1 rw_sys_reg sys_reg=vdisr_el2 xreg=x5 r=1 w=0 + + /* DC CVAP. */ + + dc cvac, x0 + dc cvau, x1 + dc cvap, x2 diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 2f06d4e..0a186e8 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,5 +1,9 @@ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> + * aarch64.h (aarch64_sys_ins_reg_supported_p): Declare. + +2015-12-10 Matthew Wahab <matthew.wahab@arm.com> + * aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags. (aarch64_sys_ins_reg_has_xt): Declare. diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index d0f6c3d..7477066 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -676,6 +676,9 @@ typedef struct } aarch64_sys_ins_reg; extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *); +extern bfd_boolean +aarch64_sys_ins_reg_supported_p (const aarch64_feature_set, + const aarch64_sys_ins_reg *); extern const aarch64_sys_ins_reg aarch64_sys_regs_ic []; extern const aarch64_sys_ins_reg aarch64_sys_regs_dc []; diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 9385878..3d84fbe 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,10 @@ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> + * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap". + (aarch64_sys_ins_reg_supported_p): New. + +2015-12-10 Matthew Wahab <matthew.wahab@arm.com> + * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt with aarch64_sys_ins_reg_has_xt. (aarch64_ext_sysins_op): Likewise. diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 2ae2f10..86aeae0 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -3264,6 +3264,7 @@ const aarch64_sys_ins_reg aarch64_sys_regs_dc[] = { "cvac", CPENS (3, C7, C10, 1), F_HASXT }, { "csw", CPENS (0, C7, C10, 2), F_HASXT }, { "cvau", CPENS (3, C7, C11, 1), F_HASXT }, + { "cvap", CPENS (3, C7, C12, 1), F_HASXT | F_ARCHEXT }, { "civac", CPENS (3, C7, C14, 1), F_HASXT }, { "cisw", CPENS (0, C7, C14, 2), F_HASXT }, { 0, CPENS(0,0,0,0), 0 } @@ -3329,6 +3330,21 @@ aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *sys_ins_reg) return (sys_ins_reg->flags & F_HASXT) != 0; } +extern bfd_boolean +aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features, + const aarch64_sys_ins_reg *reg) +{ + if (!(reg->flags & F_ARCHEXT)) + return TRUE; + + /* DC CVAP. Values are from aarch64_sys_regs_dc. */ + if (reg->value == CPENS (3, C7, C12, 1) + && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2)) + return FALSE; + + return TRUE; +} + #undef C0 #undef C1 #undef C2 |