diff options
| -rw-r--r-- | gas/ChangeLog | 4 | ||||
| -rw-r--r-- | gas/config/tc-arm.c | 4 | ||||
| -rw-r--r-- | gas/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/thumb32.d | 38 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/thumb32.s | 23 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 4 | ||||
| -rw-r--r-- | opcodes/arm-dis.c | 6 |
7 files changed, 80 insertions, 4 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 15c33fa..f1b6890 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,7 @@ +2007-06-05 Paul Brook <paul@codesourcery.com> + + * config/tc-arm.c (insns): Correct Thumb-2 ldrd/strd opcodes. + 2007-06-05 Nick Clifton <nickc@redhat.com> PR gas/4587 diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 03f97d7..ca9e337 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -15017,8 +15017,8 @@ static const struct asm_opcode insns[] = #undef ARM_VARIANT #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */ TUF(pld, 450f000, f810f000, 1, (ADDR), pld, t_pld), - TC3(ldrd, 00000d0, e9500000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd), - TC3(strd, 00000f0, e9400000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd), + TC3(ldrd, 00000d0, e8500000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd), + TC3(strd, 00000f0, e8400000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd), TCE(mcrr, c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), TCE(mrrc, c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 4bd0290..d118298 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2007-06-05 Paul Brook <paul@codesourcery.com> + + * gas/arm/thumb32.d: Add writeback addressing mode tests. + * gas/arm/thumb32.s: Update expected output. + 2007-06-05 Nick Clifton <nickc@redhat.com> PR gas/4587 diff --git a/gas/testsuite/gas/arm/thumb32.d b/gas/testsuite/gas/arm/thumb32.d index ea68ec6..5bb76a5 100644 --- a/gas/testsuite/gas/arm/thumb32.d +++ b/gas/testsuite/gas/arm/thumb32.d @@ -963,3 +963,41 @@ Disassembly of section .text: 0[0-9a-f]+ <[^>]+> f3de 8f00 subs pc, lr, #0 0[0-9a-f]+ <[^>]+> f3de 8f04 subs pc, lr, #4 0[0-9a-f]+ <[^>]+> f3de 8fff subs pc, lr, #255 +0[0-9a-f]+ <[^>]+> e9f9 240c ldrd r2, r4, \[r9, #48\]! +0[0-9a-f]+ <[^>]+> e979 240c ldrd r2, r4, \[r9, #-48\]! +0[0-9a-f]+ <[^>]+> e9e9 240c strd r2, r4, \[r9, #48\]! +0[0-9a-f]+ <[^>]+> e969 240c strd r2, r4, \[r9, #-48\]! +0[0-9a-f]+ <[^>]+> e8f9 240c ldrd r2, r4, \[r9\], #48 +0[0-9a-f]+ <[^>]+> e879 240c ldrd r2, r4, \[r9\], #-48 +0[0-9a-f]+ <[^>]+> e8e9 240c strd r2, r4, \[r9\], #48 +0[0-9a-f]+ <[^>]+> e869 240c strd r2, r4, \[r9\], #-48 +0[0-9a-f]+ <[^>]+> f8d5 1301 ldr.w r1, \[r5, #769] +0[0-9a-f]+ <[^>]+> f855 1f30 ldr.w r1, \[r5, #48]! +0[0-9a-f]+ <[^>]+> f855 1d30 ldr.w r1, \[r5, #-48]! +0[0-9a-f]+ <[^>]+> f855 1b30 ldr.w r1, \[r5\], #48 +0[0-9a-f]+ <[^>]+> f855 1930 ldr.w r1, \[r5\], #-48 +0[0-9a-f]+ <[^>]+> f855 1009 ldr.w r1, \[r5, r9\] +0[0-9a-f]+ <[^>]+> f895 1301 ldrb.w r1, \[r5, #769] +0[0-9a-f]+ <[^>]+> f815 1f30 ldrb.w r1, \[r5, #48]! +0[0-9a-f]+ <[^>]+> f815 1d30 ldrb.w r1, \[r5, #-48]! +0[0-9a-f]+ <[^>]+> f815 1b30 ldrb.w r1, \[r5\], #48 +0[0-9a-f]+ <[^>]+> f815 1930 ldrb.w r1, \[r5\], #-48 +0[0-9a-f]+ <[^>]+> f815 1009 ldrb.w r1, \[r5, r9\] +0[0-9a-f]+ <[^>]+> f995 1301 ldrsb.w r1, \[r5, #769] +0[0-9a-f]+ <[^>]+> f915 1f30 ldrsb.w r1, \[r5, #48]! +0[0-9a-f]+ <[^>]+> f915 1d30 ldrsb.w r1, \[r5, #-48]! +0[0-9a-f]+ <[^>]+> f915 1b30 ldrsb.w r1, \[r5\], #48 +0[0-9a-f]+ <[^>]+> f915 1930 ldrsb.w r1, \[r5\], #-48 +0[0-9a-f]+ <[^>]+> f915 1009 ldrsb.w r1, \[r5, r9\] +0[0-9a-f]+ <[^>]+> f8b5 1301 ldrh.w r1, \[r5, #769] +0[0-9a-f]+ <[^>]+> f835 1f30 ldrh.w r1, \[r5, #48]! +0[0-9a-f]+ <[^>]+> f835 1d30 ldrh.w r1, \[r5, #-48]! +0[0-9a-f]+ <[^>]+> f835 1b30 ldrh.w r1, \[r5\], #48 +0[0-9a-f]+ <[^>]+> f835 1930 ldrh.w r1, \[r5\], #-48 +0[0-9a-f]+ <[^>]+> f835 1009 ldrh.w r1, \[r5, r9\] +0[0-9a-f]+ <[^>]+> f9b5 1301 ldrsh.w r1, \[r5, #769] +0[0-9a-f]+ <[^>]+> f935 1f30 ldrsh.w r1, \[r5, #48]! +0[0-9a-f]+ <[^>]+> f935 1d30 ldrsh.w r1, \[r5, #-48]! +0[0-9a-f]+ <[^>]+> f935 1b30 ldrsh.w r1, \[r5\], #48 +0[0-9a-f]+ <[^>]+> f935 1930 ldrsh.w r1, \[r5\], #-48 +0[0-9a-f]+ <[^>]+> f935 1009 ldrsh.w r1, \[r5, r9\] diff --git a/gas/testsuite/gas/arm/thumb32.s b/gas/testsuite/gas/arm/thumb32.s index 7079ea6..4f602df 100644 --- a/gas/testsuite/gas/arm/thumb32.s +++ b/gas/testsuite/gas/arm/thumb32.s @@ -780,3 +780,26 @@ srs: subs pc, lr, #0 subs pc, lr, #4 subs pc, lr, #255 + + ldrd r2, r4, [r9, #48]! + ldrd r2, r4, [r9, #-48]! + strd r2, r4, [r9, #48]! + strd r2, r4, [r9, #-48]! + ldrd r2, r4, [r9], #48 + ldrd r2, r4, [r9], #-48 + strd r2, r4, [r9], #48 + strd r2, r4, [r9], #-48 + + .macro ldaddr op + ldr\op r1, [r5, #0x301] + ldr\op r1, [r5, #0x30]! + ldr\op r1, [r5, #-0x30]! + ldr\op r1, [r5], #0x30 + ldr\op r1, [r5], #-0x30 + ldr\op r1, [r5, r9] + .endm + ldaddr + ldaddr b + ldaddr sb + ldaddr h + ldaddr sh diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 6cb2ef4..b664be9 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +2007-06-05 Paul Brook <paul@codesourcery.com> + + * arm-dis.c (thumb32_opcodes): Display writeback ldrd/strd addresses. + 2007-05-24 Steve Ellcey <sje@cup.hp.com> * Makefile.in: Regnerate. diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index cf67b5f..c39aa51 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -1403,8 +1403,10 @@ static const struct opcode32 thumb32_opcodes[] = {ARM_EXT_V6T2, 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"}, {ARM_EXT_V6T2, 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"}, {ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"}, - {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]"}, - {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]"}, + {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!"}, + {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!"}, + {ARM_EXT_V6T2, 0xe8600000, 0xff700000, "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W"}, + {ARM_EXT_V6T2, 0xe8700000, 0xff700000, "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W"}, {ARM_EXT_V6T2, 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"}, {ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"}, |