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-rw-r--r--gas/testsuite/ChangeLog6
-rw-r--r--gas/testsuite/gas/aarch64/virthostext-directive.d65
-rw-r--r--gas/testsuite/gas/aarch64/virthostext.d65
-rw-r--r--gas/testsuite/gas/aarch64/virthostext.s69
-rw-r--r--include/opcode/ChangeLog5
-rw-r--r--include/opcode/aarch64.h2
-rw-r--r--opcodes/ChangeLog12
-rw-r--r--opcodes/aarch64-opc.c66
8 files changed, 290 insertions, 0 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 6492617..755f619 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2015-11-20 Matthew Wahab <matthew.wahab@arm.com>
+
+ * gas/aarch64/virthostext-directive.d: New.
+ * gas/aarch64/virthostext.d: New.
+ * gas/aarch64/virthostext.s: New.
+
2015-11-20 Matthew Wahab <matthew.wahab@foss.arm.com>
* gas/arm/mapshort-elf.d: Fix typo in exclusion list.
diff --git a/gas/testsuite/gas/aarch64/virthostext-directive.d b/gas/testsuite/gas/aarch64/virthostext-directive.d
new file mode 100644
index 0000000..73baf9a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/virthostext-directive.d
@@ -0,0 +1,65 @@
+#objdump: -dr
+#as: --defsym DIRECTIVE=1
+#source: virthostext.s
+
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ [0-9a-f]+: d51d4007 msr spsr_el12, x7
+ [0-9a-f]+: d53d4007 mrs x7, spsr_el12
+ [0-9a-f]+: d51d4027 msr elr_el12, x7
+ [0-9a-f]+: d53d4027 mrs x7, elr_el12
+ [0-9a-f]+: d51d1007 msr sctlr_el12, x7
+ [0-9a-f]+: d53d1007 mrs x7, sctlr_el12
+ [0-9a-f]+: d51d1047 msr cpacr_el12, x7
+ [0-9a-f]+: d53d1047 mrs x7, cpacr_el12
+ [0-9a-f]+: d51c2027 msr ttbr1_el2, x7
+ [0-9a-f]+: d53c2027 mrs x7, ttbr1_el2
+ [0-9a-f]+: d51d2007 msr ttbr0_el12, x7
+ [0-9a-f]+: d53d2007 mrs x7, ttbr0_el12
+ [0-9a-f]+: d51d2027 msr ttbr1_el12, x7
+ [0-9a-f]+: d53d2027 mrs x7, ttbr1_el12
+ [0-9a-f]+: d51d2047 msr tcr_el12, x7
+ [0-9a-f]+: d53d2047 mrs x7, tcr_el12
+ [0-9a-f]+: d51d5107 msr afsr0_el12, x7
+ [0-9a-f]+: d53d5107 mrs x7, afsr0_el12
+ [0-9a-f]+: d51d5127 msr afsr1_el12, x7
+ [0-9a-f]+: d53d5127 mrs x7, afsr1_el12
+ [0-9a-f]+: d51d5207 msr esr_el12, x7
+ [0-9a-f]+: d53d5207 mrs x7, esr_el12
+ [0-9a-f]+: d51d6007 msr far_el12, x7
+ [0-9a-f]+: d53d6007 mrs x7, far_el12
+ [0-9a-f]+: d51da207 msr mair_el12, x7
+ [0-9a-f]+: d53da207 mrs x7, mair_el12
+ [0-9a-f]+: d51da307 msr amair_el12, x7
+ [0-9a-f]+: d53da307 mrs x7, amair_el12
+ [0-9a-f]+: d51dc007 msr vbar_el12, x7
+ [0-9a-f]+: d53dc007 mrs x7, vbar_el12
+ [0-9a-f]+: d51cd027 msr contextidr_el2, x7
+ [0-9a-f]+: d53cd027 mrs x7, contextidr_el2
+ [0-9a-f]+: d51dd027 msr contextidr_el12, x7
+ [0-9a-f]+: d53dd027 mrs x7, contextidr_el12
+ [0-9a-f]+: d51de107 msr cntkctl_el12, x7
+ [0-9a-f]+: d53de107 mrs x7, cntkctl_el12
+ [0-9a-f]+: d51de207 msr cntp_tval_el02, x7
+ [0-9a-f]+: d53de207 mrs x7, cntp_tval_el02
+ [0-9a-f]+: d51de227 msr cntp_ctl_el02, x7
+ [0-9a-f]+: d53de227 mrs x7, cntp_ctl_el02
+ [0-9a-f]+: d51de247 msr cntp_cval_el02, x7
+ [0-9a-f]+: d53de247 mrs x7, cntp_cval_el02
+ [0-9a-f]+: d51de307 msr cntv_tval_el02, x7
+ [0-9a-f]+: d53de307 mrs x7, cntv_tval_el02
+ [0-9a-f]+: d51de327 msr cntv_ctl_el02, x7
+ [0-9a-f]+: d53de327 mrs x7, cntv_ctl_el02
+ [0-9a-f]+: d51de347 msr cntv_cval_el02, x7
+ [0-9a-f]+: d53de347 mrs x7, cntv_cval_el02
+ [0-9a-f]+: d51ce307 msr cnthv_tval_el2, x7
+ [0-9a-f]+: d53ce307 mrs x7, cnthv_tval_el2
+ [0-9a-f]+: d51ce327 msr cnthv_ctl_el2, x7
+ [0-9a-f]+: d53ce327 mrs x7, cnthv_ctl_el2
+ [0-9a-f]+: d51ce347 msr cnthv_cval_el2, x7
+ [0-9a-f]+: d53ce347 mrs x7, cnthv_cval_el2
diff --git a/gas/testsuite/gas/aarch64/virthostext.d b/gas/testsuite/gas/aarch64/virthostext.d
new file mode 100644
index 0000000..a5960ee
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/virthostext.d
@@ -0,0 +1,65 @@
+#objdump: -dr
+#as: -march=armv8.1-a
+#source: virthostext.s
+
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ [0-9a-f]+: d51d4007 msr spsr_el12, x7
+ [0-9a-f]+: d53d4007 mrs x7, spsr_el12
+ [0-9a-f]+: d51d4027 msr elr_el12, x7
+ [0-9a-f]+: d53d4027 mrs x7, elr_el12
+ [0-9a-f]+: d51d1007 msr sctlr_el12, x7
+ [0-9a-f]+: d53d1007 mrs x7, sctlr_el12
+ [0-9a-f]+: d51d1047 msr cpacr_el12, x7
+ [0-9a-f]+: d53d1047 mrs x7, cpacr_el12
+ [0-9a-f]+: d51c2027 msr ttbr1_el2, x7
+ [0-9a-f]+: d53c2027 mrs x7, ttbr1_el2
+ [0-9a-f]+: d51d2007 msr ttbr0_el12, x7
+ [0-9a-f]+: d53d2007 mrs x7, ttbr0_el12
+ [0-9a-f]+: d51d2027 msr ttbr1_el12, x7
+ [0-9a-f]+: d53d2027 mrs x7, ttbr1_el12
+ [0-9a-f]+: d51d2047 msr tcr_el12, x7
+ [0-9a-f]+: d53d2047 mrs x7, tcr_el12
+ [0-9a-f]+: d51d5107 msr afsr0_el12, x7
+ [0-9a-f]+: d53d5107 mrs x7, afsr0_el12
+ [0-9a-f]+: d51d5127 msr afsr1_el12, x7
+ [0-9a-f]+: d53d5127 mrs x7, afsr1_el12
+ [0-9a-f]+: d51d5207 msr esr_el12, x7
+ [0-9a-f]+: d53d5207 mrs x7, esr_el12
+ [0-9a-f]+: d51d6007 msr far_el12, x7
+ [0-9a-f]+: d53d6007 mrs x7, far_el12
+ [0-9a-f]+: d51da207 msr mair_el12, x7
+ [0-9a-f]+: d53da207 mrs x7, mair_el12
+ [0-9a-f]+: d51da307 msr amair_el12, x7
+ [0-9a-f]+: d53da307 mrs x7, amair_el12
+ [0-9a-f]+: d51dc007 msr vbar_el12, x7
+ [0-9a-f]+: d53dc007 mrs x7, vbar_el12
+ [0-9a-f]+: d51cd027 msr contextidr_el2, x7
+ [0-9a-f]+: d53cd027 mrs x7, contextidr_el2
+ [0-9a-f]+: d51dd027 msr contextidr_el12, x7
+ [0-9a-f]+: d53dd027 mrs x7, contextidr_el12
+ [0-9a-f]+: d51de107 msr cntkctl_el12, x7
+ [0-9a-f]+: d53de107 mrs x7, cntkctl_el12
+ [0-9a-f]+: d51de207 msr cntp_tval_el02, x7
+ [0-9a-f]+: d53de207 mrs x7, cntp_tval_el02
+ [0-9a-f]+: d51de227 msr cntp_ctl_el02, x7
+ [0-9a-f]+: d53de227 mrs x7, cntp_ctl_el02
+ [0-9a-f]+: d51de247 msr cntp_cval_el02, x7
+ [0-9a-f]+: d53de247 mrs x7, cntp_cval_el02
+ [0-9a-f]+: d51de307 msr cntv_tval_el02, x7
+ [0-9a-f]+: d53de307 mrs x7, cntv_tval_el02
+ [0-9a-f]+: d51de327 msr cntv_ctl_el02, x7
+ [0-9a-f]+: d53de327 mrs x7, cntv_ctl_el02
+ [0-9a-f]+: d51de347 msr cntv_cval_el02, x7
+ [0-9a-f]+: d53de347 mrs x7, cntv_cval_el02
+ [0-9a-f]+: d51ce307 msr cnthv_tval_el2, x7
+ [0-9a-f]+: d53ce307 mrs x7, cnthv_tval_el2
+ [0-9a-f]+: d51ce327 msr cnthv_ctl_el2, x7
+ [0-9a-f]+: d53ce327 mrs x7, cnthv_ctl_el2
+ [0-9a-f]+: d51ce347 msr cnthv_cval_el2, x7
+ [0-9a-f]+: d53ce347 mrs x7, cnthv_cval_el2
diff --git a/gas/testsuite/gas/aarch64/virthostext.s b/gas/testsuite/gas/aarch64/virthostext.s
new file mode 100644
index 0000000..6bf2369
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/virthostext.s
@@ -0,0 +1,69 @@
+/* virthostext.s Test file for ARMv8.1 Virtualization Host Extension
+ support.
+
+ Copyright (C) 2015 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+ .macro rw_sys_reg sys_reg xreg
+ msr \sys_reg, \xreg
+ mrs \xreg, \sys_reg
+ .endm
+
+ .text
+ .ifdef DIRECTIVE
+ .arch armv8.1-a
+ .endif
+
+ rw_sys_reg spsr_el12 x7
+ rw_sys_reg elr_el12 x7
+
+ rw_sys_reg sctlr_el12 x7
+ rw_sys_reg cpacr_el12 x7
+
+ rw_sys_reg ttbr1_el2 x7
+ rw_sys_reg ttbr0_el12 x7
+ rw_sys_reg ttbr1_el12 x7
+
+ rw_sys_reg tcr_el12 x7
+
+ rw_sys_reg afsr0_el12 x7
+ rw_sys_reg afsr1_el12 x7
+
+ rw_sys_reg esr_el12 x7
+ rw_sys_reg far_el12 x7
+ rw_sys_reg mair_el12 x7
+ rw_sys_reg amair_el12 x7
+ rw_sys_reg vbar_el12 x7
+
+ rw_sys_reg contextidr_el2 x7
+ rw_sys_reg contextidr_el12 x7
+
+ rw_sys_reg cntkctl_el12 x7
+
+ rw_sys_reg cntp_tval_el02 x7
+ rw_sys_reg cntp_ctl_el02 x7
+ rw_sys_reg cntp_cval_el02 x7
+
+ rw_sys_reg cntv_tval_el02 x7
+ rw_sys_reg cntv_ctl_el02 x7
+ rw_sys_reg cntv_cval_el02 x7
+
+ rw_sys_reg cnthv_tval_el2 x7
+ rw_sys_reg cnthv_ctl_el2 x7
+ rw_sys_reg cnthv_cval_el2 x7
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 16feca1..a682414 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,8 @@
+2015-11-20 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64.h (AARCH64_FEATURE_V8_1): New.
+ (AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1.
+
2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
* arm.h (ARM_EXT2_V8_2A): New.
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index fcec92b..9addf40 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -47,6 +47,7 @@ typedef uint32_t aarch64_insn;
#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
+#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
/* Architectures are the sum of the base and extensions. */
#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
@@ -55,6 +56,7 @@ typedef uint32_t aarch64_insn;
#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
AARCH64_FEATURE_FP \
| AARCH64_FEATURE_SIMD \
+ | AARCH64_FEATURE_V8_1 \
| AARCH64_FEATURE_LSE \
| AARCH64_FEATURE_PAN \
| AARCH64_FEATURE_LOR \
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 3eb88d4..c661b9a 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,15 @@
+2015-11-20 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
+ sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
+ tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
+ amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
+ cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
+ cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
+ cnthv_ctl_el2, cnthv_cval_el2.
+ (aarch64_sys_reg_supported_p): Update for the new system
+ registers.
+
2015-11-20 Nick Clifton <nickc@redhat.com>
PR binutils/19224
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 50dbd36..a19f36f 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -2743,7 +2743,9 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
const aarch64_sys_reg aarch64_sys_regs [] =
{
{ "spsr_el1", CPEN_(0,C0,0), 0 }, /* = spsr_svc */
+ { "spsr_el12", CPEN_ (5, C0, 0), F_ARCHEXT },
{ "elr_el1", CPEN_(0,C0,1), 0 },
+ { "elr_el12", CPEN_ (5, C0, 1), F_ARCHEXT },
{ "sp_el0", CPEN_(0,C1,0), 0 },
{ "spsel", CPEN_(0,C2,0), 0 },
{ "daif", CPEN_(3,C2,1), 0 },
@@ -2808,10 +2810,12 @@ const aarch64_sys_reg aarch64_sys_regs [] =
{ "sctlr_el1", CPENC(3,0,C1,C0,0), 0 },
{ "sctlr_el2", CPENC(3,4,C1,C0,0), 0 },
{ "sctlr_el3", CPENC(3,6,C1,C0,0), 0 },
+ { "sctlr_el12", CPENC (3, 5, C1, C0, 0), F_ARCHEXT },
{ "actlr_el1", CPENC(3,0,C1,C0,1), 0 },
{ "actlr_el2", CPENC(3,4,C1,C0,1), 0 },
{ "actlr_el3", CPENC(3,6,C1,C0,1), 0 },
{ "cpacr_el1", CPENC(3,0,C1,C0,2), 0 },
+ { "cpacr_el12", CPENC (3, 5, C1, C0, 2), F_ARCHEXT },
{ "cptr_el2", CPENC(3,4,C1,C1,2), 0 },
{ "cptr_el3", CPENC(3,6,C1,C1,2), 0 },
{ "scr_el3", CPENC(3,6,C1,C1,0), 0 },
@@ -2823,36 +2827,47 @@ const aarch64_sys_reg aarch64_sys_regs [] =
{ "ttbr0_el1", CPENC(3,0,C2,C0,0), 0 },
{ "ttbr1_el1", CPENC(3,0,C2,C0,1), 0 },
{ "ttbr0_el2", CPENC(3,4,C2,C0,0), 0 },
+ { "ttbr1_el2", CPENC (3, 4, C2, C0, 1), F_ARCHEXT },
{ "ttbr0_el3", CPENC(3,6,C2,C0,0), 0 },
+ { "ttbr0_el12", CPENC (3, 5, C2, C0, 0), F_ARCHEXT },
+ { "ttbr1_el12", CPENC (3, 5, C2, C0, 1), F_ARCHEXT },
{ "vttbr_el2", CPENC(3,4,C2,C1,0), 0 },
{ "tcr_el1", CPENC(3,0,C2,C0,2), 0 },
{ "tcr_el2", CPENC(3,4,C2,C0,2), 0 },
{ "tcr_el3", CPENC(3,6,C2,C0,2), 0 },
+ { "tcr_el12", CPENC (3, 5, C2, C0, 2), F_ARCHEXT },
{ "vtcr_el2", CPENC(3,4,C2,C1,2), 0 },
{ "afsr0_el1", CPENC(3,0,C5,C1,0), 0 },
{ "afsr1_el1", CPENC(3,0,C5,C1,1), 0 },
{ "afsr0_el2", CPENC(3,4,C5,C1,0), 0 },
{ "afsr1_el2", CPENC(3,4,C5,C1,1), 0 },
{ "afsr0_el3", CPENC(3,6,C5,C1,0), 0 },
+ { "afsr0_el12", CPENC (3, 5, C5, C1, 0), F_ARCHEXT },
{ "afsr1_el3", CPENC(3,6,C5,C1,1), 0 },
+ { "afsr1_el12", CPENC (3, 5, C5, C1, 1), F_ARCHEXT },
{ "esr_el1", CPENC(3,0,C5,C2,0), 0 },
{ "esr_el2", CPENC(3,4,C5,C2,0), 0 },
{ "esr_el3", CPENC(3,6,C5,C2,0), 0 },
+ { "esr_el12", CPENC (3, 5, C5, C2, 0), F_ARCHEXT },
{ "fpexc32_el2", CPENC(3,4,C5,C3,0), 0 },
{ "far_el1", CPENC(3,0,C6,C0,0), 0 },
{ "far_el2", CPENC(3,4,C6,C0,0), 0 },
{ "far_el3", CPENC(3,6,C6,C0,0), 0 },
+ { "far_el12", CPENC (3, 5, C6, C0, 0), F_ARCHEXT },
{ "hpfar_el2", CPENC(3,4,C6,C0,4), 0 },
{ "par_el1", CPENC(3,0,C7,C4,0), 0 },
{ "mair_el1", CPENC(3,0,C10,C2,0), 0 },
{ "mair_el2", CPENC(3,4,C10,C2,0), 0 },
{ "mair_el3", CPENC(3,6,C10,C2,0), 0 },
+ { "mair_el12", CPENC (3, 5, C10, C2, 0), F_ARCHEXT },
{ "amair_el1", CPENC(3,0,C10,C3,0), 0 },
{ "amair_el2", CPENC(3,4,C10,C3,0), 0 },
{ "amair_el3", CPENC(3,6,C10,C3,0), 0 },
+ { "amair_el12", CPENC (3, 5, C10, C3, 0), F_ARCHEXT },
{ "vbar_el1", CPENC(3,0,C12,C0,0), 0 },
{ "vbar_el2", CPENC(3,4,C12,C0,0), 0 },
{ "vbar_el3", CPENC(3,6,C12,C0,0), 0 },
+ { "vbar_el12", CPENC (3, 5, C12, C0, 0), F_ARCHEXT },
{ "rvbar_el1", CPENC(3,0,C12,C0,1), 0 }, /* RO */
{ "rvbar_el2", CPENC(3,4,C12,C0,1), 0 }, /* RO */
{ "rvbar_el3", CPENC(3,6,C12,C0,1), 0 }, /* RO */
@@ -2861,6 +2876,8 @@ const aarch64_sys_reg aarch64_sys_regs [] =
{ "rmr_el3", CPENC(3,6,C12,C0,2), 0 },
{ "isr_el1", CPENC(3,0,C12,C1,0), 0 }, /* RO */
{ "contextidr_el1", CPENC(3,0,C13,C0,1), 0 },
+ { "contextidr_el2", CPENC (3, 4, C13, C0, 1), F_ARCHEXT },
+ { "contextidr_el12", CPENC (3, 5, C13, C0, 1), F_ARCHEXT },
{ "tpidr_el0", CPENC(3,3,C13,C0,2), 0 },
{ "tpidrro_el0", CPENC(3,3,C13,C0,3), 0 }, /* RO */
{ "tpidr_el1", CPENC(3,0,C13,C0,4), 0 },
@@ -2872,19 +2889,29 @@ const aarch64_sys_reg aarch64_sys_regs [] =
{ "cntvct_el0", CPENC(3,3,C14,C0,2), 0 }, /* RO */
{ "cntvoff_el2", CPENC(3,4,C14,C0,3), 0 },
{ "cntkctl_el1", CPENC(3,0,C14,C1,0), 0 },
+ { "cntkctl_el12", CPENC (3, 5, C14, C1, 0), F_ARCHEXT },
{ "cnthctl_el2", CPENC(3,4,C14,C1,0), 0 },
{ "cntp_tval_el0", CPENC(3,3,C14,C2,0), 0 },
+ { "cntp_tval_el02", CPENC (3, 5, C14, C2, 0), F_ARCHEXT },
{ "cntp_ctl_el0", CPENC(3,3,C14,C2,1), 0 },
+ { "cntp_ctl_el02", CPENC (3, 5, C14, C2, 1), F_ARCHEXT },
{ "cntp_cval_el0", CPENC(3,3,C14,C2,2), 0 },
+ { "cntp_cval_el02", CPENC (3, 5, C14, C2, 2), F_ARCHEXT },
{ "cntv_tval_el0", CPENC(3,3,C14,C3,0), 0 },
+ { "cntv_tval_el02", CPENC (3, 5, C14, C3, 0), F_ARCHEXT },
{ "cntv_ctl_el0", CPENC(3,3,C14,C3,1), 0 },
+ { "cntv_ctl_el02", CPENC (3, 5, C14, C3, 1), F_ARCHEXT },
{ "cntv_cval_el0", CPENC(3,3,C14,C3,2), 0 },
+ { "cntv_cval_el02", CPENC (3, 5, C14, C3, 2), F_ARCHEXT },
{ "cnthp_tval_el2", CPENC(3,4,C14,C2,0), 0 },
{ "cnthp_ctl_el2", CPENC(3,4,C14,C2,1), 0 },
{ "cnthp_cval_el2", CPENC(3,4,C14,C2,2), 0 },
{ "cntps_tval_el1", CPENC(3,7,C14,C2,0), 0 },
{ "cntps_ctl_el1", CPENC(3,7,C14,C2,1), 0 },
{ "cntps_cval_el1", CPENC(3,7,C14,C2,2), 0 },
+ { "cnthv_tval_el2", CPENC (3, 4, C14, C3, 0), F_ARCHEXT },
+ { "cnthv_ctl_el2", CPENC (3, 4, C14, C3, 1), F_ARCHEXT },
+ { "cnthv_cval_el2", CPENC (3, 4, C14, C3, 2), F_ARCHEXT },
{ "dacr32_el2", CPENC(3,4,C3,C0,0), 0 },
{ "ifsr32_el2", CPENC(3,4,C5,C0,1), 0 },
{ "teehbr32_el1", CPENC(2,2,C1,C0,0), 0 },
@@ -3071,6 +3098,45 @@ aarch64_sys_reg_supported_p (const aarch64_feature_set features,
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
return FALSE;
+ /* Virtualization host extensions: system registers. */
+ if ((reg->value == CPENC (3, 4, C2, C0, 1)
+ || reg->value == CPENC (3, 4, C13, C0, 1)
+ || reg->value == CPENC (3, 4, C14, C3, 0)
+ || reg->value == CPENC (3, 4, C14, C3, 1)
+ || reg->value == CPENC (3, 4, C14, C3, 2))
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
+ return FALSE;
+
+ /* Virtualization host extensions: *_el12 names of *_el1 registers. */
+ if ((reg->value == CPEN_ (5, C0, 0)
+ || reg->value == CPEN_ (5, C0, 1)
+ || reg->value == CPENC (3, 5, C1, C0, 0)
+ || reg->value == CPENC (3, 5, C1, C0, 2)
+ || reg->value == CPENC (3, 5, C2, C0, 0)
+ || reg->value == CPENC (3, 5, C2, C0, 1)
+ || reg->value == CPENC (3, 5, C2, C0, 2)
+ || reg->value == CPENC (3, 5, C5, C1, 0)
+ || reg->value == CPENC (3, 5, C5, C1, 1)
+ || reg->value == CPENC (3, 5, C5, C2, 0)
+ || reg->value == CPENC (3, 5, C6, C0, 0)
+ || reg->value == CPENC (3, 5, C10, C2, 0)
+ || reg->value == CPENC (3, 5, C10, C3, 0)
+ || reg->value == CPENC (3, 5, C12, C0, 0)
+ || reg->value == CPENC (3, 5, C13, C0, 1)
+ || reg->value == CPENC (3, 5, C14, C1, 0))
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
+ return FALSE;
+
+ /* Virtualization host extensions: *_el02 names of *_el0 registers. */
+ if ((reg->value == CPENC (3, 5, C14, C2, 0)
+ || reg->value == CPENC (3, 5, C14, C2, 1)
+ || reg->value == CPENC (3, 5, C14, C2, 2)
+ || reg->value == CPENC (3, 5, C14, C3, 0)
+ || reg->value == CPENC (3, 5, C14, C3, 1)
+ || reg->value == CPENC (3, 5, C14, C3, 2))
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
+ return FALSE;
+
return TRUE;
}
generated by cgit v1.1 at 2024-11-26 15:26:12 +0000