diff options
| -rw-r--r-- | bfd/ChangeLog | 5 | ||||
| -rw-r--r-- | bfd/elf32-v850.c | 8 | ||||
| -rw-r--r-- | include/opcode/ChangeLog | 4 | ||||
| -rw-r--r-- | include/opcode/v850.h | 3 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 22 | ||||
| -rw-r--r-- | opcodes/v850-dis.c | 3 | ||||
| -rw-r--r-- | opcodes/v850-opc.c | 24 |
7 files changed, 60 insertions, 9 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog index bbcb8b5..c2a14b0 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,8 @@ +2013-04-03 Nick Clifton <nickc@redhat.com> + + * elf32-v850.c (v850_elf_is_target_special_symbol): New function. + (bfd_elf32_bfd_is_target_special_symbol): Define. + 2013-04-03 Venkataramanan Kumar <venkataramanan.kumar@linaro.org> * elf64-aarch64.c (elf64_aarch64_gc_sweep_hook): Use diff --git a/bfd/elf32-v850.c b/bfd/elf32-v850.c index c0c6498..7516ceb 100644 --- a/bfd/elf32-v850.c +++ b/bfd/elf32-v850.c @@ -1920,6 +1920,12 @@ v850_elf_is_local_label_name (bfd *abfd ATTRIBUTE_UNUSED, const char *name) return ( (name[0] == '.' && (name[1] == 'L' || name[1] == '.')) || (name[0] == '_' && name[1] == '.' && name[2] == 'L' && name[3] == '_')); } + +static bfd_boolean +v850_elf_is_target_special_symbol (bfd *abfd, asymbol *sym) +{ + return v850_elf_is_local_label_name (abfd, sym->name); +} /* We overload some of the bfd_reloc error codes for own purposes. */ #define bfd_reloc_gp_not_found bfd_reloc_other @@ -3791,6 +3797,8 @@ static const struct bfd_elf_special_section v850_elf_special_sections[] = #define elf_backend_rela_normal 1 #define bfd_elf32_bfd_is_local_label_name v850_elf_is_local_label_name +#define bfd_elf32_bfd_is_target_special_symbol v850_elf_is_target_special_symbol + #define bfd_elf32_bfd_reloc_type_lookup v850_elf_reloc_type_lookup #define bfd_elf32_bfd_reloc_name_lookup v850_elf_reloc_name_lookup #define bfd_elf32_bfd_merge_private_bfd_data v850_elf_merge_private_bfd_data diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 5813878..cf53c8c 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,7 @@ +2013-04-03 Nick Clifton <nickc@redhat.com> + + * v850.h (V850_INVERSE_PCREL): Define. + 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com> PR binutils/15068 diff --git a/include/opcode/v850.h b/include/opcode/v850.h index 31cb69e..02ef3d4 100644 --- a/include/opcode/v850.h +++ b/include/opcode/v850.h @@ -232,6 +232,9 @@ extern const struct v850_operand v850_operands[]; /* This operand is a prefetch oparation. */ #define V850_OPERAND_PREFOP 0x800000 +/* A PC-relative displacement where a positive value indicates a backwards displacement. */ +#define V850_INVERSE_PCREL 0x1000000 + extern int v850_msg_is_out_of_range (const char *); #endif /* V850_H */ diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 39c256e..dfd3969 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,25 @@ +2013-04-03 Nick Clifton <nickc@redhat.com> + + * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the + destination address by subtracting the operand from the current + address. + * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store + a positive value in the insn. + (extract_u16_loop): Do not negate the returned value. + (D16_LOOP): Add V850_INVERSE_PCREL flag. + + (ceilf.sw): Remove duplicate entry. + (cvtf.hs): New entry. + (cvtf.sh): Likewise. + (fmaf.s): Likewise. + (fmsf.s): Likewise. + (fnmaf.s): Likewise. + (fnmsf.s): Likewise. + (maddf.s): Restrict to E3V5 architectures. + (msubf.s): Likewise. + (nmaddf.s): Likewise. + (nmsubf.s): Likewise. + 2013-03-27 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (get_sib): Add the sizeflag argument. Properly diff --git a/opcodes/v850-dis.c b/opcodes/v850-dis.c index 648846b..bf16851 100644 --- a/opcodes/v850-dis.c +++ b/opcodes/v850-dis.c @@ -94,6 +94,9 @@ print_value (int flags, if (flags & V850_PCREL) { bfd_vma addr = value + memaddr; + + if (flags & V850_INVERSE_PCREL) + addr = memaddr - value; info->print_address_func (addr, info); } else if (flags & V850_OPERAND_DISP) diff --git a/opcodes/v850-opc.c b/opcodes/v850-opc.c index 0b25f3b..bfbc280 100644 --- a/opcodes/v850-opc.c +++ b/opcodes/v850-opc.c @@ -301,7 +301,9 @@ extract_d9 (unsigned long insn, int * invalid) static unsigned long insert_u16_loop (unsigned long insn, long value, const char ** errmsg) { - if (value < -0xffff || value > 0) + /* Loop displacement is encoded as a positive value, + even though the instruction branches backwards. */ + if (value < 0 || value > 0xffff) { if ((value % 2) != 0) * errmsg = branch_out_of_range_and_odd_offset; @@ -311,14 +313,13 @@ insert_u16_loop (unsigned long insn, long value, const char ** errmsg) else if ((value % 2) != 0) * errmsg = branch_to_odd_offset; - return insn | ((-value & 0xfffe) << 16); + return insn | ((value & 0xfffe) << 16); } static unsigned long extract_u16_loop (unsigned long insn, int * invalid) { long ret = (insn >> 16) & 0xfffe; - ret = -ret; if (invalid != 0) *invalid = 0; @@ -1211,7 +1212,7 @@ const struct v850_operand v850_operands[] = /* The unsigned DISP16 field in a format 7 insn. */ #define D16_LOOP (D16_15 + 1) - { 16, 0, insert_u16_loop, extract_u16_loop, V850_OPERAND_RELAX | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_16_PCREL }, + { 16, 0, insert_u16_loop, extract_u16_loop, V850_OPERAND_RELAX | V850_OPERAND_DISP | V850_PCREL | V850_INVERSE_PCREL, BFD_RELOC_V850_16_PCREL }, /* The DISP17 field in a format 7 insn. */ #define D17_16 (D16_LOOP + 1) @@ -1814,7 +1815,6 @@ const struct v850_opcode v850_opcodes[] = { "ceilf.sul", two (0x07f2, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, { "ceilf.suw", two (0x07f2, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, { "ceilf.sw", two (0x07e2, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, -{ "ceilf.sw", two (0x07e2, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, { "cmovf.d", two (0x07e0, 0x0410), two (0x0fe1, 0x0ff1), {FFF, R1_EVEN, R2_EVEN, R3_EVEN_NOTR0}, 0, PROCESSOR_V850E2V3_UP }, /* Default value for FFF is 0(not defined in spec). */ { "cmovf.d", two (0x07e0, 0x0410), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN_NOTR0}, 0, PROCESSOR_V850E2V3_UP }, @@ -1830,10 +1830,12 @@ const struct v850_opcode v850_opcodes[] = { "cvtf.dul", two (0x07f4, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, { "cvtf.duw", two (0x07f4, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, { "cvtf.dw", two (0x07e4, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, +{ "cvtf.hs", two (0x07e2, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E3V5_UP }, { "cvtf.ld", two (0x07e1, 0x0452), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, { "cvtf.ls", two (0x07e1, 0x0442), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, { "cvtf.sd", two (0x07e2, 0x0452), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, { "cvtf.sl", two (0x07e4, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, +{ "cvtf.sh", two (0x07e3, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E3V5_UP }, { "cvtf.sul", two (0x07f4, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, { "cvtf.suw", two (0x07f4, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, { "cvtf.sw", two (0x07e4, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, @@ -1853,18 +1855,22 @@ const struct v850_opcode v850_opcodes[] = { "floorf.sul", two (0x07f3, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, { "floorf.suw", two (0x07f3, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, { "floorf.sw", two (0x07e3, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, -{ "maddf.s", two (0x07e0, 0x0500), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3_UP }, +{ "maddf.s", two (0x07e0, 0x0500), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 }, +{ "fmaf.s", two (0x07e0, 0x04e0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP }, { "maxf.d", two (0x07e0, 0x0478), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, { "maxf.s", two (0x07e0, 0x0468), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP }, { "minf.d", two (0x07e0, 0x047a), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, { "minf.s", two (0x07e0, 0x046a), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP }, -{ "msubf.s", two (0x07e0, 0x0520), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3_UP }, +{ "msubf.s", two (0x07e0, 0x0520), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 }, +{ "fmsf.s", two (0x07e0, 0x04e2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP }, { "mulf.d", two (0x07e0, 0x0474), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, { "mulf.s", two (0x07e0, 0x0464), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP }, { "negf.d", two (0x07e1, 0x0458), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, { "negf.s", two (0x07e1, 0x0448), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, -{ "nmaddf.s", two (0x07e0, 0x0540), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3_UP }, -{ "nmsubf.s", two (0x07e0, 0x0560), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3_UP }, +{ "nmaddf.s", two (0x07e0, 0x0540), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 }, +{ "fnmaf.s", two (0x07e0, 0x04e4), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP }, +{ "nmsubf.s", two (0x07e0, 0x0560), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 }, +{ "fnmsf.s", two (0x07e0, 0x04e6), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP }, { "recipf.d", two (0x07e1, 0x045e), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, { "recipf.s", two (0x07e1, 0x044e), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, |