diff options
| -rw-r--r-- | gas/testsuite/gas/riscv/vector-insns.d | 6 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/vector-insns.s | 7 | ||||
| -rw-r--r-- | include/opcode/riscv.h | 2 | ||||
| -rw-r--r-- | opcodes/riscv-dis.c | 2 |
4 files changed, 14 insertions, 3 deletions
diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d index 6325c74..71764aa 100644 --- a/gas/testsuite/gas/riscv/vector-insns.d +++ b/gas/testsuite/gas/riscv/vector-insns.d @@ -24,6 +24,12 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+c4a5f557[ ]+vsetivli[ ]+a0,11,e16,m4,ta,mu [ ]+[0-9a-f]+:[ ]+c165f557[ ]+vsetivli[ ]+a0,11,e32,mf4,tu,mu [ ]+[0-9a-f]+:[ ]+c9d5f557[ ]+vsetivli[ ]+a0,11,e64,mf8,tu,ma +[ ]+[0-9a-f]+:[ ]+7005f557[ ]+vsetvli[ ]+a0,a1,1792 +[ ]+[0-9a-f]+:[ ]+4005f557[ ]+vsetvli[ ]+a0,a1,1024 +[ ]+[0-9a-f]+:[ ]+3005f557[ ]+vsetvli[ ]+a0,a1,768 +[ ]+[0-9a-f]+:[ ]+1005f557[ ]+vsetvli[ ]+a0,a1,256 +[ ]+[0-9a-f]+:[ ]+f005f557[ ]+vsetivli[ ]+a0,11,768 +[ ]+[0-9a-f]+:[ ]+d005f557[ ]+vsetivli[ ]+a0,11,256 [ ]+[0-9a-f]+:[ ]+02b50207[ ]+vlm.v[ ]+v4,\(a0\) [ ]+[0-9a-f]+:[ ]+02b50207[ ]+vlm.v[ ]+v4,\(a0\) [ ]+[0-9a-f]+:[ ]+02b50207[ ]+vlm.v[ ]+v4,\(a0\) diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s index 8370264..a4b98d8 100644 --- a/gas/testsuite/gas/riscv/vector-insns.s +++ b/gas/testsuite/gas/riscv/vector-insns.s @@ -16,6 +16,13 @@ vsetivli a0, 0xb, e32, mf4, mu vsetivli a0, 0xb, e64, mf8, tu, ma + vsetvli a0, a1, 0x700 + vsetvli a0, a1, 0x400 + vsetvli a0, a1, 0x300 + vsetvli a0, a1, 0x100 + vsetivli a0, 0xb, 0x300 + vsetivli a0, 0xb, 0x100 + vlm.v v4, (a0) vlm.v v4, 0(a0) vle1.v v4, (a0) # Alias of vlm.v diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 8cb4fd2..1488997 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -306,8 +306,6 @@ static const char * const riscv_pred_succ[16] = #define OP_SH_VTA 6 #define OP_MASK_VMA 0x1 #define OP_SH_VMA 7 -#define OP_MASK_VTYPE_RES 0x1 -#define OP_SH_VTYPE_RES 10 #define OP_MASK_VWD 0x1 #define OP_SH_VWD 26 diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index a3c8506..d646dd5 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -328,7 +328,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info unsigned int imm_vsew = EXTRACT_OPERAND (VSEW, imm); unsigned int imm_vta = EXTRACT_OPERAND (VTA, imm); unsigned int imm_vma = EXTRACT_OPERAND (VMA, imm); - unsigned int imm_vtype_res = EXTRACT_OPERAND (VTYPE_RES, imm); + unsigned int imm_vtype_res = (imm >> 8); if (imm_vsew < ARRAY_SIZE (riscv_vsew) && imm_vlmul < ARRAY_SIZE (riscv_vlmul) |