diff options
| -rw-r--r-- | gas/ChangeLog | 5 | ||||
| -rw-r--r-- | gas/config/tc-riscv.c | 10 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 4 | ||||
| -rw-r--r-- | opcodes/riscv-opc.c | 2 |
4 files changed, 20 insertions, 1 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 04c922b..a6c0e6c 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2018-01-17 Jim Wilson <jimw@sifive.com> + + * config/tc-riscv.c (validate_riscv_insn) <'z'>: New. + (riscv_ip) <'z'>: New. + 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com> * config/tc-i386.c (cpu_arch): Delete .cet. Add .ibt, .shstk. diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index f60bea1..a84240d 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -570,6 +570,7 @@ validate_riscv_insn (const struct riscv_opcode *opc) case 'p': used_bits |= ENCODE_SBTYPE_IMM (-1U); break; case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break; case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break; + case 'z': break; case '[': break; case ']': break; case '0': break; @@ -1712,6 +1713,15 @@ jump: *imm_reloc = BFD_RELOC_RISCV_CALL; continue; + case 'z': + if (my_getSmallExpression (imm_expr, imm_reloc, s, p) + || imm_expr->X_op != O_constant + || imm_expr->X_add_number != 0) + break; + s = expr_end; + imm_expr->X_op = O_absent; + continue; + default: as_fatal (_("internal error: bad argument type %c"), *args); } diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 8e0baff..35a16f5 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +2018-01-17 Jim Wilson <jimw@sifive.com> + + * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0. + 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com> * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index a4e4b26..4aeb55a 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -232,7 +232,7 @@ const struct riscv_opcode riscv_opcodes[] = {"bne", "I", "s,t,p", MATCH_BNE, MASK_BNE, match_opcode, 0 }, {"addi", "C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS }, {"addi", "C", "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS }, -{"addi", "C", "d,CU,0", MATCH_C_NOP, MASK_C_ADDI | MASK_RVC_IMM, match_c_nop, INSN_ALIAS }, +{"addi", "C", "d,CU,z", MATCH_C_NOP, MASK_C_ADDI | MASK_RVC_IMM, match_c_nop, INSN_ALIAS }, {"addi", "C", "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS }, {"addi", "I", "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, 0 }, {"add", "C", "d,CU,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS }, |