diff options
| -rw-r--r-- | gas/config/tc-aarch64.c | 127 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sme-f64.d | 31 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sme-f64.s | 32 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sme-i64.d | 117 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sme-i64.s | 135 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sme-illegal.d | 3 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sme-illegal.l | 95 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sme-illegal.s | 117 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sme.d | 93 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sme.s | 123 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 4 | ||||
| -rw-r--r-- | opcodes/aarch64-asm-2.c | 7 | ||||
| -rw-r--r-- | opcodes/aarch64-dis-2.c | 573 | ||||
| -rw-r--r-- | opcodes/aarch64-opc-2.c | 3 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.c | 11 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.h | 3 | ||||
| -rw-r--r-- | opcodes/aarch64-tbl.h | 83 |
17 files changed, 1423 insertions, 134 deletions
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index b592e80..7c94e9b 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -278,6 +278,7 @@ struct reloc_entry BASIC_REG_TYPE(VN) /* v[0-31] */ \ BASIC_REG_TYPE(ZN) /* z[0-31] */ \ BASIC_REG_TYPE(PN) /* p[0-15] */ \ + BASIC_REG_TYPE(ZA) /* za[0-15] */ \ /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \ MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \ /* Typecheck: same, plus SVE registers. */ \ @@ -4164,6 +4165,117 @@ parse_bti_operand (char **str, return 0; } +/* Parse STR for reg of REG_TYPE and following '.' and QUALIFIER. + Function returns REG_ENTRY struct and QUALIFIER [bhsdq] or NULL + on failure. Format: + + REG_TYPE.QUALIFIER + + Side effect: Update STR with current parse position of success. +*/ + +static const reg_entry * +parse_reg_with_qual (char **str, aarch64_reg_type reg_type, + aarch64_opnd_qualifier_t *qualifier) +{ + char *q; + + reg_entry *reg = parse_reg (str); + if (reg != NULL && reg->type == reg_type) + { + if (!skip_past_char (str, '.')) + { + set_syntax_error (_("missing ZA tile element size separator")); + return NULL; + } + + q = *str; + switch (TOLOWER (*q)) + { + case 'b': + *qualifier = AARCH64_OPND_QLF_S_B; + break; + case 'h': + *qualifier = AARCH64_OPND_QLF_S_H; + break; + case 's': + *qualifier = AARCH64_OPND_QLF_S_S; + break; + case 'd': + *qualifier = AARCH64_OPND_QLF_S_D; + break; + case 'q': + *qualifier = AARCH64_OPND_QLF_S_Q; + break; + default: + return NULL; + } + q++; + + *str = q; + return reg; + } + + return NULL; +} + +/* Parse SME ZA tile encoded in <ZAda> assembler symbol. + Function return tile QUALIFIER on success. + + Tiles are in example format: za[0-9]\.[bhsd] + + Function returns <ZAda> register number or PARSE_FAIL. +*/ +static int +parse_sme_zada_operand (char **str, aarch64_opnd_qualifier_t *qualifier) +{ + int regno; + const reg_entry *reg = parse_reg_with_qual (str, REG_TYPE_ZA, qualifier); + + if (reg == NULL) + return PARSE_FAIL; + regno = reg->number; + + switch (*qualifier) + { + case AARCH64_OPND_QLF_S_B: + if (regno != 0x00) + { + set_syntax_error (_("invalid ZA tile register number, expected za0")); + return PARSE_FAIL; + } + break; + case AARCH64_OPND_QLF_S_H: + if (regno > 0x01) + { + set_syntax_error (_("invalid ZA tile register number, expected za0-za1")); + return PARSE_FAIL; + } + break; + case AARCH64_OPND_QLF_S_S: + if (regno > 0x03) + { + /* For the 32-bit variant: is the name of the ZA tile ZA0-ZA3. */ + set_syntax_error (_("invalid ZA tile register number, expected za0-za3")); + return PARSE_FAIL; + } + break; + case AARCH64_OPND_QLF_S_D: + if (regno > 0x07) + { + /* For the 64-bit variant: is the name of the ZA tile ZA0-ZA7 */ + set_syntax_error (_("invalid ZA tile register number, expected za0-za7")); + return PARSE_FAIL; + } + break; + default: + set_syntax_error (_("invalid ZA tile element size, allowed b, h, s and d")); + return PARSE_FAIL; + } + + return regno; +} + /* Parse a system register or a PSTATE field name for an MSR/MRS instruction. Returns the encoding for the option, or PARSE_FAIL. @@ -5801,6 +5913,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SVE_Pm: case AARCH64_OPND_SVE_Pn: case AARCH64_OPND_SVE_Pt: + case AARCH64_OPND_SME_Pm: reg_type = REG_TYPE_PN; goto vector_reg; @@ -6867,6 +6980,15 @@ parse_operands (char *str, const aarch64_opcode *opcode) goto failure; break; + case AARCH64_OPND_SME_ZAda_2b: + case AARCH64_OPND_SME_ZAda_3b: + val = parse_sme_zada_operand (&str, &qualifier); + if (val == PARSE_FAIL) + goto failure; + info->reg.regno = val; + info->qualifier = qualifier; + break; + default: as_fatal (_("unhandled operand code %d"), operands[i]); } @@ -7463,7 +7585,10 @@ static const reg_entry reg_names[] = { REGSET (z, ZN), REGSET (Z, ZN), /* SVE predicate registers. */ - REGSET16 (p, PN), REGSET16 (P, PN) + REGSET16 (p, PN), REGSET16 (P, PN), + + /* SME ZA tile registers. */ + REGSET16 (za, ZA), REGSET16 (ZA, ZA) }; #undef REGDEF diff --git a/gas/testsuite/gas/aarch64/sme-f64.d b/gas/testsuite/gas/aarch64/sme-f64.d new file mode 100644 index 0000000..7fdd19f --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-f64.d @@ -0,0 +1,31 @@ +#name: SME F64 extension +#as: -march=armv8-a+sme-f64 +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: + 0: 80c82020 fmopa za0.d, p0/m, p1/m, z1.d, z8.d + 4: 80c76841 fmopa za1.d, p2/m, p3/m, z2.d, z7.d + 8: 80c6b062 fmopa za2.d, p4/m, p5/m, z3.d, z6.d + c: 80c5f883 fmopa za3.d, p6/m, p7/m, z4.d, z5.d + 10: 80c404a4 fmopa za4.d, p1/m, p0/m, z5.d, z4.d + 14: 80c34cc5 fmopa za5.d, p3/m, p2/m, z6.d, z3.d + 18: 80c294e6 fmopa za6.d, p5/m, p4/m, z7.d, z2.d + 1c: 80c1dd07 fmopa za7.d, p7/m, p6/m, z8.d, z1.d + 20: 80c41ca4 fmopa za4.d, p7/m, p0/m, z5.d, z4.d + 24: 80c338c5 fmopa za5.d, p6/m, p1/m, z6.d, z3.d + 28: 80c254e6 fmopa za6.d, p5/m, p2/m, z7.d, z2.d + 2c: 80c17107 fmopa za7.d, p4/m, p3/m, z8.d, z1.d + 30: 80c82030 fmops za0.d, p0/m, p1/m, z1.d, z8.d + 34: 80c76851 fmops za1.d, p2/m, p3/m, z2.d, z7.d + 38: 80c6b072 fmops za2.d, p4/m, p5/m, z3.d, z6.d + 3c: 80c5f893 fmops za3.d, p6/m, p7/m, z4.d, z5.d + 40: 80c404b4 fmops za4.d, p1/m, p0/m, z5.d, z4.d + 44: 80c34cd5 fmops za5.d, p3/m, p2/m, z6.d, z3.d + 48: 80c294f6 fmops za6.d, p5/m, p4/m, z7.d, z2.d + 4c: 80c1dd17 fmops za7.d, p7/m, p6/m, z8.d, z1.d + 50: 81a1f803 fmopa za3.s, p6/m, p7/m, z0.h, z1.h + 54: 8081f813 fmops za3.s, p6/m, p7/m, z0.s, z1.s diff --git a/gas/testsuite/gas/aarch64/sme-f64.s b/gas/testsuite/gas/aarch64/sme-f64.s new file mode 100644 index 0000000..03a136b --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-f64.s @@ -0,0 +1,32 @@ +/* Scalable Matrix Extension (SME F64). */ + +/* FMOPA (non-widening), double-precision. */ +fmopa za0.d, p0/m, p1/m, z1.d, z8.d +fmopa za1.d, p2/m, p3/m, z2.d, z7.d +fmopa za2.d, p4/m, p5/m, z3.d, z6.d +fmopa za3.d, p6/m, p7/m, z4.d, z5.d +fmopa za4.d, p1/m, p0/m, z5.d, z4.d +fmopa za5.d, p3/m, p2/m, z6.d, z3.d +fmopa za6.d, p5/m, p4/m, z7.d, z2.d +fmopa za7.d, p7/m, p6/m, z8.d, z1.d +fmopa za4.d, p7/m, p0/m, z5.d, z4.d +fmopa za5.d, p6/m, p1/m, z6.d, z3.d +fmopa za6.d, p5/m, p2/m, z7.d, z2.d +fmopa za7.d, p4/m, p3/m, z8.d, z1.d + +/* FMOPS (non-widening), double-precision. */ +fmops za0.d, p0/m, p1/m, z1.d, z8.d +fmops za1.d, p2/m, p3/m, z2.d, z7.d +fmops za2.d, p4/m, p5/m, z3.d, z6.d +fmops za3.d, p6/m, p7/m, z4.d, z5.d +fmops za4.d, p1/m, p0/m, z5.d, z4.d +fmops za5.d, p3/m, p2/m, z6.d, z3.d +fmops za6.d, p5/m, p4/m, z7.d, z2.d +fmops za7.d, p7/m, p6/m, z8.d, z1.d + +/* Register aliases. */ +foo .req za3 +bar .req z0 + +fmopa foo.s, p6/m, p7/m, bar.h, z1.h +fmops foo.s, p6/m, p7/m, bar.s, z1.s diff --git a/gas/testsuite/gas/aarch64/sme-i64.d b/gas/testsuite/gas/aarch64/sme-i64.d new file mode 100644 index 0000000..ee5880e --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-i64.d @@ -0,0 +1,117 @@ +#name: SME I64 extension +#as: -march=armv8-a+sme-i64 +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: + 0: c0d02020 addha za0.d, p0/m, p1/m, z1.d + 4: c0d06841 addha za1.d, p2/m, p3/m, z2.d + 8: c0d0b062 addha za2.d, p4/m, p5/m, z3.d + c: c0d0f883 addha za3.d, p6/m, p7/m, z4.d + 10: c0d004a4 addha za4.d, p1/m, p0/m, z5.d + 14: c0d04cc5 addha za5.d, p3/m, p2/m, z6.d + 18: c0d094e6 addha za6.d, p5/m, p4/m, z7.d + 1c: c0d0dd07 addha za7.d, p7/m, p6/m, z8.d + 20: c0d01ca4 addha za4.d, p7/m, p0/m, z5.d + 24: c0d038c5 addha za5.d, p6/m, p1/m, z6.d + 28: c0d054e6 addha za6.d, p5/m, p2/m, z7.d + 2c: c0d07107 addha za7.d, p4/m, p3/m, z8.d + 30: c0d12020 addva za0.d, p0/m, p1/m, z1.d + 34: c0d16841 addva za1.d, p2/m, p3/m, z2.d + 38: c0d1b062 addva za2.d, p4/m, p5/m, z3.d + 3c: c0d1f883 addva za3.d, p6/m, p7/m, z4.d + 40: c0d104a4 addva za4.d, p1/m, p0/m, z5.d + 44: c0d14cc5 addva za5.d, p3/m, p2/m, z6.d + 48: c0d194e6 addva za6.d, p5/m, p4/m, z7.d + 4c: c0d1dd07 addva za7.d, p7/m, p6/m, z8.d + 50: c0d11ca4 addva za4.d, p7/m, p0/m, z5.d + 54: c0d138c5 addva za5.d, p6/m, p1/m, z6.d + 58: c0d154e6 addva za6.d, p5/m, p2/m, z7.d + 5c: c0d17107 addva za7.d, p4/m, p3/m, z8.d + 60: a0c82020 smopa za0.d, p0/m, p1/m, z1.h, z8.h + 64: a0c76841 smopa za1.d, p2/m, p3/m, z2.h, z7.h + 68: a0c6b062 smopa za2.d, p4/m, p5/m, z3.h, z6.h + 6c: a0c5f883 smopa za3.d, p6/m, p7/m, z4.h, z5.h + 70: a0c404a4 smopa za4.d, p1/m, p0/m, z5.h, z4.h + 74: a0c34cc5 smopa za5.d, p3/m, p2/m, z6.h, z3.h + 78: a0c294e6 smopa za6.d, p5/m, p4/m, z7.h, z2.h + 7c: a0c1dd07 smopa za7.d, p7/m, p6/m, z8.h, z1.h + 80: a0c82030 smops za0.d, p0/m, p1/m, z1.h, z8.h + 84: a0c76851 smops za1.d, p2/m, p3/m, z2.h, z7.h + 88: a0c6b072 smops za2.d, p4/m, p5/m, z3.h, z6.h + 8c: a0c5f893 smops za3.d, p6/m, p7/m, z4.h, z5.h + 90: a0c404b4 smops za4.d, p1/m, p0/m, z5.h, z4.h + 94: a0c34cd5 smops za5.d, p3/m, p2/m, z6.h, z3.h + 98: a0c294f6 smops za6.d, p5/m, p4/m, z7.h, z2.h + 9c: a0c1dd17 smops za7.d, p7/m, p6/m, z8.h, z1.h + a0: a0c41cb4 smops za4.d, p7/m, p0/m, z5.h, z4.h + a4: a0c338d5 smops za5.d, p6/m, p1/m, z6.h, z3.h + a8: a0c254f6 smops za6.d, p5/m, p2/m, z7.h, z2.h + ac: a0c17117 smops za7.d, p4/m, p3/m, z8.h, z1.h + b0: a0e82020 sumopa za0.d, p0/m, p1/m, z1.h, z8.h + b4: a0e76841 sumopa za1.d, p2/m, p3/m, z2.h, z7.h + b8: a0e6b062 sumopa za2.d, p4/m, p5/m, z3.h, z6.h + bc: a0e5f883 sumopa za3.d, p6/m, p7/m, z4.h, z5.h + c0: a0e404a4 sumopa za4.d, p1/m, p0/m, z5.h, z4.h + c4: a0e34cc5 sumopa za5.d, p3/m, p2/m, z6.h, z3.h + c8: a0e294e6 sumopa za6.d, p5/m, p4/m, z7.h, z2.h + cc: a0e1dd07 sumopa za7.d, p7/m, p6/m, z8.h, z1.h + d0: a0e82030 sumops za0.d, p0/m, p1/m, z1.h, z8.h + d4: a0e76851 sumops za1.d, p2/m, p3/m, z2.h, z7.h + d8: a0e6b072 sumops za2.d, p4/m, p5/m, z3.h, z6.h + dc: a0e5f893 sumops za3.d, p6/m, p7/m, z4.h, z5.h + e0: a0e404b4 sumops za4.d, p1/m, p0/m, z5.h, z4.h + e4: a0e34cd5 sumops za5.d, p3/m, p2/m, z6.h, z3.h + e8: a0e294f6 sumops za6.d, p5/m, p4/m, z7.h, z2.h + ec: a0e1dd17 sumops za7.d, p7/m, p6/m, z8.h, z1.h + f0: a1e82020 umopa za0.d, p0/m, p1/m, z1.h, z8.h + f4: a1e76841 umopa za1.d, p2/m, p3/m, z2.h, z7.h + f8: a1e6b062 umopa za2.d, p4/m, p5/m, z3.h, z6.h + fc: a1e5f883 umopa za3.d, p6/m, p7/m, z4.h, z5.h + 100: a1e404a4 umopa za4.d, p1/m, p0/m, z5.h, z4.h + 104: a1e34cc5 umopa za5.d, p3/m, p2/m, z6.h, z3.h + 108: a1e294e6 umopa za6.d, p5/m, p4/m, z7.h, z2.h + 10c: a1e1dd07 umopa za7.d, p7/m, p6/m, z8.h, z1.h + 110: a1e82030 umops za0.d, p0/m, p1/m, z1.h, z8.h + 114: a1e76851 umops za1.d, p2/m, p3/m, z2.h, z7.h + 118: a1e6b072 umops za2.d, p4/m, p5/m, z3.h, z6.h + 11c: a1e5f893 umops za3.d, p6/m, p7/m, z4.h, z5.h + 120: a1e404b4 umops za4.d, p1/m, p0/m, z5.h, z4.h + 124: a1e34cd5 umops za5.d, p3/m, p2/m, z6.h, z3.h + 128: a1e294f6 umops za6.d, p5/m, p4/m, z7.h, z2.h + 12c: a1e1dd17 umops za7.d, p7/m, p6/m, z8.h, z1.h + 130: a1c82020 usmopa za0.d, p0/m, p1/m, z1.h, z8.h + 134: a1c76841 usmopa za1.d, p2/m, p3/m, z2.h, z7.h + 138: a1c6b062 usmopa za2.d, p4/m, p5/m, z3.h, z6.h + 13c: a1c5f883 usmopa za3.d, p6/m, p7/m, z4.h, z5.h + 140: a1c404a4 usmopa za4.d, p1/m, p0/m, z5.h, z4.h + 144: a1c34cc5 usmopa za5.d, p3/m, p2/m, z6.h, z3.h + 148: a1c294e6 usmopa za6.d, p5/m, p4/m, z7.h, z2.h + 14c: a1c1dd07 usmopa za7.d, p7/m, p6/m, z8.h, z1.h + 150: a1c82030 usmops za0.d, p0/m, p1/m, z1.h, z8.h + 154: a1c76851 usmops za1.d, p2/m, p3/m, z2.h, z7.h + 158: a1c6b072 usmops za2.d, p4/m, p5/m, z3.h, z6.h + 15c: a1c5f893 usmops za3.d, p6/m, p7/m, z4.h, z5.h + 160: a1c404b4 usmops za4.d, p1/m, p0/m, z5.h, z4.h + 164: a1c34cd5 usmops za5.d, p3/m, p2/m, z6.h, z3.h + 168: a1c294f6 usmops za6.d, p5/m, p4/m, z7.h, z2.h + 16c: a1c1dd17 usmops za7.d, p7/m, p6/m, z8.h, z1.h + 170: a1c41cb4 usmops za4.d, p7/m, p0/m, z5.h, z4.h + 174: a1c338d5 usmops za5.d, p6/m, p1/m, z6.h, z3.h + 178: a1c254f6 usmops za6.d, p5/m, p2/m, z7.h, z2.h + 17c: a1c17117 usmops za7.d, p4/m, p3/m, z8.h, z1.h + 180: c0d02020 addha za0.d, p0/m, p1/m, z1.d + 184: c0d17107 addva za7.d, p4/m, p3/m, z8.d + 188: 8181f883 bfmopa za3.s, p6/m, p7/m, z4.h, z1.h + 18c: 8181f893 bfmops za3.s, p6/m, p7/m, z4.h, z1.h + 190: a0c1dd07 smopa za7.d, p7/m, p6/m, z8.h, z1.h + 194: a0c17117 smops za7.d, p4/m, p3/m, z8.h, z1.h + 198: a0e1dd07 sumopa za7.d, p7/m, p6/m, z8.h, z1.h + 19c: a0e1dd17 sumops za7.d, p7/m, p6/m, z8.h, z1.h + 1a0: a1a1f883 umopa za3.s, p6/m, p7/m, z4.b, z1.b + 1a4: a1a1f893 umops za3.s, p6/m, p7/m, z4.b, z1.b + 1a8: a1817083 usmopa za3.s, p4/m, p3/m, z4.b, z1.b + 1ac: a181f893 usmops za3.s, p6/m, p7/m, z4.b, z1.b diff --git a/gas/testsuite/gas/aarch64/sme-i64.s b/gas/testsuite/gas/aarch64/sme-i64.s new file mode 100644 index 0000000..1f8ba84 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-i64.s @@ -0,0 +1,135 @@ +/* Scalable Matrix Extension (SME I64). */ + +/* ADDHA 64-bit variant. */ +addha za0.d, p0/m, p1/m, z1.d +addha za1.d, p2/m, p3/m, z2.d +addha za2.d, p4/m, p5/m, z3.d +addha za3.d, p6/m, p7/m, z4.d +addha za4.d, p1/m, p0/m, z5.d +addha za5.d, p3/m, p2/m, z6.d +addha za6.d, p5/m, p4/m, z7.d +addha za7.d, p7/m, p6/m, z8.d +addha za4.d, p7/m, p0/m, z5.d +addha za5.d, p6/m, p1/m, z6.d +addha za6.d, p5/m, p2/m, z7.d +addha za7.d, p4/m, p3/m, z8.d + +/* ADDVA 64-bit variant. */ +addva za0.d, p0/m, p1/m, z1.d +addva za1.d, p2/m, p3/m, z2.d +addva za2.d, p4/m, p5/m, z3.d +addva za3.d, p6/m, p7/m, z4.d +addva za4.d, p1/m, p0/m, z5.d +addva za5.d, p3/m, p2/m, z6.d +addva za6.d, p5/m, p4/m, z7.d +addva za7.d, p7/m, p6/m, z8.d +addva za4.d, p7/m, p0/m, z5.d +addva za5.d, p6/m, p1/m, z6.d +addva za6.d, p5/m, p2/m, z7.d +addva za7.d, p4/m, p3/m, z8.d + +/* SMOPA 64-bit variant. */ +smopa za0.d, p0/m, p1/m, z1.h, z8.h +smopa za1.d, p2/m, p3/m, z2.h, z7.h +smopa za2.d, p4/m, p5/m, z3.h, z6.h +smopa za3.d, p6/m, p7/m, z4.h, z5.h +smopa za4.d, p1/m, p0/m, z5.h, z4.h +smopa za5.d, p3/m, p2/m, z6.h, z3.h +smopa za6.d, p5/m, p4/m, z7.h, z2.h +smopa za7.d, p7/m, p6/m, z8.h, z1.h + +/* SMOPS 64-bit variant. */ +smops za0.d, p0/m, p1/m, z1.h, z8.h +smops za1.d, p2/m, p3/m, z2.h, z7.h +smops za2.d, p4/m, p5/m, z3.h, z6.h +smops za3.d, p6/m, p7/m, z4.h, z5.h +smops za4.d, p1/m, p0/m, z5.h, z4.h +smops za5.d, p3/m, p2/m, z6.h, z3.h +smops za6.d, p5/m, p4/m, z7.h, z2.h +smops za7.d, p7/m, p6/m, z8.h, z1.h +smops za4.d, p7/m, p0/m, z5.h, z4.h +smops za5.d, p6/m, p1/m, z6.h, z3.h +smops za6.d, p5/m, p2/m, z7.h, z2.h +smops za7.d, p4/m, p3/m, z8.h, z1.h + +/* SUMOPA 64-bit variant. */ +sumopa za0.d, p0/m, p1/m, z1.h, z8.h +sumopa za1.d, p2/m, p3/m, z2.h, z7.h +sumopa za2.d, p4/m, p5/m, z3.h, z6.h +sumopa za3.d, p6/m, p7/m, z4.h, z5.h +sumopa za4.d, p1/m, p0/m, z5.h, z4.h +sumopa za5.d, p3/m, p2/m, z6.h, z3.h +sumopa za6.d, p5/m, p4/m, z7.h, z2.h +sumopa za7.d, p7/m, p6/m, z8.h, z1.h + +/* SUMOPS 64-bit variant. */ +sumops za0.d, p0/m, p1/m, z1.h, z8.h +sumops za1.d, p2/m, p3/m, z2.h, z7.h +sumops za2.d, p4/m, p5/m, z3.h, z6.h +sumops za3.d, p6/m, p7/m, z4.h, z5.h +sumops za4.d, p1/m, p0/m, z5.h, z4.h +sumops za5.d, p3/m, p2/m, z6.h, z3.h +sumops za6.d, p5/m, p4/m, z7.h, z2.h +sumops za7.d, p7/m, p6/m, z8.h, z1.h + +/* UMOPA 64-bit variant. */ +umopa za0.d, p0/m, p1/m, z1.h, z8.h +umopa za1.d, p2/m, p3/m, z2.h, z7.h +umopa za2.d, p4/m, p5/m, z3.h, z6.h +umopa za3.d, p6/m, p7/m, z4.h, z5.h +umopa za4.d, p1/m, p0/m, z5.h, z4.h +umopa za5.d, p3/m, p2/m, z6.h, z3.h +umopa za6.d, p5/m, p4/m, z7.h, z2.h +umopa za7.d, p7/m, p6/m, z8.h, z1.h + +/* UMOPS 64-bit variant. */ +umops za0.d, p0/m, p1/m, z1.h, z8.h +umops za1.d, p2/m, p3/m, z2.h, z7.h +umops za2.d, p4/m, p5/m, z3.h, z6.h +umops za3.d, p6/m, p7/m, z4.h, z5.h +umops za4.d, p1/m, p0/m, z5.h, z4.h +umops za5.d, p3/m, p2/m, z6.h, z3.h +umops za6.d, p5/m, p4/m, z7.h, z2.h +umops za7.d, p7/m, p6/m, z8.h, z1.h + +/* USMOPA 64-bit variant. */ +usmopa za0.d, p0/m, p1/m, z1.h, z8.h +usmopa za1.d, p2/m, p3/m, z2.h, z7.h +usmopa za2.d, p4/m, p5/m, z3.h, z6.h +usmopa za3.d, p6/m, p7/m, z4.h, z5.h +usmopa za4.d, p1/m, p0/m, z5.h, z4.h +usmopa za5.d, p3/m, p2/m, z6.h, z3.h +usmopa za6.d, p5/m, p4/m, z7.h, z2.h +usmopa za7.d, p7/m, p6/m, z8.h, z1.h + +/* USMOPS 64-bit variant. */ +usmops za0.d, p0/m, p1/m, z1.h, z8.h +usmops za1.d, p2/m, p3/m, z2.h, z7.h +usmops za2.d, p4/m, p5/m, z3.h, z6.h +usmops za3.d, p6/m, p7/m, z4.h, z5.h +usmops za4.d, p1/m, p0/m, z5.h, z4.h +usmops za5.d, p3/m, p2/m, z6.h, z3.h +usmops za6.d, p5/m, p4/m, z7.h, z2.h +usmops za7.d, p7/m, p6/m, z8.h, z1.h +usmops za4.d, p7/m, p0/m, z5.h, z4.h +usmops za5.d, p6/m, p1/m, z6.h, z3.h +usmops za6.d, p5/m, p2/m, z7.h, z2.h +usmops za7.d, p4/m, p3/m, z8.h, z1.h + +/* Register aliases. */ +foo .req za3 +bar .req za7 +baz .req za0 + +addha baz.d, p0/m, p1/m, z1.d +addva bar.d, p4/m, p3/m, z8.d +bfmopa foo.s, p6/m, p7/m, z4.h, z1.h +bfmops foo.s, p6/m, p7/m, z4.h, z1.h +smopa bar.d, p7/m, p6/m, z8.h, z1.h +smops bar.d, p4/m, p3/m, z8.h, z1.h +sumopa bar.d, p7/m, p6/m, z8.h, z1.h +sumops bar.d, p7/m, p6/m, z8.h, z1.h +umopa foo.s, p6/m, p7/m, z4.b, z1.b +umops foo.s, p6/m, p7/m, z4.b, z1.b +usmopa foo.s, p4/m, p3/m, z4.b, z1.b +usmops foo.s, p6/m, p7/m, z4.b, z1.b diff --git a/gas/testsuite/gas/aarch64/sme-illegal.d b/gas/testsuite/gas/aarch64/sme-illegal.d new file mode 100644 index 0000000..8fb819b --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-illegal.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a+sme+sme-i64+sme-f64 +#source: sme-illegal.s +#error_output: sme-illegal.l diff --git a/gas/testsuite/gas/aarch64/sme-illegal.l b/gas/testsuite/gas/aarch64/sme-illegal.l new file mode 100644 index 0000000..19d22da --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-illegal.l @@ -0,0 +1,95 @@ +[^:]*: Assembler messages: +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `addha za4.s,p0/m,p1/m,z1.s' +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `addha za15.s,p2/m,p3/m,z2.s' +[^:]*:[0-9]+: Error: operand mismatch -- `addha za0.s,p2/m,p3/m,z2.d' +[^:]*:[0-9]+: Info: did you mean this\? +[^:]*:[0-9]+: Info: addha za0.d, p2/m, p3/m, z2.d +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `addha za8.d,p0/m,p1/m,z1.d' +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `addha za15.d,p2/m,p3/m,z2.d' +[^:]*:[0-9]+: Error: operand mismatch -- `addha za0.d,p2/m,p3/m,z2.s' +[^:]*:[0-9]+: Info: did you mean this\? +[^:]*:[0-9]+: Info: addha za0.d, p2/m, p3/m, z2.d +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `addva za4.s,p0/m,p1/m,z1.s' +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `addva za15.s,p2/m,p3/m,z2.s' +[^:]*:[0-9]+: Error: operand mismatch -- `addva za0.s,p2/m,p3/m,z2.d' +[^:]*:[0-9]+: Info: did you mean this\? +[^:]*:[0-9]+: Info: addva za0.d, p2/m, p3/m, z2.d +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `addva za8.d,p0/m,p1/m,z1.d' +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `addva za15.d,p2/m,p3/m,z2.d' +[^:]*:[0-9]+: Error: operand mismatch -- `addva za0.d,p2/m,p3/m,z2.s' +[^:]*:[0-9]+: Info: did you mean this\? +[^:]*:[0-9]+: Info: addva za0.d, p2/m, p3/m, z2.d +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `bfmopa za4.s,p0/m,p1/m,z1.h,z4.h' +[^:]*:[0-9]+: Error: operand mismatch -- `bfmopa za0.s,p2/m,p3/m,z2.s,z3.s' +[^:]*:[0-9]+: Info: did you mean this\? +[^:]*:[0-9]+: Info: bfmopa za0.s, p2/m, p3/m, z2.h, z3.h +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `bfmops za4.s,p0/m,p1/m,z1.h,z4.h' +[^:]*:[0-9]+: Error: operand mismatch -- `bfmops za0.s,p2/m,p3/m,z2.s,z3.s' +[^:]*:[0-9]+: Info: did you mean this\? +[^:]*:[0-9]+: Info: bfmops za0.s, p2/m, p3/m, z2.h, z3.h +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `fmopa za4.s,p0/m,p1/m,z1.s,z4.s' +[^:]*:[0-9]+: Error: operand mismatch -- `fmopa za0.s,p6/m,p7/m,z4.d,z1.d' +[^:]*:[0-9]+: Info: did you mean this\? +[^:]*:[0-9]+: Info: fmopa za0.d, p6/m, p7/m, z4.d, z1.d +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `fmopa za8.d,p0/m,p1/m,z1.d,z8.d' +[^:]*:[0-9]+: Error: operand mismatch -- `fmopa za0.d,p2/m,p3/m,z2.s,z7.s' +[^:]*:[0-9]+: Info: did you mean this\? +[^:]*:[0-9]+: Info: fmopa za0.d, p2/m, p3/m, z2.d, z7.d +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `fmopa za4.s,p0/m,p1/m,z1.h,z4.h' +[^:]*:[0-9]+: Error: operand mismatch -- `fmopa za1.s,p2/m,p3/m,z2.q,z3.q' +[^:]*:[0-9]+: Info: did you mean this\? +[^:]*:[0-9]+: Info: fmopa za1.d, p2/m, p3/m, z2.d, z3.d +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `fmops za4.s,p0/m,p1/m,z1.s,z4.s' +[^:]*:[0-9]+: Error: operand mismatch -- `fmops za1.s,p2/m,p3/m,z2.q,z3.q' +[^:]*:[0-9]+: Info: did you mean this\? +[^:]*:[0-9]+: Info: fmops za1.d, p2/m, p3/m, z2.d, z3.d +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `fmops za8.d,p0/m,p1/m,z1.d,z8.d' +[^:]*:[0-9]+: Error: operand mismatch -- `fmops za0.d,p2/m,p3/m,z2.s,z7.s' +[^:]*:[0-9]+: Info: did you mean this\? +[^:]*:[0-9]+: Info: fmops za0.d, p2/m, p3/m, z2.d, z7.d +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `fmops za8.s,p0/m,p1/m,z1.h,z4.h' +[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `fmops za1.q,p2/m,p3/m,z2.h,z3.h' +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `smopa za4.s,p0/m,p1/m,z1.b,z4.b' +[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `smopa za1.q,p2/m,p3/m,z2.b,z3.b' +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `smopa za8.d,p0/m,p1/m,z1.h,z8.h' +[^:]*:[0-9]+: Error: operand mismatch -- `smopa za1.d,p2/m,p3/m,z2.h,z7.q' +[^:]*:[0-9]+: Info: did you mean this\? +[^:]*:[0-9]+: Info: smopa za1.d, p2/m, p3/m, z2.h, z7.h +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `smops za4.s,p0/m,p1/m,z1.b,z4.b' +[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `smops za1.q,p2/m,p3/m,z2.b,z3.b' +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `smops za8.d,p0/m,p1/m,z1.h,z8.h' +[^:]*:[0-9]+: Error: operand mismatch -- `smops za1.d,p2/m,p3/m,z2.h,z7.q' +[^:]*:[0-9]+: Info: did you mean this\? +[^:]*:[0-9]+: Info: smops za1.d, p2/m, p3/m, z2.h, z7.h +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `sumopa za4.s,p0/m,p1/m,z1.b,z4.b' +[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `sumopa za1.q,p2/m,p3/m,z2.s,z3.s' +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `sumopa za8.d,p0/m,p1/m,z1.h,z8.h' +[^:]*:[0-9]+: Error: operand mismatch -- `sumopa za1.d,p2/m,p3/m,z2.h,z7.q' +[^:]*:[0-9]+: Info: did you mean this\? +[^:]*:[0-9]+: Info: sumopa za1.d, p2/m, p3/m, z2.h, z7.h +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `sumops za4.s,p0/m,p1/m,z1.b,z4.b' +[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `sumops za1.q,p2/m,p3/m,z2.b,z3.b' +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `sumops za8.d,p0/m,p1/m,z1.h,z8.h' +[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `sumops za1.q,p2/m,p3/m,z2.h,z7.h' +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `umopa za4.s,p0/m,p1/m,z1.b,z4.b' +[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `umopa za1.q,p2/m,p3/m,z2.b,z3.b' +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `umopa za8.d,p0/m,p1/m,z1.h,z8.h' +[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `umopa za1.q,p2/m,p3/m,z2.h,z7.h' +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `umops za4.s,p0/m,p1/m,z1.b,z4.b' +[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `umops za1.q,p2/m,p3/m,z2.b,z3.b' +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `umops za8.d,p0/m,p1/m,z1.h,z8.h' +[^:]*:[0-9]+: Error: operand mismatch -- `umops za1.d,p2/m,p3/m,z2.d,z7.d' +[^:]*:[0-9]+: Info: did you mean this\? +[^:]*:[0-9]+: Info: umops za1.d, p2/m, p3/m, z2.h, z7.h +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `usmopa za4.s,p0/m,p1/m,z1.b,z4.b' +[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `usmopa za1.q,p2/m,p3/m,z2.b,z3.b' +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `usmopa za8.d,p0/m,p1/m,z1.h,z8.h' +[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `usmopa za1.q,p2/m,p3/m,z2.h,z7.h' +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `usmops za4.s,p0/m,p1/m,z1.b,z4.b' +[^:]*:[0-9]+: Error: operand mismatch -- `usmops za1.s,p2/m,p3/m,z2.s,z3.b' +[^:]*:[0-9]+: Info: did you mean this\? +[^:]*:[0-9]+: Info: usmops za1.d, p2/m, p3/m, z2.h, z3.h +[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `usmops za8.d,p0/m,p1/m,z1.h,z8.h' +[^:]*:[0-9]+: Error: operand mismatch -- `usmops za1.d,p2/m,p3/m,z2.d,z7.d' +[^:]*:[0-9]+: Info: did you mean this\? +[^:]*:[0-9]+: Info: usmops za1.d, p2/m, p3/m, z2.h, z7.h diff --git a/gas/testsuite/gas/aarch64/sme-illegal.s b/gas/testsuite/gas/aarch64/sme-illegal.s new file mode 100644 index 0000000..d543a64 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-illegal.s @@ -0,0 +1,117 @@ +/* Scalable Matrix Extension (SME). */ + +/* ADDHA 32-bit variant. */ +addha za4.s, p0/m, p1/m, z1.s +addha za15.s, p2/m, p3/m, z2.s +addha za0.s, p2/m, p3/m, z2.d + +/* ADDHA 64-bit variant. */ +addha za8.d, p0/m, p1/m, z1.d +addha za15.d, p2/m, p3/m, z2.d +addha za0.d, p2/m, p3/m, z2.s + +/* ADDVA 32-bit variant. */ +addva za4.s, p0/m, p1/m, z1.s +addva za15.s, p2/m, p3/m, z2.s +addva za0.s, p2/m, p3/m, z2.d + +/* ADDVA 64-bit variant. */ +addva za8.d, p0/m, p1/m, z1.d +addva za15.d, p2/m, p3/m, z2.d +addva za0.d, p2/m, p3/m, z2.s + +/* BFMOPA. */ +bfmopa za4.s, p0/m, p1/m, z1.h, z4.h +bfmopa za0.s, p2/m, p3/m, z2.s, z3.s + +/* BFMOPS. */ +bfmops za4.s, p0/m, p1/m, z1.h, z4.h +bfmops za0.s, p2/m, p3/m, z2.s, z3.s + +/* FMOPA (non-widening), single-precision. */ +fmopa za4.s, p0/m, p1/m, z1.s, z4.s +fmopa za0.s, p6/m, p7/m, z4.d, z1.d + +/* FMOPA (non-widening), double-precision. */ +fmopa za8.d, p0/m, p1/m, z1.d, z8.d +fmopa za0.d, p2/m, p3/m, z2.s, z7.s + +/* FMOPA (widening) */ +fmopa za4.s, p0/m, p1/m, z1.h, z4.h +fmopa za1.s, p2/m, p3/m, z2.q, z3.q + +/* FMOPS (non-widening), single-precision. */ +fmops za4.s, p0/m, p1/m, z1.s, z4.s +fmops za1.s, p2/m, p3/m, z2.q, z3.q + +/* FMOPS (non-widening), double-precision. */ +fmops za8.d, p0/m, p1/m, z1.d, z8.d +fmops za0.d, p2/m, p3/m, z2.s, z7.s + +/* FMOPS (widening) */ +fmops za8.s, p0/m, p1/m, z1.h, z4.h +fmops za1.q, p2/m, p3/m, z2.h, z3.h + +/* SMOPA 32-bit variant. */ +smopa za4.s, p0/m, p1/m, z1.b, z4.b +smopa za1.q, p2/m, p3/m, z2.b, z3.b + +/* SMOPA 64-bit variant. */ +smopa za8.d, p0/m, p1/m, z1.h, z8.h +smopa za1.d, p2/m, p3/m, z2.h, z7.q + +/* SMOPS 32-bit variant. */ +smops za4.s, p0/m, p1/m, z1.b, z4.b +smops za1.q, p2/m, p3/m, z2.b, z3.b + +/* SMOPS 64-bit variant. */ +smops za8.d, p0/m, p1/m, z1.h, z8.h +smops za1.d, p2/m, p3/m, z2.h, z7.q + +/* SUMOPA 32-bit variant. */ +sumopa za4.s, p0/m, p1/m, z1.b, z4.b +sumopa za1.q, p2/m, p3/m, z2.s, z3.s + +/* SUMOPA 64-bit variant. */ +sumopa za8.d, p0/m, p1/m, z1.h, z8.h +sumopa za1.d, p2/m, p3/m, z2.h, z7.q + +/* SUMOPS 32-bit variant. */ +sumops za4.s, p0/m, p1/m, z1.b, z4.b +sumops za1.q, p2/m, p3/m, z2.b, z3.b + +/* SUMOPS 64-bit variant. */ +sumops za8.d, p0/m, p1/m, z1.h, z8.h +sumops za1.q, p2/m, p3/m, z2.h, z7.h + +/* UMOPA 32-bit variant. */ +umopa za4.s, p0/m, p1/m, z1.b, z4.b +umopa za1.q, p2/m, p3/m, z2.b, z3.b + +/* UMOPA 64-bit variant. */ +umopa za8.d, p0/m, p1/m, z1.h, z8.h +umopa za1.q, p2/m, p3/m, z2.h, z7.h + +/* UMOPS 32-bit variant. */ +umops za4.s, p0/m, p1/m, z1.b, z4.b +umops za1.q, p2/m, p3/m, z2.b, z3.b + +/* UMOPS 64-bit variant. */ +umops za8.d, p0/m, p1/m, z1.h, z8.h +umops za1.d, p2/m, p3/m, z2.d, z7.d + +/* USMOPA 32-bit variant. */ +usmopa za4.s, p0/m, p1/m, z1.b, z4.b +usmopa za1.q, p2/m, p3/m, z2.b, z3.b + +/* USMOPA 64-bit variant. */ +usmopa za8.d, p0/m, p1/m, z1.h, z8.h +usmopa za1.q, p2/m, p3/m, z2.h, z7.h + +/* USMOPS 32-bit variant. */ +usmops za4.s, p0/m, p1/m, z1.b, z4.b +usmops za1.s, p2/m, p3/m, z2.s, z3.b + +/* USMOPS 64-bit variant. */ +usmops za8.d, p0/m, p1/m, z1.h, z8.h +usmops za1.d, p2/m, p3/m, z2.d, z7.d diff --git a/gas/testsuite/gas/aarch64/sme.d b/gas/testsuite/gas/aarch64/sme.d new file mode 100644 index 0000000..673ac79 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme.d @@ -0,0 +1,93 @@ +#name: SME extension +#as: -march=armv8-a+sme +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: + 0: c0902020 addha za0.s, p0/m, p1/m, z1.s + 4: c0906841 addha za1.s, p2/m, p3/m, z2.s + 8: c090b062 addha za2.s, p4/m, p5/m, z3.s + c: c090f883 addha za3.s, p6/m, p7/m, z4.s + 10: c0912020 addva za0.s, p0/m, p1/m, z1.s + 14: c0916841 addva za1.s, p2/m, p3/m, z2.s + 18: c091b062 addva za2.s, p4/m, p5/m, z3.s + 1c: c091f883 addva za3.s, p6/m, p7/m, z4.s + 20: 81842020 bfmopa za0.s, p0/m, p1/m, z1.h, z4.h + 24: 81836841 bfmopa za1.s, p2/m, p3/m, z2.h, z3.h + 28: 8182b062 bfmopa za2.s, p4/m, p5/m, z3.h, z2.h + 2c: 8181f883 bfmopa za3.s, p6/m, p7/m, z4.h, z1.h + 30: 81842030 bfmops za0.s, p0/m, p1/m, z1.h, z4.h + 34: 81836851 bfmops za1.s, p2/m, p3/m, z2.h, z3.h + 38: 8182b072 bfmops za2.s, p4/m, p5/m, z3.h, z2.h + 3c: 8181f893 bfmops za3.s, p6/m, p7/m, z4.h, z1.h + 40: 80842020 fmopa za0.s, p0/m, p1/m, z1.s, z4.s + 44: 80836841 fmopa za1.s, p2/m, p3/m, z2.s, z3.s + 48: 8082b062 fmopa za2.s, p4/m, p5/m, z3.s, z2.s + 4c: 8081f883 fmopa za3.s, p6/m, p7/m, z4.s, z1.s + 50: 81a42020 fmopa za0.s, p0/m, p1/m, z1.h, z4.h + 54: 81a36841 fmopa za1.s, p2/m, p3/m, z2.h, z3.h + 58: 81a2b062 fmopa za2.s, p4/m, p5/m, z3.h, z2.h + 5c: 81a1f883 fmopa za3.s, p6/m, p7/m, z4.h, z1.h + 60: 80842030 fmops za0.s, p0/m, p1/m, z1.s, z4.s + 64: 80836851 fmops za1.s, p2/m, p3/m, z2.s, z3.s + 68: 8082b072 fmops za2.s, p4/m, p5/m, z3.s, z2.s + 6c: 8081f893 fmops za3.s, p6/m, p7/m, z4.s, z1.s + 70: 80841c30 fmops za0.s, p7/m, p0/m, z1.s, z4.s + 74: 80833851 fmops za1.s, p6/m, p1/m, z2.s, z3.s + 78: 80825472 fmops za2.s, p5/m, p2/m, z3.s, z2.s + 7c: 80817093 fmops za3.s, p4/m, p3/m, z4.s, z1.s + 80: 80842030 fmops za0.s, p0/m, p1/m, z1.s, z4.s + 84: 80836851 fmops za1.s, p2/m, p3/m, z2.s, z3.s + 88: 8082b072 fmops za2.s, p4/m, p5/m, z3.s, z2.s + 8c: 8081f893 fmops za3.s, p6/m, p7/m, z4.s, z1.s + 90: a0842020 smopa za0.s, p0/m, p1/m, z1.b, z4.b + 94: a0836841 smopa za1.s, p2/m, p3/m, z2.b, z3.b + 98: a082b062 smopa za2.s, p4/m, p5/m, z3.b, z2.b + 9c: a081f883 smopa za3.s, p6/m, p7/m, z4.b, z1.b + a0: a0842030 smops za0.s, p0/m, p1/m, z1.b, z4.b + a4: a0836851 smops za1.s, p2/m, p3/m, z2.b, z3.b + a8: a082b072 smops za2.s, p4/m, p5/m, z3.b, z2.b + ac: a081f893 smops za3.s, p6/m, p7/m, z4.b, z1.b + b0: a0a42020 sumopa za0.s, p0/m, p1/m, z1.b, z4.b + b4: a0a36841 sumopa za1.s, p2/m, p3/m, z2.b, z3.b + b8: a0a2b062 sumopa za2.s, p4/m, p5/m, z3.b, z2.b + bc: a0a1f883 sumopa za3.s, p6/m, p7/m, z4.b, z1.b + c0: a0a42030 sumops za0.s, p0/m, p1/m, z1.b, z4.b + c4: a0a36851 sumops za1.s, p2/m, p3/m, z2.b, z3.b + c8: a0a2b072 sumops za2.s, p4/m, p5/m, z3.b, z2.b + cc: a0a1f893 sumops za3.s, p6/m, p7/m, z4.b, z1.b + d0: a0a41c30 sumops za0.s, p7/m, p0/m, z1.b, z4.b + d4: a0a33851 sumops za1.s, p6/m, p1/m, z2.b, z3.b + d8: a0a25472 sumops za2.s, p5/m, p2/m, z3.b, z2.b + dc: a0a17093 sumops za3.s, p4/m, p3/m, z4.b, z1.b + e0: a1a42020 umopa za0.s, p0/m, p1/m, z1.b, z4.b + e4: a1a36841 umopa za1.s, p2/m, p3/m, z2.b, z3.b + e8: a1a2b062 umopa za2.s, p4/m, p5/m, z3.b, z2.b + ec: a1a1f883 umopa za3.s, p6/m, p7/m, z4.b, z1.b + f0: a1a42030 umops za0.s, p0/m, p1/m, z1.b, z4.b + f4: a1a36851 umops za1.s, p2/m, p3/m, z2.b, z3.b + f8: a1a2b072 umops za2.s, p4/m, p5/m, z3.b, z2.b + fc: a1a1f893 umops za3.s, p6/m, p7/m, z4.b, z1.b + 100: a1842020 usmopa za0.s, p0/m, p1/m, z1.b, z4.b + 104: a1836841 usmopa za1.s, p2/m, p3/m, z2.b, z3.b + 108: a182b062 usmopa za2.s, p4/m, p5/m, z3.b, z2.b + 10c: a181f883 usmopa za3.s, p6/m, p7/m, z4.b, z1.b + 110: a1841c20 usmopa za0.s, p7/m, p0/m, z1.b, z4.b + 114: a1833841 usmopa za1.s, p6/m, p1/m, z2.b, z3.b + 118: a1825462 usmopa za2.s, p5/m, p2/m, z3.b, z2.b + 11c: a1817083 usmopa za3.s, p4/m, p3/m, z4.b, z1.b + 120: a1842030 usmops za0.s, p0/m, p1/m, z1.b, z4.b + 124: a1836851 usmops za1.s, p2/m, p3/m, z2.b, z3.b + 128: a182b072 usmops za2.s, p4/m, p5/m, z3.b, z2.b + 12c: a181f893 usmops za3.s, p6/m, p7/m, z4.b, z1.b + 130: 8181f883 bfmopa za3.s, p6/m, p7/m, z4.h, z1.h + 134: 8181f893 bfmops za3.s, p6/m, p7/m, z4.h, z1.h + 138: 81a1f883 fmopa za3.s, p6/m, p7/m, z4.h, z1.h + 13c: 8081f893 fmops za3.s, p6/m, p7/m, z4.s, z1.s + 140: a1a1f883 umopa za3.s, p6/m, p7/m, z4.b, z1.b + 144: a1a1f893 umops za3.s, p6/m, p7/m, z4.b, z1.b + 148: a1817083 usmopa za3.s, p4/m, p3/m, z4.b, z1.b + 14c: a181f893 usmops za3.s, p6/m, p7/m, z4.b, z1.b diff --git a/gas/testsuite/gas/aarch64/sme.s b/gas/testsuite/gas/aarch64/sme.s new file mode 100644 index 0000000..ad48fa0 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme.s @@ -0,0 +1,123 @@ +/* Scalable Matrix Extension (SME). */ + +/* ADDHA 32-bit variant. */ +addha za0.s, p0/m, p1/m, z1.s +addha za1.s, p2/m, p3/m, z2.s +addha za2.s, p4/m, p5/m, z3.s +addha za3.s, p6/m, p7/m, z4.s + +/* ADDVA 32-bit variant. */ +addva za0.s, p0/m, p1/m, z1.s +addva za1.s, p2/m, p3/m, z2.s +addva za2.s, p4/m, p5/m, z3.s +addva za3.s, p6/m, p7/m, z4.s + +/* BFMOPA. */ +bfmopa za0.s, p0/m, p1/m, z1.h, z4.h +bfmopa za1.s, p2/m, p3/m, z2.h, z3.h +bfmopa za2.s, p4/m, p5/m, z3.h, z2.h +bfmopa za3.s, p6/m, p7/m, z4.h, z1.h + +/* BFMOPS. */ +bfmops za0.s, p0/m, p1/m, z1.h, z4.h +bfmops za1.s, p2/m, p3/m, z2.h, z3.h +bfmops za2.s, p4/m, p5/m, z3.h, z2.h +bfmops za3.s, p6/m, p7/m, z4.h, z1.h + +/* FMOPA (non-widening), single-precision. */ +fmopa za0.s, p0/m, p1/m, z1.s, z4.s +fmopa za1.s, p2/m, p3/m, z2.s, z3.s +fmopa za2.s, p4/m, p5/m, z3.s, z2.s +fmopa za3.s, p6/m, p7/m, z4.s, z1.s + +/* FMOPA (widening) */ +fmopa za0.s, p0/m, p1/m, z1.h, z4.h +fmopa za1.s, p2/m, p3/m, z2.h, z3.h +fmopa za2.s, p4/m, p5/m, z3.h, z2.h +fmopa za3.s, p6/m, p7/m, z4.h, z1.h + +/* FMOPS (non-widening), single-precision. */ +fmops za0.s, p0/m, p1/m, z1.s, z4.s +fmops za1.s, p2/m, p3/m, z2.s, z3.s +fmops za2.s, p4/m, p5/m, z3.s, z2.s +fmops za3.s, p6/m, p7/m, z4.s, z1.s +fmops za0.s, p7/m, p0/m, z1.s, z4.s +fmops za1.s, p6/m, p1/m, z2.s, z3.s +fmops za2.s, p5/m, p2/m, z3.s, z2.s +fmops za3.s, p4/m, p3/m, z4.s, z1.s + +/* FMOPS (widening) */ +fmops za0.s, p0/m, p1/m, z1.s, z4.s +fmops za1.s, p2/m, p3/m, z2.s, z3.s +fmops za2.s, p4/m, p5/m, z3.s, z2.s +fmops za3.s, p6/m, p7/m, z4.s, z1.s + +/* SMOPA 32-bit variant. */ +smopa za0.s, p0/m, p1/m, z1.b, z4.b +smopa za1.s, p2/m, p3/m, z2.b, z3.b +smopa za2.s, p4/m, p5/m, z3.b, z2.b +smopa za3.s, p6/m, p7/m, z4.b, z1.b + +/* SMOPS 32-bit variant. */ +smops za0.s, p0/m, p1/m, z1.b, z4.b +smops za1.s, p2/m, p3/m, z2.b, z3.b +smops za2.s, p4/m, p5/m, z3.b, z2.b +smops za3.s, p6/m, p7/m, z4.b, z1.b + +/* SUMOPA 32-bit variant. */ +sumopa za0.s, p0/m, p1/m, z1.b, z4.b +sumopa za1.s, p2/m, p3/m, z2.b, z3.b +sumopa za2.s, p4/m, p5/m, z3.b, z2.b +sumopa za3.s, p6/m, p7/m, z4.b, z1.b + +/* SUMOPS 32-bit variant. */ +sumops za0.s, p0/m, p1/m, z1.b, z4.b +sumops za1.s, p2/m, p3/m, z2.b, z3.b +sumops za2.s, p4/m, p5/m, z3.b, z2.b +sumops za3.s, p6/m, p7/m, z4.b, z1.b +sumops za0.s, p7/m, p0/m, z1.b, z4.b +sumops za1.s, p6/m, p1/m, z2.b, z3.b +sumops za2.s, p5/m, p2/m, z3.b, z2.b +sumops za3.s, p4/m, p3/m, z4.b, z1.b + +/* UMOPA 32-bit variant. */ +umopa za0.s, p0/m, p1/m, z1.b, z4.b +umopa za1.s, p2/m, p3/m, z2.b, z3.b +umopa za2.s, p4/m, p5/m, z3.b, z2.b +umopa za3.s, p6/m, p7/m, z4.b, z1.b + +/* UMOPS 32-bit variant. */ +umops za0.s, p0/m, p1/m, z1.b, z4.b +umops za1.s, p2/m, p3/m, z2.b, z3.b +umops za2.s, p4/m, p5/m, z3.b, z2.b +umops za3.s, p6/m, p7/m, z4.b, z1.b + +/* USMOPA 32-bit variant. */ +usmopa za0.s, p0/m, p1/m, z1.b, z4.b +usmopa za1.s, p2/m, p3/m, z2.b, z3.b +usmopa za2.s, p4/m, p5/m, z3.b, z2.b +usmopa za3.s, p6/m, p7/m, z4.b, z1.b +usmopa za0.s, p7/m, p0/m, z1.b, z4.b +usmopa za1.s, p6/m, p1/m, z2.b, z3.b +usmopa za2.s, p5/m, p2/m, z3.b, z2.b +usmopa za3.s, p4/m, p3/m, z4.b, z1.b + +/* USMOPS 32-bit variant. */ +usmops za0.s, p0/m, p1/m, z1.b, z4.b +usmops za1.s, p2/m, p3/m, z2.b, z3.b +usmops za2.s, p4/m, p5/m, z3.b, z2.b +usmops za3.s, p6/m, p7/m, z4.b, z1.b + +/* Register aliases. */ +foo .req za3 +bar .req za7 +baz .req za0 + +bfmopa foo.s, p6/m, p7/m, z4.h, z1.h +bfmops foo.s, p6/m, p7/m, z4.h, z1.h +fmopa foo.s, p6/m, p7/m, z4.h, z1.h +fmops foo.s, p6/m, p7/m, z4.s, z1.s +umopa foo.s, p6/m, p7/m, z4.b, z1.b +umops foo.s, p6/m, p7/m, z4.b, z1.b +usmopa foo.s, p4/m, p3/m, z4.b, z1.b +usmops foo.s, p6/m, p7/m, z4.b, z1.b diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index e361920..cc5a5f3 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -445,6 +445,9 @@ enum aarch64_opnd AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */ AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */ AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */ + AARCH64_OPND_SME_ZAda_2b, /* SME <ZAda>.S, 2-bits. */ + AARCH64_OPND_SME_ZAda_3b, /* SME <ZAda>.D, 3-bits. */ + AARCH64_OPND_SME_Pm, /* SME scalable predicate register, bits [15:13]. */ AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */ AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */ }; @@ -609,6 +612,7 @@ enum aarch64_insn_class movewide, pcreladdr, ic_system, + sme_misc, sve_cpy, sve_index, sve_limm, diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index 26d61da..4839fef 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -661,6 +661,9 @@ aarch64_insert_operand (const aarch64_operand *self, case 198: case 204: case 207: + case 209: + case 210: + case 211: return aarch64_ins_regno (self, info, code, inst, errors); case 15: return aarch64_ins_reg_extended (self, info, code, inst, errors); @@ -672,7 +675,7 @@ aarch64_insert_operand (const aarch64_operand *self, case 33: case 34: case 35: - case 210: + case 213: return aarch64_ins_reglane (self, info, code, inst, errors); case 36: return aarch64_ins_reglist (self, info, code, inst, errors); @@ -717,7 +720,7 @@ aarch64_insert_operand (const aarch64_operand *self, case 187: case 188: case 189: - case 209: + case 212: return aarch64_ins_imm (self, info, code, inst, errors); case 44: case 45: diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index 1b98ee6..4376e3b 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -36,11 +36,187 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 28) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00000xxxxxxxxxxxxxxxxxxxxxxxx - udf. */ - return 754; + if (((word >> 21) & 0x1) == 0) + { + if (((word >> 22) & 0x1) == 0) + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xxx00000000xxxxxxxxxxxxxxxxxxxxx + udf. */ + return 754; + } + else + { + if (((word >> 4) & 0x1) == 0) + { + if (((word >> 29) & 0x1) == 0) + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0000000100xxxxxxxxxxxxxxxx0xxxx + fmopa. */ + return 2354; + } + else + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000100xxxx0xxxxxxxxxxx0xxxx + addha. */ + return 2348; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000100xxxx1xxxxxxxxxxx0xxxx + addva. */ + return 2350; + } + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100000100xxxxxxxxxxxxxxxx0xxxx + smopa. */ + return 2360; + } + } + else + { + if (((word >> 29) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx000000100xxxxxxxxxxxxxxxx1xxxx + fmops. */ + return 2357; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100000100xxxxxxxxxxxxxxxx1xxxx + smops. */ + return 2362; + } + } + } + } + else + { + if (((word >> 4) & 0x1) == 0) + { + if (((word >> 29) & 0x1) == 0) + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0000000x10xxxxxxxxxxxxxxxx0xxxx + fmopa. */ + return 2355; + } + else + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000x10xxxx0xxxxxxxxxxx0xxxx + addha. */ + return 2349; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000x10xxxx1xxxxxxxxxxx0xxxx + addva. */ + return 2351; + } + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100000x10xxxxxxxxxxxxxxxx0xxxx + smopa. */ + return 2361; + } + } + else + { + if (((word >> 29) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx000000x10xxxxxxxxxxxxxxxx1xxxx + fmops. */ + return 2358; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100000x10xxxxxxxxxxxxxxxx1xxxx + smops. */ + return 2363; + } + } + } + } + else + { + if (((word >> 4) & 0x1) == 0) + { + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xxx00000x01xxxxxxxxxxxxxxxx0xxxx + sumopa. */ + return 2364; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xxx00000x11xxxxxxxxxxxxxxxx0xxxx + sumopa. */ + return 2365; + } + } + else + { + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xxx00000x01xxxxxxxxxxxxxxxx1xxxx + sumops. */ + return 2366; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xxx00000x11xxxxxxxxxxxxxxxx1xxxx + sumops. */ + return 2367; + } + } + } } else { @@ -64,42 +240,174 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 29) & 0x1) == 0) + if (((word >> 28) & 0x1) == 0) { - if (((word >> 30) & 0x1) == 0) + if (((word >> 4) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x00x0001xxxxxxxxxxxxxxxxxxxxxxxx - add. */ - return 12; + if (((word >> 21) & 0x1) == 0) + { + if (((word >> 22) & 0x1) == 0) + { + if (((word >> 29) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx000001x00xxxxxxxxxxxxxxxx0xxxx + bfmopa. */ + return 2352; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001x00xxxxxxxxxxxxxxxx0xxxx + usmopa. */ + return 2372; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xxx00001x10xxxxxxxxxxxxxxxx0xxxx + usmopa. */ + return 2373; + } + } + else + { + if (((word >> 22) & 0x1) == 0) + { + if (((word >> 29) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx000001x01xxxxxxxxxxxxxxxx0xxxx + fmopa. */ + return 2356; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001x01xxxxxxxxxxxxxxxx0xxxx + umopa. */ + return 2368; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xxx00001x11xxxxxxxxxxxxxxxx0xxxx + umopa. */ + return 2369; + } + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x10x0001xxxxxxxxxxxxxxxxxxxxxxxx - sub. */ - return 16; + if (((word >> 21) & 0x1) == 0) + { + if (((word >> 22) & 0x1) == 0) + { + if (((word >> 29) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx000001x00xxxxxxxxxxxxxxxx1xxxx + bfmops. */ + return 2353; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001x00xxxxxxxxxxxxxxxx1xxxx + usmops. */ + return 2374; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xxx00001x10xxxxxxxxxxxxxxxx1xxxx + usmops. */ + return 2375; + } + } + else + { + if (((word >> 22) & 0x1) == 0) + { + if (((word >> 29) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx000001x01xxxxxxxxxxxxxxxx1xxxx + fmops. */ + return 2359; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001x01xxxxxxxxxxxxxxxx1xxxx + umops. */ + return 2370; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xxx00001x11xxxxxxxxxxxxxxxx1xxxx + umops. */ + return 2371; + } + } } } else { - if (((word >> 30) & 0x1) == 0) + if (((word >> 29) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x01x0001xxxxxxxxxxxxxxxxxxxxxxxx - adds. */ - return 14; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0010001xxxxxxxxxxxxxxxxxxxxxxxx + add. */ + return 12; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1010001xxxxxxxxxxxxxxxxxxxxxxxx + sub. */ + return 16; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x11x0001xxxxxxxxxxxxxxxxxxxxxxxx - subs. */ - return 17; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0110001xxxxxxxxxxxxxxxxxxxxxxxx + adds. */ + return 14; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1110001xxxxxxxxxxxxxxxxxxxxxxxx + subs. */ + return 17; + } } } } @@ -2423,7 +2731,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001000xxxxxxxxx00xxxxxxxxxx stlurb. */ - return 2388; + return 2416; } else { @@ -2431,7 +2739,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001000xxxxxxxxx00xxxxxxxxxx stlur. */ - return 2396; + return 2424; } } else @@ -2442,7 +2750,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01011001000xxxxxxxxx00xxxxxxxxxx stlurh. */ - return 2392; + return 2420; } else { @@ -2450,7 +2758,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11011001000xxxxxxxxx00xxxxxxxxxx stlur. */ - return 2399; + return 2427; } } } @@ -2530,7 +2838,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001010xxxxxxxxx00xxxxxxxxxx ldapurb. */ - return 2389; + return 2417; } else { @@ -2538,7 +2846,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001010xxxxxxxxx00xxxxxxxxxx ldapur. */ - return 2397; + return 2425; } } else @@ -2549,7 +2857,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01011001010xxxxxxxxx00xxxxxxxxxx ldapurh. */ - return 2393; + return 2421; } else { @@ -2557,7 +2865,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11011001010xxxxxxxxx00xxxxxxxxxx ldapur. */ - return 2400; + return 2428; } } } @@ -2640,7 +2948,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001100xxxxxxxxx00xxxxxxxxxx ldapursb. */ - return 2391; + return 2419; } else { @@ -2648,7 +2956,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001100xxxxxxxxx00xxxxxxxxxx ldapursw. */ - return 2398; + return 2426; } } else @@ -2657,7 +2965,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1011001100xxxxxxxxx00xxxxxxxxxx ldapursh. */ - return 2395; + return 2423; } } else @@ -2668,7 +2976,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0011001110xxxxxxxxx00xxxxxxxxxx ldapursb. */ - return 2390; + return 2418; } else { @@ -2676,7 +2984,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1011001110xxxxxxxxx00xxxxxxxxxx ldapursh. */ - return 2394; + return 2422; } } } @@ -3162,7 +3470,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x00xxxxxx0xx10xxxxxxxxxx setf8. */ - return 2386; + return 2414; } else { @@ -3170,7 +3478,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x00xxxxxx1xx10xxxxxxxxxx setf16. */ - return 2387; + return 2415; } } else @@ -3316,7 +3624,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010000xxxxxxxxx01xxxxxxxxxx rmif. */ - return 2385; + return 2413; } else { @@ -4365,7 +4673,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x01x1xxxxx000110xxxxxxxxxx usdot. */ - return 2405; + return 2433; } } } @@ -4439,7 +4747,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x01x1xxxxx000111xxxxxxxxxx sudot. */ - return 2406; + return 2434; } } } @@ -7058,7 +7366,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx011110xxxxxxxxxx usdot. */ - return 2404; + return 2432; } } } @@ -8762,7 +9070,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0100xxx10101xxxxxxxxxxxxx bfcvtnt. */ - return 2433; + return 2461; } } else @@ -9005,7 +9313,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x00x1xxxxxx00xxxxxxxxxxxxx ld1rob. */ - return 2409; + return 2437; } else { @@ -9013,7 +9321,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x01x1xxxxxx00xxxxxxxxxxxxx ld1roh. */ - return 2410; + return 2438; } } else @@ -9245,7 +9553,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx010xxxxxxxxxxxxx bfdot. */ - return 2430; + return 2458; } else { @@ -9266,7 +9574,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx010xx0xxxxxxxxxx bfmlalb. */ - return 2437; + return 2465; } else { @@ -9274,7 +9582,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx010xx1xxxxxxxxxx bfmlalt. */ - return 2436; + return 2464; } } else @@ -9329,7 +9637,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0011xxxxx1x0xxxxxxxxxxxxx bfdot. */ - return 2429; + return 2457; } else { @@ -9341,7 +9649,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx1x0xx0xxxxxxxxxx bfmlalb. */ - return 2435; + return 2463; } else { @@ -9349,7 +9657,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx1x0xx1xxxxxxxxxx bfmlalt. */ - return 2434; + return 2462; } } else @@ -9400,7 +9708,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x00x1xxxxx001xxxxxxxxxxxxx ld1rob. */ - return 2413; + return 2441; } else { @@ -9408,7 +9716,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x01x1xxxxx001xxxxxxxxxxxxx ld1roh. */ - return 2414; + return 2442; } } else @@ -9767,7 +10075,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx111xxxxxxxxxxxxx fmmla. */ - return 2407; + return 2435; } else { @@ -9800,7 +10108,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx111xxxxxxxxxxxxx bfmmla. */ - return 2431; + return 2459; } else { @@ -9830,7 +10138,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx111xxxxxxxxxxxxx fmmla. */ - return 2408; + return 2436; } else { @@ -9959,7 +10267,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000x00xxxxxxxxxx zip1. */ - return 2417; + return 2445; } else { @@ -9969,7 +10277,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000010xxxxxxxxxx uzp1. */ - return 2419; + return 2447; } else { @@ -9977,7 +10285,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000110xxxxxxxxxx trn1. */ - return 2421; + return 2449; } } } @@ -9989,7 +10297,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000x01xxxxxxxxxx zip2. */ - return 2418; + return 2446; } else { @@ -9999,7 +10307,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000011xxxxxxxxxx uzp2. */ - return 2420; + return 2448; } else { @@ -10007,7 +10315,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000111xxxxxxxxxx trn2. */ - return 2422; + return 2450; } } } @@ -11055,7 +11363,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1000xxxxx100110xxxxxxxxxx smmla. */ - return 2401; + return 2429; } else { @@ -11063,7 +11371,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1100xxxxx100110xxxxxxxxxx usmmla. */ - return 2403; + return 2431; } } else @@ -11072,7 +11380,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1x10xxxxx100110xxxxxxxxxx ummla. */ - return 2402; + return 2430; } } } @@ -12568,7 +12876,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx000xxxxxxxxxxxxx ld1row. */ - return 2411; + return 2439; } else { @@ -12576,7 +12884,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx000xxxxxxxxxxxxx ld1rod. */ - return 2412; + return 2440; } } } @@ -12950,7 +13258,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx001xxxxxxxxxxxxx ld1row. */ - return 2415; + return 2443; } else { @@ -12958,7 +13266,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx001xxxxxxxxxxxxx ld1rod. */ - return 2416; + return 2444; } } } @@ -14392,7 +14700,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x110001x10101xxxxxxxxxxxxx bfcvt. */ - return 2432; + return 2460; } } else @@ -16461,7 +16769,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x1001xxxxxxxxxx smmla. */ - return 2423; + return 2451; } } } @@ -16494,7 +16802,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x0101xxxxxxxxxx sdot. */ - return 2349; + return 2377; } } else @@ -16568,7 +16876,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x1011xxxxxxxxxx usmmla. */ - return 2425; + return 2453; } } } @@ -16601,7 +16909,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x0111xxxxxxxxxx usdot. */ - return 2426; + return 2454; } } else @@ -16648,7 +16956,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110000xxxxxxxxxxxxxxxxxxxxx eor3. */ - return 2356; + return 2384; } else { @@ -16656,7 +16964,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110100xxxxxxxxxxxxxxxxxxxxx xar. */ - return 2358; + return 2386; } } else @@ -16667,7 +16975,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx0xxxxxxxxxxxxxxx sm3ss1. */ - return 2360; + return 2388; } else { @@ -16681,7 +16989,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110010xxxxx1xxx00xxxxxxxxxx sm3tt1a. */ - return 2361; + return 2389; } else { @@ -16689,7 +16997,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110110xxxxx1xxx00xxxxxxxxxx sha512su0. */ - return 2354; + return 2382; } } else @@ -16698,7 +17006,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx1xxx10xxxxxxxxxx sm3tt2a. */ - return 2363; + return 2391; } } else @@ -16711,7 +17019,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110010xxxxx1xxx01xxxxxxxxxx sm3tt1b. */ - return 2362; + return 2390; } else { @@ -16719,7 +17027,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110110xxxxx1xxx01xxxxxxxxxx sm4e. */ - return 2367; + return 2395; } } else @@ -16728,7 +17036,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx1xxx11xxxxxxxxxx sm3tt2b. */ - return 2364; + return 2392; } } } @@ -16909,7 +17217,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx100101xxxxxxxxxx udot. */ - return 2348; + return 2376; } } else @@ -16940,7 +17248,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx101x01xxxxxxxxxx ummla. */ - return 2424; + return 2452; } else { @@ -16959,7 +17267,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx1x1011xxxxxxxxxx bfmmla. */ - return 2440; + return 2468; } else { @@ -16969,7 +17277,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx1011100x0xxxxx1x1111xxxxxxxxxx bfdot. */ - return 2438; + return 2466; } else { @@ -16979,7 +17287,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011101x0xxxxx1x1111xxxxxxxxxx bfmlalb. */ - return 2445; + return 2473; } else { @@ -16987,7 +17295,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011101x0xxxxx1x1111xxxxxxxxxx bfmlalt. */ - return 2444; + return 2472; } } } @@ -17571,7 +17879,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000011101x1xxxx1011010xxxxxxxxxx bfcvtn. */ - return 2441; + return 2469; } else { @@ -17579,7 +17887,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010011101x1xxxx1011010xxxxxxxxxx bfcvtn2. */ - return 2442; + return 2470; } } } @@ -17897,7 +18205,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx0xxxxxxxxxxxxxxx bcax. */ - return 2359; + return 2387; } } else @@ -18508,7 +18816,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11001110xx1xxxxx100000xxxxxxxxxx sha512h. */ - return 2352; + return 2380; } } } @@ -18560,7 +18868,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11001110xx1xxxxx110000xxxxxxxxxx sm3partw1. */ - return 2365; + return 2393; } } } @@ -18803,7 +19111,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100010xxxxxxxxxx sha512su1. */ - return 2355; + return 2383; } } else @@ -18879,7 +19187,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x0011100x1xxxxx110010xxxxxxxxxx sm4ekey. */ - return 2368; + return 2396; } } else @@ -19705,7 +20013,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100001xxxxxxxxxx sha512h2. */ - return 2353; + return 2381; } } else @@ -19737,7 +20045,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x0011100x1xxxxx110001xxxxxxxxxx sm3partw2. */ - return 2366; + return 2394; } } else @@ -19977,7 +20285,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100011xxxxxxxxxx rax1. */ - return 2357; + return 2385; } } else @@ -20009,7 +20317,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011100x1xxxxx110011xxxxxxxxxx fmlal2. */ - return 2371; + return 2399; } else { @@ -20017,7 +20325,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011100x1xxxxx110011xxxxxxxxxx fmlal2. */ - return 2375; + return 2403; } } } @@ -20039,7 +20347,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011101x1xxxxx110011xxxxxxxxxx fmlsl2. */ - return 2372; + return 2400; } else { @@ -20047,7 +20355,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011101x1xxxxx110011xxxxxxxxxx fmlsl2. */ - return 2376; + return 2404; } } } @@ -20086,7 +20394,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x00011100x1xxxxx111011xxxxxxxxxx fmlal. */ - return 2369; + return 2397; } else { @@ -20094,7 +20402,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10011100x1xxxxx111011xxxxxxxxxx fmlal. */ - return 2373; + return 2401; } } else @@ -20116,7 +20424,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x00011101x1xxxxx111011xxxxxxxxxx fmlsl. */ - return 2370; + return 2398; } else { @@ -20124,7 +20432,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10011101x1xxxxx111011xxxxxxxxxx fmlsl. */ - return 2374; + return 2402; } } else @@ -21932,7 +22240,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0001111xxxxxxxx0000x0xxxxxxxxxx fmlal. */ - return 2377; + return 2405; } else { @@ -21940,7 +22248,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1001111xxxxxxxx0000x0xxxxxxxxxx fmlal. */ - return 2381; + return 2409; } } else @@ -21962,7 +22270,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0001111xxxxxxxx0100x0xxxxxxxxxx fmlsl. */ - return 2378; + return 2406; } else { @@ -21970,7 +22278,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1001111xxxxxxxx0100x0xxxxxxxxxx fmlsl. */ - return 2382; + return 2410; } } else @@ -22476,7 +22784,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111xxxxxxxx1000x0xxxxxxxxxx fmlal2. */ - return 2379; + return 2407; } else { @@ -22484,7 +22792,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111xxxxxxxx1000x0xxxxxxxxxx fmlal2. */ - return 2383; + return 2411; } } } @@ -22506,7 +22814,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111xxxxxxxx1100x0xxxxxxxxxx fmlsl2. */ - return 2380; + return 2408; } else { @@ -22514,7 +22822,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111xxxxxxxx1100x0xxxxxxxxxx fmlsl2. */ - return 2384; + return 2412; } } } @@ -22570,7 +22878,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx001111xxxxxxxx1110x0xxxxxxxxxx sdot. */ - return 2351; + return 2379; } else { @@ -22578,7 +22886,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101111xxxxxxxx1110x0xxxxxxxxxx udot. */ - return 2350; + return 2378; } } } @@ -22681,7 +22989,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111100xxxxxx1111x0xxxxxxxxxx sudot. */ - return 2428; + return 2456; } else { @@ -22689,7 +22997,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111110xxxxxx1111x0xxxxxxxxxx usdot. */ - return 2427; + return 2455; } } else @@ -22700,7 +23008,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111101xxxxxx1111x0xxxxxxxxxx bfdot. */ - return 2439; + return 2467; } else { @@ -22710,7 +23018,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x000111111xxxxxx1111x0xxxxxxxxxx bfmlalb. */ - return 2447; + return 2475; } else { @@ -22718,7 +23026,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x100111111xxxxxx1111x0xxxxxxxxxx bfmlalt. */ - return 2446; + return 2474; } } } @@ -23352,8 +23660,8 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 824: return NULL; /* fsqrt --> NULL. */ case 832: value = 833; break; /* frintz --> frintz. */ case 833: return NULL; /* frintz --> NULL. */ - case 825: value = 2443; break; /* fcvt --> bfcvt. */ - case 2443: return NULL; /* bfcvt --> NULL. */ + case 825: value = 2471; break; /* fcvt --> bfcvt. */ + case 2471: return NULL; /* bfcvt --> NULL. */ case 834: value = 835; break; /* frinta --> frinta. */ case 835: return NULL; /* frinta --> NULL. */ case 836: value = 837; break; /* frintx --> frintx. */ @@ -23854,6 +24162,9 @@ aarch64_extract_operand (const aarch64_operand *self, case 198: case 204: case 207: + case 209: + case 210: + case 211: return aarch64_ext_regno (self, info, code, inst, errors); case 10: return aarch64_ext_regrt_sysins (self, info, code, inst, errors); @@ -23869,7 +24180,7 @@ aarch64_extract_operand (const aarch64_operand *self, case 33: case 34: case 35: - case 210: + case 213: return aarch64_ext_reglane (self, info, code, inst, errors); case 36: return aarch64_ext_reglist (self, info, code, inst, errors); @@ -23915,7 +24226,7 @@ aarch64_extract_operand (const aarch64_operand *self, case 187: case 188: case 189: - case 209: + case 212: return aarch64_ext_imm (self, info, code, inst, errors); case 44: case 45: diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 820f6f1..cf1ce0b 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -233,6 +233,9 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SVE_REG, "SVE_ZnxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a list of SVE vector registers"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "an SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_2b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_2b}, "an SME ZA tile ZA0-ZA3"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_3b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_3b}, "an SME ZA tile ZA0-ZA7"}, + {AARCH64_OPND_CLASS_PRED_REG, "SME_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pm}, "an SVE predicate register"}, {AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate for TME tcancel"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"}, {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"}, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index dea4b8e..8ced8e0 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -321,6 +321,9 @@ const aarch64_field fields[] = { 19, 2 }, /* SVE_tszl_19: triangular size select low, bits [20,19]. */ { 14, 1 }, /* SVE_xs_14: UXTW/SXTW select (bit 14). */ { 22, 1 }, /* SVE_xs_22: UXTW/SXTW select (bit 22). */ + { 0, 2 }, /* SME ZAda tile ZA0-ZA3. */ + { 0, 3 }, /* SME ZAda tile ZA0-ZA7. */ + { 13, 3 }, /* SME Pm second source scalable predicate register P0-P7. */ { 11, 2 }, /* rotate1: FCMLA immediate rotate. */ { 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */ { 12, 1 }, /* rotate3: FCADD immediate rotate. */ @@ -3304,6 +3307,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SVE_Pm: case AARCH64_OPND_SVE_Pn: case AARCH64_OPND_SVE_Pt: + case AARCH64_OPND_SME_Pm: if (opnd->qualifier == AARCH64_OPND_QLF_NIL) snprintf (buf, size, "p%d", opnd->reg.regno); else if (opnd->qualifier == AARCH64_OPND_QLF_P_Z @@ -3345,6 +3349,12 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, opnd->reglane.index); break; + case AARCH64_OPND_SME_ZAda_2b: + case AARCH64_OPND_SME_ZAda_3b: + snprintf (buf, size, "za%d.%s", opnd->reg.regno, + aarch64_get_qualifier_name (opnd->qualifier)); + break; + case AARCH64_OPND_CRn: case AARCH64_OPND_CRm: snprintf (buf, size, "C%" PRIi64, opnd->imm.value); @@ -5277,6 +5287,7 @@ verify_constraints (const struct aarch64_inst *inst, case AARCH64_OPND_SVE_Pm: case AARCH64_OPND_SVE_Pn: case AARCH64_OPND_SVE_Pt: + case AARCH64_OPND_SME_Pm: inst_pred = inst_op; inst_pred_idx = i; break; diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index a4a2b6f..ba19c12 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -150,6 +150,9 @@ enum aarch64_field_kind FLD_SVE_tszl_19, FLD_SVE_xs_14, FLD_SVE_xs_22, + FLD_SME_ZAda_2b, + FLD_SME_ZAda_3b, + FLD_SME_Pm, FLD_rotate1, FLD_rotate2, FLD_rotate3, diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index d63b081..f725f2f 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2168,6 +2168,42 @@ { \ QLF3(X,X,NIL), \ } +/* e.g. ADDVA <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.S */ +#define OP_SME_ZADA_PN_PM_ZN_S \ +{ \ + QLF4(S_S,P_M,P_M,S_S), \ +} +/* e.g. ADDVA <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.D */ +#define OP_SME_ZADA_PN_PM_ZN_D \ +{ \ + QLF4(S_D,P_M,P_M,S_D), \ +} +/* e.g. BFMOPA <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H */ +#define OP_SME_ZADA_PN_PM_ZN_ZM \ +{ \ + QLF5(S_S,P_M,P_M,S_H,S_H), \ +} +#define OP_SME_ZADA_S_PM_PM_S_S \ +{ \ + QLF5(S_S,P_M,P_M,S_S,S_S) \ +} +#define OP_SME_ZADA_D_PM_PM_D_D \ +{ \ + QLF5(S_D,P_M,P_M,S_D,S_D) \ +} +#define OP_SME_ZADA_S_PM_PM_H_H \ +{ \ + QLF5(S_S,P_M,P_M,S_H,S_H) \ +} +#define OP_SME_ZADA_S_PM_PM_B_B \ +{ \ + QLF5(S_S,P_M,P_M,S_B,S_B) \ +} +#define OP_SME_ZADA_D_PM_PM_H_H \ +{ \ + QLF5(S_D,P_M,P_M,S_H,S_H) \ +} + /* e.g. UDOT <Vd>.2S, <Vn>.8B, <Vm>.8B. */ #define QL_V3DOT \ { \ @@ -2564,6 +2600,18 @@ static const aarch64_feature_set aarch64_feature_flagm = #define SVE2SM4_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2_SM4, OPS, QUALS, \ FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } +#define SME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ + { NAME, OPCODE, MASK, CLASS, OP, SME, OPS, QUALS, \ + FLAGS, 0, TIED, NULL } +#define SME_F64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ + { NAME, OPCODE, MASK, CLASS, OP, SME_F64, OPS, QUALS, \ + FLAGS, 0, TIED, NULL } +#define SME_I64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ + { NAME, OPCODE, MASK, CLASS, OP, SME_I64, OPS, QUALS, \ + FLAGS, 0, TIED, NULL } +#define SME_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ + { NAME, OPCODE, MASK, CLASS, OP, SME, OPS, QUALS, \ + FLAGS, CONSTRAINTS, TIED, NULL } #define SVE2BITPERM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2_BITPERM, OPS, QUALS, \ FLAGS | F_STRICT, 0, TIED, NULL } @@ -5045,6 +5093,35 @@ const struct aarch64_opcode aarch64_opcode_table[] = SVE2BITPERM_INSN ("bdep", 0x4500b400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), SVE2BITPERM_INSN ("bext", 0x4500b000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), SVE2BITPERM_INSN ("bgrp", 0x4500b800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), + /* SME instructions. */ + SME_INSN ("addha", 0xc0900000, 0xffff001c, sme_misc, 0, OP4 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SME_ZADA_PN_PM_ZN_S, 0, 0), + SME_I64_INSN ("addha", 0xc0d00000, 0xffff0018, sme_misc, 0, OP4 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SME_ZADA_PN_PM_ZN_D, 0, 0), + SME_INSN ("addva", 0xc0910000, 0xffff001c, sme_misc, 0, OP4 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SME_ZADA_PN_PM_ZN_S, 0, 0), + SME_I64_INSN ("addva", 0xc0d10000, 0xffff0018, sme_misc, 0, OP4 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SME_ZADA_PN_PM_ZN_D, 0, 0), + SME_INSN ("bfmopa", 0x81800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_PN_PM_ZN_ZM, 0, 0), + SME_INSN ("bfmops", 0x81800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_PN_PM_ZN_ZM, 0, 0), + SME_INSN ("fmopa", 0x80800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_S_S, 0, 0), + SME_F64_INSN ("fmopa", 0x80c00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_D_D, 0, 0), + SME_INSN ("fmopa", 0x81a00000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_H_H, 0, 0), + SME_INSN ("fmops", 0x80800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_S_S, 0, 0), + SME_F64_INSN ("fmops", 0x80c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_D_D, 0, 0), + SME_INSN ("fmops", 0x81a00010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_H_H, 0, 0), + SME_INSN ("smopa", 0xa0800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0), + SME_I64_INSN ("smopa", 0xa0c00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), + SME_INSN ("smops", 0xa0800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0), + SME_I64_INSN ("smops", 0xa0c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), + SME_INSN ("sumopa", 0xa0a00000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0), + SME_I64_INSN ("sumopa", 0xa0e00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), + SME_INSN ("sumops", 0xa0a00010 ,0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0), + SME_I64_INSN ("sumops", 0xa0e00010 ,0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), + SME_INSN ("umopa", 0xa1a00000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0), + SME_I64_INSN ("umopa", 0xa1e00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), + SME_INSN ("umops", 0xa1a00010 ,0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0), + SME_I64_INSN ("umops", 0xa1e00010 ,0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), + SME_INSN ("usmopa", 0xa1800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0), + SME_I64_INSN ("usmopa", 0xa1c00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), + SME_INSN ("usmops", 0xa1800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0), + SME_I64_INSN ("usmops", 0xa1c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), /* SIMD Dot Product (optional in v8.2-A). */ DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), @@ -5613,6 +5690,12 @@ const struct aarch64_opcode aarch64_opcode_table[] = "an SVE vector register") \ Y(SVE_REG, sve_reglist, "SVE_ZtxN", 0, F(FLD_SVE_Zt), \ "a list of SVE vector registers") \ + Y(SVE_REG, regno, "SME_ZAda_2b", 0, F(FLD_SME_ZAda_2b), \ + "an SME ZA tile ZA0-ZA3") \ + Y(SVE_REG, regno, "SME_ZAda_3b", 0, F(FLD_SME_ZAda_3b), \ + "an SME ZA tile ZA0-ZA7") \ + Y(PRED_REG, regno, "SME_Pm", 0, F(FLD_SME_Pm), \ + "an SVE predicate register") \ Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16), \ "a 16-bit unsigned immediate for TME tcancel") \ Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2), \ |