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-rw-r--r--gas/ChangeLog5
-rw-r--r--gas/testsuite/gas/arc/add_s-err.s2
-rw-r--r--opcodes/ChangeLog39
-rw-r--r--opcodes/arc-opc.c70
-rw-r--r--opcodes/riscv-dis.c2
5 files changed, 81 insertions, 37 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index f8fc64f..30d349b 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2017-07-25 Nick Clifton <nickc@redhat.com>
+
+ PR 21739
+ * testsuite/gas/arc/add_s-err.s: Update expected error message.
+
2017-07-24 Nick Clifton <nickc@redhat.com>
PR 21809
diff --git a/gas/testsuite/gas/arc/add_s-err.s b/gas/testsuite/gas/arc/add_s-err.s
index 024bc43..95fcf64 100644
--- a/gas/testsuite/gas/arc/add_s-err.s
+++ b/gas/testsuite/gas/arc/add_s-err.s
@@ -4,7 +4,7 @@
; { dg-do assemble { target arc*-*-* } }
; { dg-options "--mcpu=arc700" }
;; The following insns are accepted by ARCv2 only
- add_s r4,r4,-1 ; { dg-error "Error: Register must be either r0-r3 or r12-r15 for instruction." }
+ add_s r4,r4,-1 ; { dg-error "Error: register must be either r0-r3 or r12-r15 for instruction" }
add_s 0,0xAAAA5555,-1 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" }
add_s r0,r15,0x20 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" }
add_s r1,r15,0x20 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" }
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index ef026af..59ff038 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,42 @@
+2017-07-25 Nick Clifton <nickc@redhat.com>
+
+ PR 21739
+ * arc-opc.c (insert_rhv2): Use lower case first letter in error
+ message.
+ (insert_r0): Likewise.
+ (insert_r1): Likewise.
+ (insert_r2): Likewise.
+ (insert_r3): Likewise.
+ (insert_sp): Likewise.
+ (insert_gp): Likewise.
+ (insert_pcl): Likewise.
+ (insert_blink): Likewise.
+ (insert_ilink1): Likewise.
+ (insert_ilink2): Likewise.
+ (insert_ras): Likewise.
+ (insert_rbs): Likewise.
+ (insert_rcs): Likewise.
+ (insert_simm3s): Likewise.
+ (insert_rrange): Likewise.
+ (insert_r13el): Likewise.
+ (insert_fpel): Likewise.
+ (insert_blinkel): Likewise.
+ (insert_pclel): Likewise.
+ (insert_nps_bitop_size_2b): Likewise.
+ (insert_nps_imm_offset): Likewise.
+ (insert_nps_imm_entry): Likewise.
+ (insert_nps_size_16bit): Likewise.
+ (insert_nps_##NAME##_pos): Likewise.
+ (insert_nps_##NAME): Likewise.
+ (insert_nps_bitop_ins_ext): Likewise.
+ (insert_nps_##NAME): Likewise.
+ (insert_nps_min_hofs): Likewise.
+ (insert_nps_##NAME): Likewise.
+ (insert_nps_rbdouble_64): Likewise.
+ (insert_nps_misc_imm_offset): Likewise.
+ * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
+ option description.
+
2017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
Jiong Wang <jiong.wang@arm.com>
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index f39704d..e57877e 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -170,7 +170,7 @@ insert_rhv2 (unsigned long long insn,
const char ** errmsg)
{
if (value == 0x1E)
- *errmsg = _("Register R30 is a limm indicator");
+ *errmsg = _("register R30 is a limm indicator");
return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
}
@@ -189,7 +189,7 @@ insert_r0 (unsigned long long insn,
const char ** errmsg)
{
if (value != 0)
- *errmsg = _("Register must be R0");
+ *errmsg = _("register must be R0");
return insn;
}
@@ -207,7 +207,7 @@ insert_r1 (unsigned long long insn,
const char ** errmsg)
{
if (value != 1)
- *errmsg = _("Register must be R1");
+ *errmsg = _("register must be R1");
return insn;
}
@@ -224,7 +224,7 @@ insert_r2 (unsigned long long insn,
const char ** errmsg)
{
if (value != 2)
- *errmsg = _("Register must be R2");
+ *errmsg = _("register must be R2");
return insn;
}
@@ -241,7 +241,7 @@ insert_r3 (unsigned long long insn,
const char ** errmsg)
{
if (value != 3)
- *errmsg = _("Register must be R3");
+ *errmsg = _("register must be R3");
return insn;
}
@@ -258,7 +258,7 @@ insert_sp (unsigned long long insn,
const char ** errmsg)
{
if (value != 28)
- *errmsg = _("Register must be SP");
+ *errmsg = _("register must be SP");
return insn;
}
@@ -275,7 +275,7 @@ insert_gp (unsigned long long insn,
const char ** errmsg)
{
if (value != 26)
- *errmsg = _("Register must be GP");
+ *errmsg = _("register must be GP");
return insn;
}
@@ -292,7 +292,7 @@ insert_pcl (unsigned long long insn,
const char ** errmsg)
{
if (value != 63)
- *errmsg = _("Register must be PCL");
+ *errmsg = _("register must be PCL");
return insn;
}
@@ -309,7 +309,7 @@ insert_blink (unsigned long long insn,
const char ** errmsg)
{
if (value != 31)
- *errmsg = _("Register must be BLINK");
+ *errmsg = _("register must be BLINK");
return insn;
}
@@ -326,7 +326,7 @@ insert_ilink1 (unsigned long long insn,
const char ** errmsg)
{
if (value != 29)
- *errmsg = _("Register must be ILINK1");
+ *errmsg = _("register must be ILINK1");
return insn;
}
@@ -343,7 +343,7 @@ insert_ilink2 (unsigned long long insn,
const char ** errmsg)
{
if (value != 30)
- *errmsg = _("Register must be ILINK2");
+ *errmsg = _("register must be ILINK2");
return insn;
}
@@ -374,7 +374,7 @@ insert_ras (unsigned long long insn,
insn |= (value - 8);
break;
default:
- *errmsg = _("Register must be either r0-r3 or r12-r15");
+ *errmsg = _("register must be either r0-r3 or r12-r15");
break;
}
return insn;
@@ -412,7 +412,7 @@ insert_rbs (unsigned long long insn,
insn |= ((value - 8)) << 8;
break;
default:
- *errmsg = _("Register must be either r0-r3 or r12-r15");
+ *errmsg = _("register must be either r0-r3 or r12-r15");
break;
}
return insn;
@@ -450,7 +450,7 @@ insert_rcs (unsigned long long insn,
insn |= ((value - 8)) << 5;
break;
default:
- *errmsg = _("Register must be either r0-r3 or r12-r15");
+ *errmsg = _("register must be either r0-r3 or r12-r15");
break;
}
return insn;
@@ -501,7 +501,7 @@ insert_simm3s (unsigned long long insn,
tmp = 0x06;
break;
default:
- *errmsg = _("Accepted values are from -1 to 6");
+ *errmsg = _("accepted values are from -1 to 6");
break;
}
@@ -530,9 +530,9 @@ insert_rrange (unsigned long long insn,
int reg2 = value & 0xFFFF;
if (reg1 != 13)
- *errmsg = _("First register of the range should be r13");
+ *errmsg = _("first register of the range should be r13");
else if (reg2 < 13 || reg2 > 26)
- *errmsg = _("Last register of the range doesn't fit");
+ *errmsg = _("last register of the range doesn't fit");
else
insn |= ((reg2 - 12) & 0x0F) << 1;
return insn;
@@ -552,7 +552,7 @@ insert_r13el (unsigned long long insn,
{
if (value != 13)
{
- *errmsg = _("Invalid register number, should be fp");
+ *errmsg = _("invalid register number, should be fp");
return insn;
}
@@ -567,7 +567,7 @@ insert_fpel (unsigned long long insn,
{
if (value != 27)
{
- *errmsg = _("Invalid register number, should be fp");
+ *errmsg = _("invalid register number, should be fp");
return insn;
}
@@ -589,7 +589,7 @@ insert_blinkel (unsigned long long insn,
{
if (value != 31)
{
- *errmsg = _("Invalid register number, should be blink");
+ *errmsg = _("invalid register number, should be blink");
return insn;
}
@@ -611,7 +611,7 @@ insert_pclel (unsigned long long insn,
{
if (value != 63)
{
- *errmsg = _("Invalid register number, should be pcl");
+ *errmsg = _("invalid register number, should be pcl");
return insn;
}
@@ -715,7 +715,7 @@ insert_nps_3bit_reg_at_##OFFSET##_##NAME \
insn |= (value - 8) << (OFFSET); \
break; \
default: \
- *errmsg = _("Register must be either r0-r3 or r12-r15"); \
+ *errmsg = _("register must be either r0-r3 or r12-r15"); \
break; \
} \
return insn; \
@@ -763,7 +763,7 @@ insert_nps_bitop_size_2b (unsigned long long insn,
break;
default:
value = 0;
- *errmsg = _("Invalid size, should be 1, 2, 4, or 8");
+ *errmsg = _("invalid size, should be 1, 2, 4, or 8");
break;
}
@@ -874,7 +874,7 @@ insert_nps_imm_offset (unsigned long long insn,
value = value >> 4;
break;
default:
- *errmsg = _("Invalid position, should be 0, 16, 32, 48 or 64.");
+ *errmsg = _("invalid position, should be 0, 16, 32, 48 or 64.");
value = 0;
}
insn |= (value << 10);
@@ -908,7 +908,7 @@ insert_nps_imm_entry (unsigned long long insn,
value = 3;
break;
default:
- *errmsg = _("Invalid position, should be 16, 32, 64 or 128.");
+ *errmsg = _("invalid position, should be 16, 32, 64 or 128.");
value = 0;
}
insn |= (value << 2);
@@ -930,7 +930,7 @@ insert_nps_size_16bit (unsigned long long insn,
{
if ((value < 1) || (value > 64))
{
- *errmsg = _("Invalid size value must be on range 1-64.");
+ *errmsg = _("invalid size value must be on range 1-64.");
value = 0;
}
value = value & 0x3f;
@@ -961,7 +961,7 @@ insert_nps_##NAME##_pos (unsigned long long insn, \
value = value / 8; \
break; \
default: \
- *errmsg = _("Invalid position, should be 0, 8, 16, or 24"); \
+ *errmsg = _("invalid position, should be 0, 8, 16, or 24"); \
value = 0; \
} \
insn |= (value << SHIFT); \
@@ -986,7 +986,7 @@ insert_nps_##NAME (unsigned long long insn, \
{ \
if (value < LOWER || value > UPPER) \
{ \
- *errmsg = _("Invalid size, value must be " \
+ *errmsg = _("invalid size, value must be " \
#LOWER " to " #UPPER "."); \
return insn; \
} \
@@ -1122,7 +1122,7 @@ insert_nps_bitop_ins_ext (unsigned long long insn,
const char ** errmsg)
{
if (value < 0 || value > 28)
- *errmsg = _("Value must be in the range 0 to 28");
+ *errmsg = _("value must be in the range 0 to 28");
return insn | (value << 20);
}
@@ -1144,7 +1144,7 @@ insert_nps_##NAME (unsigned long long insn, \
const char ** errmsg) \
{ \
if (value < 1 || value > UPPER) \
- *errmsg = _("Value must be in the range 1 to " #UPPER); \
+ *errmsg = _("value must be in the range 1 to " #UPPER); \
if (value == UPPER) \
value = 0; \
return insn | (value << SHIFT); \
@@ -1174,9 +1174,9 @@ insert_nps_min_hofs (unsigned long long insn,
const char ** errmsg)
{
if (value < 0 || value > 240)
- *errmsg = _("Value must be in the range 0 to 240");
+ *errmsg = _("value must be in the range 0 to 240");
if ((value % 16) != 0)
- *errmsg = _("Value must be a multiple of 16");
+ *errmsg = _("value must be a multiple of 16");
value = value / 16;
return insn | (value << 6);
}
@@ -1196,7 +1196,7 @@ insert_nps_##NAME (unsigned long long insn, \
const char ** errmsg) \
{ \
if (value != ARC_NPS400_ADDRTYPE_##VALUE) \
- *errmsg = _("Invalid address type for operand"); \
+ *errmsg = _("invalid address type for operand"); \
return insn; \
} \
\
@@ -1230,7 +1230,7 @@ insert_nps_rbdouble_64 (unsigned long long insn,
const char ** errmsg)
{
if (value < 0 || value > 31)
- *errmsg = _("Value must be in the range 0 to 31");
+ *errmsg = _("value must be in the range 0 to 31");
return insn | (value << 43) | (value << 48);
}
@@ -1255,7 +1255,7 @@ insert_nps_misc_imm_offset (unsigned long long insn,
{
if (value & 0x3)
{
- *errmsg = _("Invalid position, should be 0,4, 8,...124.");
+ *errmsg = _("invalid position, should be one of: 0,4,8,...124.");
value = 0;
}
insn |= (value << 6);
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 2dc76de..17d042a 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -498,7 +498,7 @@ The following RISC-V-specific disassembler options are supported for use\n\
with the -M switch (multiple options should be separated by commas):\n"));
fprintf (stream, _("\n\
- numeric Print numeric reigster names, rather than ABI names.\n"));
+ numeric Print numeric register names, rather than ABI names.\n"));
fprintf (stream, _("\n\
no-aliases Disassemble only into canonical instructions, rather\n\
generated by cgit v1.1 at 2024-11-24 02:56:23 +0000