diff options
55 files changed, 7428 insertions, 27 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog index 705ee35..e9d27c7 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,20 @@ +2009-08-06 Michael Eager <eager@eagercon.com> + + * Makefile.am: Add cpu-microblaze.{lo,c}, elf32-microblaze.{lo,c}. + * Makefile.in: Regenerate. + * archures.c: Add bfd_arch_microblaze. + * bfd-in2.h: Regenerate. + * config.bfd: Add microblaze target. + * configure.in: Add bfd_elf32_microblaze_vec target. + * configure: Regenerate. + * cpu-microblaze.c: New. + * elf32-microblaze.c: New. + * libbfd-in.h: Add prototype _bfd_dwarf2_fixup_section_debug_loc(). + * libbfd.h: Regenerate. + * reloc.c: Add MICROBLAZE relocations. + * section.c: Add struct relax_table and relax_count to section. + * targets.c: Add bfd_elf32_microblaze_vec. + 2009-08-06 Jakub Jelinek <jakub@redhat.com> Alan Modra <amodra@bigpond.net.au> diff --git a/bfd/Makefile.am b/bfd/Makefile.am index 73ff953..20fcf5a 100644 --- a/bfd/Makefile.am +++ b/bfd/Makefile.am @@ -101,6 +101,7 @@ ALL_MACHINES = \ cpu-maxq.lo \ cpu-mcore.lo \ cpu-mep.lo \ + cpu-microblaze.lo \ cpu-mips.lo \ cpu-mmix.lo \ cpu-moxie.lo \ @@ -171,6 +172,7 @@ ALL_MACHINES_CFILES = \ cpu-maxq.c \ cpu-mcore.c \ cpu-mep.c \ + cpu-microblaze.c \ cpu-mips.c \ cpu-mmix.c \ cpu-moxie.c \ @@ -291,6 +293,7 @@ BFD32_BACKENDS = \ elf32-m88k.lo \ elf32-mcore.lo \ elf32-mep.lo \ + elf32-microblaze.lo \ elf32-mips.lo \ elf32-moxie.lo \ elf32-msp430.lo \ @@ -474,6 +477,7 @@ BFD32_BACKENDS_CFILES = \ elf32-m88k.c \ elf32-mcore.c \ elf32-mep.c \ + elf32-microblaze.c \ elf32-mips.c \ elf32-moxie.c \ elf32-msp430.c \ @@ -1387,6 +1391,10 @@ cpu-mep.lo: \ cpu-mep.c \ $(INCDIR)/filenames.h \ $(INCDIR)/hashtab.h +cpu-microblaze.lo: \ + cpu-microblaze.c $\ + $(INCDIR)/filenames.h \ + $(INCDIR)/hashtab.h cpu-mips.lo: \ cpu-mips.c \ $(INCDIR)/filenames.h \ @@ -2844,6 +2852,17 @@ elflink.lo: \ $(INCDIR)/objalloc.h \ $(INCDIR)/safe-ctype.h \ elf-bfd.h +elf32-microblaze.lo: \ + elf32-microblaze.c \ + $(INCDIR)/filenames.h \ + $(INCDIR)/bfdlink.h \ + genlink.h \ + elf-bfd.h \ + $(INCDIR)/elf/common.h \ + $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h \ + $(INCDIR)/elf/reloc-macros.h \ + elf32-target.h elfxx-mips.lo: \ elfxx-mips.c \ $(INCDIR)/bfdlink.h \ diff --git a/bfd/Makefile.in b/bfd/Makefile.in index 65f94e8..0bee7d3 100644 --- a/bfd/Makefile.in +++ b/bfd/Makefile.in @@ -371,6 +371,7 @@ ALL_MACHINES = \ cpu-maxq.lo \ cpu-mcore.lo \ cpu-mep.lo \ + cpu-microblaze.lo \ cpu-mips.lo \ cpu-mmix.lo \ cpu-moxie.lo \ @@ -441,6 +442,7 @@ ALL_MACHINES_CFILES = \ cpu-maxq.c \ cpu-mcore.c \ cpu-mep.c \ + cpu-microblaze.c \ cpu-mips.c \ cpu-mmix.c \ cpu-moxie.c \ @@ -562,6 +564,7 @@ BFD32_BACKENDS = \ elf32-m88k.lo \ elf32-mcore.lo \ elf32-mep.lo \ + elf32-microblaze.lo \ elf32-mips.lo \ elf32-moxie.lo \ elf32-msp430.lo \ @@ -745,6 +748,7 @@ BFD32_BACKENDS_CFILES = \ elf32-m88k.c \ elf32-mcore.c \ elf32-mep.c \ + elf32-microblaze.c \ elf32-mips.c \ elf32-moxie.c \ elf32-msp430.c \ @@ -1988,6 +1992,10 @@ cpu-mep.lo: \ cpu-mep.c \ $(INCDIR)/filenames.h \ $(INCDIR)/hashtab.h +cpu-microblaze.lo: \ + cpu-microblaze.c $\ + $(INCDIR)/filenames.h \ + $(INCDIR)/hashtab.h cpu-mips.lo: \ cpu-mips.c \ $(INCDIR)/filenames.h \ @@ -3445,6 +3453,17 @@ elflink.lo: \ $(INCDIR)/objalloc.h \ $(INCDIR)/safe-ctype.h \ elf-bfd.h +elf32-microblaze.lo: \ + elf32-microblaze.c \ + $(INCDIR)/filenames.h \ + $(INCDIR)/bfdlink.h \ + genlink.h \ + elf-bfd.h \ + $(INCDIR)/elf/common.h \ + $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h \ + $(INCDIR)/elf/reloc-macros.h \ + elf32-target.h elfxx-mips.lo: \ elfxx-mips.c \ $(INCDIR)/bfdlink.h \ diff --git a/bfd/archures.c b/bfd/archures.c index ad52d00..81d8ff6 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -422,6 +422,7 @@ DESCRIPTION .#define bfd_mach_r800 11 {* R800: successor with multiplication. *} . bfd_arch_lm32, {* Lattice Mico32 *} .#define bfd_mach_lm32 1 +. bfd_arch_microblaze,{* Xilinx MicroBlaze. *} . bfd_arch_last . }; */ @@ -496,6 +497,7 @@ extern const bfd_arch_info_type bfd_maxq_arch; extern const bfd_arch_info_type bfd_mcore_arch; extern const bfd_arch_info_type bfd_mep_arch; extern const bfd_arch_info_type bfd_mips_arch; +extern const bfd_arch_info_type bfd_microblaze_arch; extern const bfd_arch_info_type bfd_mmix_arch; extern const bfd_arch_info_type bfd_mn10200_arch; extern const bfd_arch_info_type bfd_mn10300_arch; @@ -570,6 +572,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] = &bfd_maxq_arch, &bfd_mcore_arch, &bfd_mep_arch, + &bfd_microblaze_arch, &bfd_mips_arch, &bfd_mmix_arch, &bfd_mn10200_arch, diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index d957610..adaba63 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -1405,6 +1405,13 @@ typedef struct bfd_section section size calculated on a previous linker relaxation pass. */ bfd_size_type rawsize; + /* Relaxation table. */ + struct relax_table *relax; + + /* Count of used relaxation table entries. */ + int relax_count; + + /* If this section is going to be output, then this value is the offset in *bytes* into the output section of the first byte in the input section (byte ==> smallest addressable unit on the @@ -1494,6 +1501,17 @@ typedef struct bfd_section } map_head, map_tail; } asection; +/* Relax table contains information about instructions which can + be removed by relaxation -- replacing a long address with a + short address. */ +struct relax_table { + /* Address where bytes may be deleted. */ + bfd_vma addr; + + /* Number of bytes to be deleted. */ + int size; +}; + /* These sections are global, and are managed by BFD. The application and target back end are not permitted to change the values in these sections. New code should use the section_ptr macros rather @@ -1629,8 +1647,8 @@ extern asection bfd_ind_section; /* has_tls_get_addr_call, has_gp_reloc, need_finalize_relax, */ \ 0, 0, 0, \ \ - /* reloc_done, vma, lma, size, rawsize */ \ - 0, 0, 0, 0, 0, \ + /* reloc_done, vma, lma, size, rawsize, relax, relax_count, */ \ + 0, 0, 0, 0, 0, 0, 0, \ \ /* output_offset, output_section, alignment_power, */ \ 0, (struct bfd_section *) &SEC, 0, \ @@ -2071,6 +2089,7 @@ enum bfd_architecture #define bfd_mach_r800 11 /* R800: successor with multiplication. */ bfd_arch_lm32, /* Lattice Mico32 */ #define bfd_mach_lm32 1 + bfd_arch_microblaze,/* Xilinx MicroBlaze. */ bfd_arch_last }; @@ -4513,6 +4532,59 @@ BFD_RELOC_MACH_O_PAIR. */ /* Mach-O generic relocations. */ BFD_RELOC_MACH_O_PAIR, + +/* This is a 32 bit reloc for the microblaze that stores the +low 16 bits of a value */ + BFD_RELOC_MICROBLAZE_32_LO, + +/* This is a 32 bit pc-relative reloc for the microblaze that +stores the low 16 bits of a value */ + BFD_RELOC_MICROBLAZE_32_LO_PCREL, + +/* This is a 32 bit reloc for the microblaze that stores a +value relative to the read-only small data area anchor */ + BFD_RELOC_MICROBLAZE_32_ROSDA, + +/* This is a 32 bit reloc for the microblaze that stores a +value relative to the read-write small data area anchor */ + BFD_RELOC_MICROBLAZE_32_RWSDA, + +/* This is a 32 bit reloc for the microblaze to handle +expressions of the form "Symbol Op Symbol" */ + BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM, + +/* This is a 64 bit reloc that stores the 32 bit pc relative +value in two words (with an imm instruction). No relocation is +done here - only used for relaxing */ + BFD_RELOC_MICROBLAZE_64_NONE, + +/* This is a 64 bit reloc that stores the 32 bit pc relative +value in two words (with an imm instruction). The relocation is +PC-relative GOT offset */ + BFD_RELOC_MICROBLAZE_64_GOTPC, + +/* This is a 64 bit reloc that stores the 32 bit pc relative +value in two words (with an imm instruction). The relocation is +GOT offset */ + BFD_RELOC_MICROBLAZE_64_GOT, + +/* This is a 64 bit reloc that stores the 32 bit pc relative +value in two words (with an imm instruction). The relocation is +PC-relative offset into PLT */ + BFD_RELOC_MICROBLAZE_64_PLT, + +/* This is a 64 bit reloc that stores the 32 bit GOT relative +value in two words (with an imm instruction). The relocation is +relative offset from _GLOBAL_OFFSET_TABLE_ */ + BFD_RELOC_MICROBLAZE_64_GOTOFF, + +/* This is a 32 bit reloc that stores the 32 bit GOT relative +value in a word. The relocation is relative offset from */ + BFD_RELOC_MICROBLAZE_32_GOTOFF, + +/* This is used to tell the dynamic linker to copy the value out of +the dynamic object into the runtime process image. */ + BFD_RELOC_MICROBLAZE_COPY, BFD_RELOC_UNUSED }; typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; reloc_howto_type *bfd_reloc_type_lookup diff --git a/bfd/config.bfd b/bfd/config.bfd index 029fa34..e340251 100644 --- a/bfd/config.bfd +++ b/bfd/config.bfd @@ -91,6 +91,7 @@ m6812*|m68hc12*) targ_archs="bfd_m68hc12_arch bfd_m68hc11_arch" ;; m68*) targ_archs=bfd_m68k_arch ;; m88*) targ_archs=bfd_m88k_arch ;; maxq*) targ_archs=bfd_maxq_arch ;; +microblaze*) targ_archs=bfd_microblaze_arch ;; mips*) targ_archs=bfd_mips_arch ;; or32*) targ_archs=bfd_or32_arch ;; pdp11*) targ_archs=bfd_pdp11_arch ;; @@ -899,6 +900,10 @@ case "${targ}" in targ_selvecs=bfd_elf32_mep_little_vec ;; + microblaze*-*) + targ_defvec=bfd_elf32_microblaze_vec + ;; + mips*-big-*) targ_defvec=ecoff_big_vec targ_selvecs=ecoff_little_vec diff --git a/bfd/configure b/bfd/configure index 052631f..9871cbe 100755 --- a/bfd/configure +++ b/bfd/configure @@ -21247,6 +21247,7 @@ do bfd_elf32_mcore_little_vec) tb="$tb elf32-mcore.lo elf32.lo $elf" ;; bfd_elf32_mep_vec) tb="$tb elf32-mep.lo elf32.lo $elf" ;; bfd_elf32_mep_little_vec) tb="$tb elf32-mep.lo elf32.lo $elf" ;; + bfd_elf32_microblaze_vec) tb="$tb elf32-microblaze.lo elf32.lo $elf" ;; bfd_elf32_mn10200_vec) tb="$tb elf-m10200.lo elf32.lo $elf" ;; bfd_elf32_mn10300_vec) tb="$tb elf-m10300.lo elf32.lo $elf" ;; bfd_elf32_mt_vec) tb="$tb elf32-mt.lo elf32.lo $elf" ;; diff --git a/bfd/configure.in b/bfd/configure.in index 4325200..7396f19 100644 --- a/bfd/configure.in +++ b/bfd/configure.in @@ -751,6 +751,7 @@ do bfd_elf32_mcore_little_vec) tb="$tb elf32-mcore.lo elf32.lo $elf" ;; bfd_elf32_mep_vec) tb="$tb elf32-mep.lo elf32.lo $elf" ;; bfd_elf32_mep_little_vec) tb="$tb elf32-mep.lo elf32.lo $elf" ;; + bfd_elf32_microblaze_vec) tb="$tb elf32-microblaze.lo elf32.lo $elf" ;; bfd_elf32_mn10200_vec) tb="$tb elf-m10200.lo elf32.lo $elf" ;; bfd_elf32_mn10300_vec) tb="$tb elf-m10300.lo elf32.lo $elf" ;; bfd_elf32_mt_vec) tb="$tb elf32-mt.lo elf32.lo $elf" ;; diff --git a/bfd/cpu-microblaze.c b/bfd/cpu-microblaze.c new file mode 100644 index 0000000..45a4a2b --- /dev/null +++ b/bfd/cpu-microblaze.c @@ -0,0 +1,40 @@ +/* BFD Xilinx MicroBlaze architecture definition + + Copyright 2009 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "bfd.h" +#include "sysdep.h" +#include "libbfd.h" + +const bfd_arch_info_type bfd_microblaze_arch = +{ + 32, /* 32 bits in a word. */ + 32, /* 32 bits in an address. */ + 8, /* 8 bits in a byte. */ + bfd_arch_microblaze, /* Architecture. */ + 0, /* Machine number - 0 for now. */ + "microblaze", /* Architecture name. */ + "MicroBlaze", /* Printable name. */ + 3, /* Section align power. */ + TRUE, /* Is this the default architecture ? */ + bfd_default_compatible, /* Architecture comparison function. */ + bfd_default_scan, /* String to architecture conversion. */ + NULL /* Next in list. */ +}; diff --git a/bfd/ecoff.c b/bfd/ecoff.c index 4d27740..9ff6a20 100644 --- a/bfd/ecoff.c +++ b/bfd/ecoff.c @@ -62,8 +62,8 @@ static asection bfd_debug_section = 0, 0, 0, 0, /* has_tls_get_addr_call, has_gp_reloc, need_finalize_relax, */ 0, 0, 0, - /* reloc_done, vma, lma, size, rawsize, */ - 0, 0, 0, 0, 0, + /* reloc_done, vma, lma, size, rawsize, relax, relax_count, */ + 0, 0, 0, 0, 0, 0, 0, /* output_offset, output_section, alignment_power, */ 0, NULL, 0, /* relocation, orelocation, reloc_count, filepos, rel_filepos, */ diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c new file mode 100644 index 0000000..5b1a71b --- /dev/null +++ b/bfd/elf32-microblaze.c @@ -0,0 +1,3058 @@ +/* Xilinx MicroBlaze-specific support for 32-bit ELF + + Copyright 2009 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the + Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. */ + + +int dbg = 0; + +#include "bfd.h" +#include "sysdep.h" +#include "bfdlink.h" +#include "libbfd.h" +#include "elf-bfd.h" +#include "elf/microblaze.h" +#include <assert.h> + +#define USE_RELA /* Only USE_REL is actually significant, but this is + here are a reminder... */ +#define INST_WORD_SIZE 4 + +static int ro_small_data_pointer = 0; +static int rw_small_data_pointer = 0; + +static reloc_howto_type * microblaze_elf_howto_table [(int) R_MICROBLAZE_max]; + +static reloc_howto_type microblaze_elf_howto_raw[] = +{ + /* This reloc does nothing. */ + HOWTO (R_MICROBLAZE_NONE, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 32, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_bitfield, /* Complain on overflow. */ + NULL, /* Special Function. */ + "R_MICROBLAZE_NONE", /* Name. */ + FALSE, /* Partial Inplace. */ + 0, /* Source Mask. */ + 0, /* Dest Mask. */ + FALSE), /* PC relative offset? */ + + /* A standard 32 bit relocation. */ + HOWTO (R_MICROBLAZE_32, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 32, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_bitfield, /* Complain on overflow. */ + bfd_elf_generic_reloc,/* Special Function. */ + "R_MICROBLAZE_32", /* Name. */ + FALSE, /* Partial Inplace. */ + 0, /* Source Mask. */ + 0xffffffff, /* Dest Mask. */ + FALSE), /* PC relative offset? */ + + /* A standard PCREL 32 bit relocation. */ + HOWTO (R_MICROBLAZE_32_PCREL,/* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 32, /* Bitsize. */ + TRUE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_bitfield, /* Complain on overflow. */ + bfd_elf_generic_reloc,/* Special Function. */ + "R_MICROBLAZE_32_PCREL", /* Name. */ + TRUE, /* Partial Inplace. */ + 0, /* Source Mask. */ + 0xffffffff, /* Dest Mask. */ + TRUE), /* PC relative offset? */ + + /* A 64 bit PCREL relocation. Table-entry not really used. */ + HOWTO (R_MICROBLAZE_64_PCREL,/* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + TRUE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain on overflow. */ + bfd_elf_generic_reloc,/* Special Function. */ + "R_MICROBLAZE_64_PCREL", /* Name. */ + FALSE, /* Partial Inplace. */ + 0, /* Source Mask. */ + 0x0000ffff, /* Dest Mask. */ + TRUE), /* PC relative offset? */ + + /* The low half of a PCREL 32 bit relocation. */ + HOWTO (R_MICROBLAZE_32_PCREL_LO, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + TRUE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_signed, /* Complain on overflow. */ + bfd_elf_generic_reloc, /* Special Function. */ + "R_MICROBLAZE_32_PCREL_LO", /* Name. */ + FALSE, /* Partial Inplace. */ + 0, /* Source Mask. */ + 0x0000ffff, /* Dest Mask. */ + TRUE), /* PC relative offset? */ + + /* A 64 bit relocation. Table entry not really used. */ + HOWTO (R_MICROBLAZE_64, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain on overflow. */ + bfd_elf_generic_reloc,/* Special Function. */ + "R_MICROBLAZE_64", /* Name. */ + FALSE, /* Partial Inplace. */ + 0, /* Source Mask. */ + 0x0000ffff, /* Dest Mask. */ + FALSE), /* PC relative offset? */ + + /* The low half of a 32 bit relocation. */ + HOWTO (R_MICROBLAZE_32_LO, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_signed, /* Complain on overflow. */ + bfd_elf_generic_reloc,/* Special Function. */ + "R_MICROBLAZE_32_LO", /* Name. */ + FALSE, /* Partial Inplace. */ + 0, /* Source Mask. */ + 0x0000ffff, /* Dest Mask. */ + FALSE), /* PC relative offset? */ + + /* Read-only small data section relocation. */ + HOWTO (R_MICROBLAZE_SRO32, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_bitfield, /* Complain on overflow. */ + bfd_elf_generic_reloc,/* Special Function. */ + "R_MICROBLAZE_SRO32", /* Name. */ + FALSE, /* Partial Inplace. */ + 0, /* Source Mask. */ + 0x0000ffff, /* Dest Mask. */ + FALSE), /* PC relative offset? */ + + /* Read-write small data area relocation. */ + HOWTO (R_MICROBLAZE_SRW32, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_bitfield, /* Complain on overflow. */ + bfd_elf_generic_reloc,/* Special Function. */ + "R_MICROBLAZE_SRW32", /* Name. */ + FALSE, /* Partial Inplace. */ + 0, /* Source Mask. */ + 0x0000ffff, /* Dest Mask. */ + FALSE), /* PC relative offset? */ + + /* This reloc does nothing. Used for relaxation. */ + HOWTO (R_MICROBLAZE_64_NONE, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 32, /* Bitsize. */ + TRUE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_bitfield, /* Complain on overflow. */ + NULL, /* Special Function. */ + "R_MICROBLAZE_64_NONE",/* Name. */ + FALSE, /* Partial Inplace. */ + 0, /* Source Mask. */ + 0, /* Dest Mask. */ + FALSE), /* PC relative offset? */ + + /* Symbol Op Symbol relocation. */ + HOWTO (R_MICROBLAZE_32_SYM_OP_SYM, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 32, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_bitfield, /* Complain on overflow. */ + bfd_elf_generic_reloc,/* Special Function. */ + "R_MICROBLAZE_32_SYM_OP_SYM", /* Name. */ + FALSE, /* Partial Inplace. */ + 0, /* Source Mask. */ + 0xffffffff, /* Dest Mask. */ + FALSE), /* PC relative offset? */ + + /* GNU extension to record C++ vtable hierarchy. */ + HOWTO (R_MICROBLAZE_GNU_VTINHERIT, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 0, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont,/* Complain on overflow. */ + NULL, /* Special Function. */ + "R_MICROBLAZE_GNU_VTINHERIT", /* Name. */ + FALSE, /* Partial Inplace. */ + 0, /* Source Mask. */ + 0, /* Dest Mask. */ + FALSE), /* PC relative offset? */ + + /* GNU extension to record C++ vtable member usage. */ + HOWTO (R_MICROBLAZE_GNU_VTENTRY, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 0, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont,/* Complain on overflow. */ + _bfd_elf_rel_vtable_reloc_fn, /* Special Function. */ + "R_MICROBLAZE_GNU_VTENTRY", /* Name. */ + FALSE, /* Partial Inplace. */ + 0, /* Source Mask. */ + 0, /* Dest Mask. */ + FALSE), /* PC relative offset? */ + + /* A 64 bit GOTPC relocation. Table-entry not really used. */ + HOWTO (R_MICROBLAZE_GOTPC_64, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + TRUE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain on overflow. */ + bfd_elf_generic_reloc, /* Special Function. */ + "R_MICROBLAZE_GOTPC_64", /* Name. */ + FALSE, /* Partial Inplace. */ + 0, /* Source Mask. */ + 0x0000ffff, /* Dest Mask. */ + TRUE), /* PC relative offset? */ + + /* A 64 bit GOT relocation. Table-entry not really used. */ + HOWTO (R_MICROBLAZE_GOT_64, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain on overflow. */ + bfd_elf_generic_reloc,/* Special Function. */ + "R_MICROBLAZE_GOT_64",/* Name. */ + FALSE, /* Partial Inplace. */ + 0, /* Source Mask. */ + 0x0000ffff, /* Dest Mask. */ + FALSE), /* PC relative offset? */ + + /* A 64 bit PLT relocation. Table-entry not really used. */ + HOWTO (R_MICROBLAZE_PLT_64, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + TRUE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain on overflow. */ + bfd_elf_generic_reloc,/* Special Function. */ + "R_MICROBLAZE_PLT_64",/* Name. */ + FALSE, /* Partial Inplace. */ + 0, /* Source Mask. */ + 0x0000ffff, /* Dest Mask. */ + TRUE), /* PC relative offset? */ + + /* Table-entry not really used. */ + HOWTO (R_MICROBLAZE_REL, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + TRUE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain on overflow. */ + bfd_elf_generic_reloc,/* Special Function. */ + "R_MICROBLAZE_REL", /* Name. */ + FALSE, /* Partial Inplace. */ + 0, /* Source Mask. */ + 0x0000ffff, /* Dest Mask. */ + TRUE), /* PC relative offset? */ + + /* Table-entry not really used. */ + HOWTO (R_MICROBLAZE_JUMP_SLOT,/* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + TRUE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain on overflow. */ + bfd_elf_generic_reloc,/* Special Function. */ + "R_MICROBLAZE_JUMP_SLOT", /* Name. */ + FALSE, /* Partial Inplace. */ + 0, /* Source Mask. */ + 0x0000ffff, /* Dest Mask. */ + TRUE), /* PC relative offset? */ + + /* Table-entry not really used. */ + HOWTO (R_MICROBLAZE_GLOB_DAT,/* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + TRUE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain on overflow. */ + bfd_elf_generic_reloc,/* Special Function. */ + "R_MICROBLAZE_GLOB_DAT", /* Name. */ + FALSE, /* Partial Inplace. */ + 0, /* Source Mask. */ + 0x0000ffff, /* Dest Mask. */ + TRUE), /* PC relative offset? */ + + /* A 64 bit GOT relative relocation. Table-entry not really used. */ + HOWTO (R_MICROBLAZE_GOTOFF_64, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain on overflow. */ + bfd_elf_generic_reloc,/* Special Function. */ + "R_MICROBLAZE_GOTOFF_64", /* Name. */ + FALSE, /* Partial Inplace. */ + 0, /* Source Mask. */ + 0x0000ffff, /* Dest Mask. */ + FALSE), /* PC relative offset? */ + + /* A 32 bit GOT relative relocation. Table-entry not really used. */ + HOWTO (R_MICROBLAZE_GOTOFF_32, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain on overflow. */ + bfd_elf_generic_reloc, /* Special Function. */ + "R_MICROBLAZE_GOTOFF_32", /* Name. */ + FALSE, /* Partial Inplace. */ + 0, /* Source Mask. */ + 0x0000ffff, /* Dest Mask. */ + FALSE), /* PC relative offset? */ + + /* COPY relocation. Table-entry not really used. */ + HOWTO (R_MICROBLAZE_COPY, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain on overflow. */ + bfd_elf_generic_reloc,/* Special Function. */ + "R_MICROBLAZE_COPY", /* Name. */ + FALSE, /* Partial Inplace. */ + 0, /* Source Mask. */ + 0x0000ffff, /* Dest Mask. */ + FALSE), /* PC relative offset? */ +}; + +#ifndef NUM_ELEM +#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0]) +#endif + +/* Initialize the microblaze_elf_howto_table, so that linear accesses can be done. */ + +static void +microblaze_elf_howto_init (void) +{ + unsigned int i; + + for (i = NUM_ELEM (microblaze_elf_howto_raw); i--;) + { + unsigned int type; + + type = microblaze_elf_howto_raw[i].type; + + BFD_ASSERT (type < NUM_ELEM (microblaze_elf_howto_table)); + + microblaze_elf_howto_table [type] = & microblaze_elf_howto_raw [i]; + } +} + +static reloc_howto_type * +microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, + bfd_reloc_code_real_type code) +{ + enum elf_microblaze_reloc_type microblaze_reloc = R_MICROBLAZE_NONE; + + switch (code) + { + case BFD_RELOC_NONE: + microblaze_reloc = R_MICROBLAZE_NONE; + break; + case BFD_RELOC_MICROBLAZE_64_NONE: + microblaze_reloc = R_MICROBLAZE_64_NONE; + break; + case BFD_RELOC_32: + microblaze_reloc = R_MICROBLAZE_32; + break; + /* RVA is treated the same as 32 */ + case BFD_RELOC_RVA: + microblaze_reloc = R_MICROBLAZE_32; + break; + case BFD_RELOC_32_PCREL: + microblaze_reloc = R_MICROBLAZE_32_PCREL; + break; + case BFD_RELOC_64_PCREL: + microblaze_reloc = R_MICROBLAZE_64_PCREL; + break; + case BFD_RELOC_MICROBLAZE_32_LO_PCREL: + microblaze_reloc = R_MICROBLAZE_32_PCREL_LO; + break; + case BFD_RELOC_64: + microblaze_reloc = R_MICROBLAZE_64; + break; + case BFD_RELOC_MICROBLAZE_32_LO: + microblaze_reloc = R_MICROBLAZE_32_LO; + break; + case BFD_RELOC_MICROBLAZE_32_ROSDA: + microblaze_reloc = R_MICROBLAZE_SRO32; + break; + case BFD_RELOC_MICROBLAZE_32_RWSDA: + microblaze_reloc = R_MICROBLAZE_SRW32; + break; + case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM: + microblaze_reloc = R_MICROBLAZE_32_SYM_OP_SYM; + break; + case BFD_RELOC_VTABLE_INHERIT: + microblaze_reloc = R_MICROBLAZE_GNU_VTINHERIT; + break; + case BFD_RELOC_VTABLE_ENTRY: + microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY; + break; + case BFD_RELOC_MICROBLAZE_64_GOTPC: + microblaze_reloc = R_MICROBLAZE_GOTPC_64; + break; + case BFD_RELOC_MICROBLAZE_64_GOT: + microblaze_reloc = R_MICROBLAZE_GOT_64; + break; + case BFD_RELOC_MICROBLAZE_64_PLT: + microblaze_reloc = R_MICROBLAZE_PLT_64; + break; + case BFD_RELOC_MICROBLAZE_64_GOTOFF: + microblaze_reloc = R_MICROBLAZE_GOTOFF_64; + break; + case BFD_RELOC_MICROBLAZE_32_GOTOFF: + microblaze_reloc = R_MICROBLAZE_GOTOFF_32; + break; + case BFD_RELOC_MICROBLAZE_COPY: + microblaze_reloc = R_MICROBLAZE_COPY; + break; + default: + return (reloc_howto_type *) NULL; + } + + if (!microblaze_elf_howto_table [R_MICROBLAZE_32]) + /* Initialize howto table if needed. */ + microblaze_elf_howto_init (); + + return microblaze_elf_howto_table [(int) microblaze_reloc]; +}; + +static reloc_howto_type * +microblaze_elf_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, + const char *r_name) +{ + unsigned int i; + + for (i = 0; i < NUM_ELEM (microblaze_elf_howto_raw); i++) + if (microblaze_elf_howto_raw[i].name != NULL + && strcasecmp (microblaze_elf_howto_raw[i].name, r_name) == 0) + return µblaze_elf_howto_raw[i]; + + return NULL; +} + +/* Set the howto pointer for a RCE ELF reloc. */ + +static void +microblaze_elf_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, + arelent * cache_ptr, + Elf_Internal_Rela * dst) +{ + if (!microblaze_elf_howto_table [R_MICROBLAZE_32]) + /* Initialize howto table if needed. */ + microblaze_elf_howto_init (); + + BFD_ASSERT (ELF32_R_TYPE (dst->r_info) < (unsigned int) R_MICROBLAZE_max); + + cache_ptr->howto = microblaze_elf_howto_table [ELF32_R_TYPE (dst->r_info)]; +} + +/* Microblaze ELF local labels start with 'L.' or '$L', not '.L'. */ + +static bfd_boolean +microblaze_elf_is_local_label_name (bfd *abfd, const char *name) +{ + if (name[0] == 'L' && name[1] == '.') + return TRUE; + + if (name[0] == '$' && name[1] == 'L') + return TRUE; + + /* With gcc, the labels go back to starting with '.', so we accept + the generic ELF local label syntax as well. */ + return _bfd_elf_is_local_label_name (abfd, name); +} + +/* The microblaze linker (like many others) needs to keep track of + the number of relocs that it decides to copy as dynamic relocs in + check_relocs for each symbol. This is so that it can later discard + them if they are found to be unnecessary. We store the information + in a field extending the regular ELF linker hash table. */ + +struct elf32_mb_dyn_relocs +{ + struct elf32_mb_dyn_relocs *next; + + /* The input section of the reloc. */ + asection *sec; + + /* Total number of relocs copied for the input section. */ + bfd_size_type count; + + /* Number of pc-relative relocs copied for the input section. */ + bfd_size_type pc_count; +}; + +/* ELF linker hash entry. */ + +struct elf32_mb_link_hash_entry +{ + struct elf_link_hash_entry elf; + + /* Track dynamic relocs copied for this symbol. */ + struct elf32_mb_dyn_relocs *dyn_relocs; + +}; + +#define elf32_mb_hash_entry(ent) ((struct elf32_mb_link_hash_entry *)(ent)) + +/* ELF linker hash table. */ + +struct elf32_mb_link_hash_table +{ + struct elf_link_hash_table elf; + + /* Short-cuts to get to dynamic linker sections. */ + asection *sgot; + asection *sgotplt; + asection *srelgot; + asection *splt; + asection *srelplt; + asection *sdynbss; + asection *srelbss; + + /* Small local sym to section mapping cache. */ + struct sym_cache sym_sec; +}; + +/* Get the ELF linker hash table from a link_info structure. */ + +#define elf32_mb_hash_table(p) \ + ((struct elf32_mb_link_hash_table *) ((p)->hash)) + +/* Create an entry in a microblaze ELF linker hash table. */ + +static struct bfd_hash_entry * +link_hash_newfunc (struct bfd_hash_entry *entry, + struct bfd_hash_table *table, + const char *string) +{ + /* Allocate the structure if it has not already been allocated by a + subclass. */ + if (entry == NULL) + { + entry = bfd_hash_allocate (table, + sizeof (struct elf32_mb_link_hash_entry)); + if (entry == NULL) + return entry; + } + + /* Call the allocation method of the superclass. */ + entry = _bfd_elf_link_hash_newfunc (entry, table, string); + if (entry != NULL) + { + struct elf32_mb_link_hash_entry *eh; + + eh = (struct elf32_mb_link_hash_entry *) entry; + eh->dyn_relocs = NULL; + } + + return entry; +} + +/* Create a mb ELF linker hash table. */ + +static struct bfd_link_hash_table * +microblaze_elf_link_hash_table_create (bfd *abfd) +{ + struct elf32_mb_link_hash_table *ret; + bfd_size_type amt = sizeof (struct elf32_mb_link_hash_table); + + ret = (struct elf32_mb_link_hash_table *) bfd_zmalloc (amt); + if (ret == NULL) + return NULL; + + if (!_bfd_elf_link_hash_table_init (&ret->elf, abfd, link_hash_newfunc, + sizeof (struct elf32_mb_link_hash_entry))) + { + free (ret); + return NULL; + } + + return &ret->elf.root; +} + +/* Set the values of the small data pointers. */ + +static void +microblaze_elf_final_sdp (struct bfd_link_info *info) +{ + struct bfd_link_hash_entry *h; + + h = bfd_link_hash_lookup (info->hash, RO_SDA_ANCHOR_NAME, FALSE, FALSE, TRUE); + if (h != (struct bfd_link_hash_entry *) NULL + && h->type == bfd_link_hash_defined) + ro_small_data_pointer = (h->u.def.value + + h->u.def.section->output_section->vma + + h->u.def.section->output_offset); + + h = bfd_link_hash_lookup (info->hash, RW_SDA_ANCHOR_NAME, FALSE, FALSE, TRUE); + if (h != (struct bfd_link_hash_entry *) NULL + && h->type == bfd_link_hash_defined) + rw_small_data_pointer = (h->u.def.value + + h->u.def.section->output_section->vma + + h->u.def.section->output_offset); +} + +/* This code is taken from elf32-m32r.c + There is some attempt to make this function usable for many architectures, + both USE_REL and USE_RELA ['twould be nice if such a critter existed], + if only to serve as a learning tool. + + The RELOCATE_SECTION function is called by the new ELF backend linker + to handle the relocations for a section. + + The relocs are always passed as Rela structures; if the section + actually uses Rel structures, the r_addend field will always be + zero. + + This function is responsible for adjust the section contents as + necessary, and (if using Rela relocs and generating a + relocatable output file) adjusting the reloc addend as + necessary. + + This function does not have to worry about setting the reloc + address or the reloc symbol index. + + LOCAL_SYMS is a pointer to the swapped in local symbols. + + LOCAL_SECTIONS is an array giving the section in the input file + corresponding to the st_shndx field of each local symbol. + + The global hash table entry for the global symbols can be found + via elf_sym_hashes (input_bfd). + + When generating relocatable output, this function must handle + STB_LOCAL/STT_SECTION symbols specially. The output symbol is + going to be the section symbol corresponding to the output + section, which means that the addend must be adjusted + accordingly. */ + +static bfd_boolean +microblaze_elf_relocate_section (bfd *output_bfd, + struct bfd_link_info *info, + bfd *input_bfd, + asection *input_section, + bfd_byte *contents, + Elf_Internal_Rela *relocs, + Elf_Internal_Sym *local_syms, + asection **local_sections) +{ + struct elf32_mb_link_hash_table *htab; + Elf_Internal_Shdr *symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr; + struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (input_bfd); + Elf_Internal_Rela *rel, *relend; + /* Assume success. */ + bfd_boolean ret = TRUE; + asection *sreloc; + bfd_vma *local_got_offsets; + + if (!microblaze_elf_howto_table[R_MICROBLAZE_max-1]) + microblaze_elf_howto_init (); + + htab = elf32_mb_hash_table (info); + local_got_offsets = elf_local_got_offsets (input_bfd); + + sreloc = elf_section_data (input_section)->sreloc; + + rel = relocs; + relend = relocs + input_section->reloc_count; + for (; rel < relend; rel++) + { + int r_type; + reloc_howto_type *howto; + unsigned long r_symndx; + bfd_vma addend = rel->r_addend; + bfd_vma offset = rel->r_offset; + struct elf_link_hash_entry *h; + Elf_Internal_Sym *sym; + asection *sec; + const char *sym_name; + bfd_reloc_status_type r = bfd_reloc_ok; + const char *errmsg = NULL; + bfd_boolean unresolved_reloc = FALSE; + + h = NULL; + r_type = ELF32_R_TYPE (rel->r_info); + if (r_type < 0 || r_type >= (int) R_MICROBLAZE_max) + { + (*_bfd_error_handler) (_("%s: unknown relocation type %d"), + bfd_get_filename (input_bfd), (int) r_type); + bfd_set_error (bfd_error_bad_value); + ret = FALSE; + continue; + } + + howto = microblaze_elf_howto_table[r_type]; + r_symndx = ELF32_R_SYM (rel->r_info); + + if (info->relocatable) + { + /* This is a relocatable link. We don't have to change + anything, unless the reloc is against a section symbol, + in which case we have to adjust according to where the + section symbol winds up in the output section. */ + sec = NULL; + if (r_symndx >= symtab_hdr->sh_info) + /* External symbol. */ + continue; + + /* Local symbol. */ + sym = local_syms + r_symndx; + sym_name = "<local symbol>"; + /* STT_SECTION: symbol is associated with a section. */ + if (ELF_ST_TYPE (sym->st_info) != STT_SECTION) + /* Symbol isn't associated with a section. Nothing to do. */ + continue; + + sec = local_sections[r_symndx]; + addend += sec->output_offset + sym->st_value; +#ifndef USE_REL + /* This can't be done for USE_REL because it doesn't mean anything + and elf_link_input_bfd asserts this stays zero. */ + /* rel->r_addend = addend; */ +#endif + +#ifndef USE_REL + /* Addends are stored with relocs. We're done. */ + continue; +#else /* USE_REL */ + /* If partial_inplace, we need to store any additional addend + back in the section. */ + if (!howto->partial_inplace) + continue; + /* ??? Here is a nice place to call a special_function like handler. */ + r = _bfd_relocate_contents (howto, input_bfd, addend, + contents + offset); +#endif /* USE_REL */ + } + else + { + bfd_vma relocation; + + /* This is a final link. */ + sym = NULL; + sec = NULL; + unresolved_reloc = FALSE; + + if (r_symndx < symtab_hdr->sh_info) + { + /* Local symbol. */ + sym = local_syms + r_symndx; + sec = local_sections[r_symndx]; + if (sec == 0) + continue; + sym_name = "<local symbol>"; + relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel); + /* r_addend may have changed if the reference section was + a merge section. */ + addend = rel->r_addend; + } + else + { + /* External symbol. */ + bfd_boolean warned ATTRIBUTE_UNUSED; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, + unresolved_reloc, warned); + sym_name = h->root.root.string; + } + + /* Sanity check the address. */ + if (offset > bfd_get_section_limit (output_bfd, input_section)) + { + r = bfd_reloc_outofrange; + goto check_reloc; + } + + switch ((int) r_type) + { + case (int) R_MICROBLAZE_SRO32 : + { + const char *name; + + /* Only relocate if the symbol is defined. */ + if (sec) + { + name = bfd_get_section_name (abfd, sec); + + if (strcmp (name, ".sdata2") == 0 + || strcmp (name, ".sbss2") == 0) + { + if (ro_small_data_pointer == 0) + microblaze_elf_final_sdp (info); + if (ro_small_data_pointer == 0) + { + ret = FALSE; + r = bfd_reloc_undefined; + goto check_reloc; + } + + /* At this point `relocation' contains the object's + address. */ + relocation -= ro_small_data_pointer; + /* Now it contains the offset from _SDA2_BASE_. */ + r = _bfd_final_link_relocate (howto, input_bfd, + input_section, + contents, offset, + relocation, addend); + } + else + { + (*_bfd_error_handler) (_("%s: The target (%s) of an %s relocation is in the wrong section (%s)"), + bfd_get_filename (input_bfd), + sym_name, + microblaze_elf_howto_table[(int) r_type]->name, + bfd_get_section_name (abfd, sec)); + /*bfd_set_error (bfd_error_bad_value); ??? why? */ + ret = FALSE; + continue; + } + } + } + break; + + case (int) R_MICROBLAZE_SRW32 : + { + const char *name; + + /* Only relocate if the symbol is defined. */ + if (sec) + { + name = bfd_get_section_name (abfd, sec); + + if (strcmp (name, ".sdata") == 0 + || strcmp (name, ".sbss") == 0) + { + if (rw_small_data_pointer == 0) + microblaze_elf_final_sdp (info); + if (rw_small_data_pointer == 0) + { + ret = FALSE; + r = bfd_reloc_undefined; + goto check_reloc; + } + + /* At this point `relocation' contains the object's + address. */ + relocation -= rw_small_data_pointer; + /* Now it contains the offset from _SDA_BASE_. */ + r = _bfd_final_link_relocate (howto, input_bfd, + input_section, + contents, offset, + relocation, addend); + } + else + { + (*_bfd_error_handler) (_("%s: The target (%s) of an %s relocation is in the wrong section (%s)"), + bfd_get_filename (input_bfd), + sym_name, + microblaze_elf_howto_table[(int) r_type]->name, + bfd_get_section_name (abfd, sec)); + /*bfd_set_error (bfd_error_bad_value); ??? why? */ + ret = FALSE; + continue; + } + } + } + break; + + case (int) R_MICROBLAZE_32_SYM_OP_SYM: + break; /* Do nothing. */ + + case (int) R_MICROBLAZE_GOTPC_64: + relocation = htab->sgotplt->output_section->vma + + htab->sgotplt->output_offset; + relocation -= (input_section->output_section->vma + + input_section->output_offset + + offset + INST_WORD_SIZE); + relocation += addend; + bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, + contents + offset + 2); + bfd_put_16 (input_bfd, relocation & 0xffff, + contents + offset + 2 + INST_WORD_SIZE); + break; + + case (int) R_MICROBLAZE_PLT_64: + { + bfd_vma immediate; + if (htab->splt != NULL && h != NULL + && h->plt.offset != (bfd_vma) -1) + { + relocation = (htab->splt->output_section->vma + + htab->splt->output_offset + + h->plt.offset); + unresolved_reloc = FALSE; + immediate = relocation - (input_section->output_section->vma + + input_section->output_offset + + offset + INST_WORD_SIZE); + bfd_put_16 (input_bfd, (immediate >> 16) & 0xffff, + contents + offset + 2); + bfd_put_16 (input_bfd, immediate & 0xffff, + contents + offset + 2 + INST_WORD_SIZE); + } + else + { + relocation -= (input_section->output_section->vma + + input_section->output_offset + + offset + INST_WORD_SIZE); + immediate = relocation; + bfd_put_16 (input_bfd, (immediate >> 16) & 0xffff, + contents + offset + 2); + bfd_put_16 (input_bfd, immediate & 0xffff, + contents + offset + 2 + INST_WORD_SIZE); + } + break; + } + + case (int) R_MICROBLAZE_GOT_64: + { + if (htab->sgot == NULL) + abort (); + if (h == NULL) + { + bfd_vma off; + if (local_got_offsets == NULL) + abort (); + off = local_got_offsets[r_symndx]; + /* The LSB indicates whether we've already + created relocation. */ + if (off & 1) + off &= ~1; + else + { + bfd_put_32 (output_bfd, relocation + addend, + htab->sgot->contents + off); + + if (info->shared) + { + Elf_Internal_Rela outrel; + bfd_byte *loc; + if (htab->srelgot == NULL) + abort (); + outrel.r_offset = (htab->sgot->output_section->vma + + htab->sgot->output_offset + + off); + outrel.r_info = ELF32_R_INFO (0, R_MICROBLAZE_REL); + outrel.r_addend = relocation + addend; + loc = htab->srelgot->contents; + loc += htab->srelgot->reloc_count++ + * sizeof (Elf32_External_Rela); + bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc); + } + local_got_offsets[r_symndx] |= 1; + } + relocation = htab->sgot->output_section->vma + + htab->sgot->output_offset + off + - htab->sgotplt->output_section->vma + - htab->sgotplt->output_offset; + unresolved_reloc = FALSE; + } + else + { + if (htab->sgotplt != NULL && h != NULL + && h->got.offset != (bfd_vma) -1) + { + bfd_put_32 (output_bfd, relocation + addend, + htab->sgot->contents + h->got.offset); + relocation = htab->sgot->output_section->vma + + htab->sgot->output_offset + + h->got.offset + - htab->sgotplt->output_section->vma + - htab->sgotplt->output_offset; + unresolved_reloc = FALSE; + } + else + abort (); /* ??? */ + } + bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, + contents + offset + 2); + bfd_put_16 (input_bfd, relocation & 0xffff, + contents + offset + 2 + INST_WORD_SIZE); + break; + } + + case (int) R_MICROBLAZE_GOTOFF_64: + { + bfd_vma immediate; + unsigned short lo, high; + relocation += addend; + relocation -= htab->sgotplt->output_section->vma + + htab->sgotplt->output_offset; + /* Write this value into correct location. */ + immediate = relocation; + lo = immediate & 0x0000ffff; + high = (immediate >> 16) & 0x0000ffff; + bfd_put_16 (input_bfd, high, contents + offset + 2); + bfd_put_16 (input_bfd, lo, contents + offset + INST_WORD_SIZE + 2); + break; + } + + case (int) R_MICROBLAZE_GOTOFF_32: + { + relocation += addend; + relocation -= htab->sgotplt->output_section->vma + + htab->sgotplt->output_offset; + /* Write this value into correct location. */ + bfd_put_32 (input_bfd, relocation, contents + offset); + break; + } + + case (int) R_MICROBLAZE_64_PCREL : + case (int) R_MICROBLAZE_64: + case (int) R_MICROBLAZE_32: + { + /* r_symndx will be zero only for relocs against symbols + from removed linkonce sections, or sections discarded by + a linker script. */ + if (r_symndx == 0 || (input_section->flags & SEC_ALLOC) == 0) + { + relocation += addend; + if (r_type == R_MICROBLAZE_32) + bfd_put_32 (input_bfd, relocation, contents + offset); + else + { + if (r_type == R_MICROBLAZE_64_PCREL) + relocation -= (input_section->output_section->vma + + input_section->output_offset + + offset + INST_WORD_SIZE); + bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, + contents + offset + 2); + bfd_put_16 (input_bfd, relocation & 0xffff, + contents + offset + 2 + INST_WORD_SIZE); + } + break; + } + + if ((info->shared + && (h == NULL + || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT + || h->root.type != bfd_link_hash_undefweak) + && (!howto->pc_relative + || (h != NULL + && h->dynindx != -1 + && (!info->symbolic + || !h->def_regular)))) + || (!info->shared + && h != NULL + && h->dynindx != -1 + && !h->non_got_ref + && ((h->def_dynamic + && !h->def_regular) + || h->root.type == bfd_link_hash_undefweak + || h->root.type == bfd_link_hash_undefined))) + { + Elf_Internal_Rela outrel; + bfd_byte *loc; + bfd_boolean skip, relocate = FALSE; + + /* When generating a shared object, these relocations + are copied into the output file to be resolved at run + time. */ + + BFD_ASSERT (sreloc != NULL); + + skip = FALSE; + + outrel.r_offset = + _bfd_elf_section_offset (output_bfd, info, input_section, + rel->r_offset); + if (outrel.r_offset == (bfd_vma) -1) + skip = TRUE; + else if (outrel.r_offset == (bfd_vma) -2) + skip = TRUE, relocate = TRUE; + outrel.r_offset += (input_section->output_section->vma + + input_section->output_offset); + + if (skip) + memset (&outrel, 0, sizeof outrel); + /* h->dynindx may be -1 if the symbol was marked to + become local. */ + else if (h != NULL + && ((! info->symbolic && h->dynindx != -1) + || !h->def_regular)) + { + BFD_ASSERT (h->dynindx != -1); + outrel.r_info = ELF32_R_INFO (h->dynindx, r_type); + outrel.r_addend = addend; + } + else + { + if (r_type == R_MICROBLAZE_32) + { + outrel.r_info = ELF32_R_INFO (0, R_MICROBLAZE_REL); + outrel.r_addend = relocation + addend; + } + else + { + BFD_FAIL (); + (*_bfd_error_handler) + (_("%B: probably compiled without -fPIC?"), + input_bfd); + bfd_set_error (bfd_error_bad_value); + return FALSE; + } + } + + loc = sreloc->contents; + loc += sreloc->reloc_count++ * sizeof (Elf32_External_Rela); + bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc); + break; + } + else + { + relocation += addend; + if (r_type == R_MICROBLAZE_32) + bfd_put_32 (input_bfd, relocation, contents + offset); + else + { + if (r_type == R_MICROBLAZE_64_PCREL) + relocation -= (input_section->output_section->vma + + input_section->output_offset + + offset + INST_WORD_SIZE); + bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, + contents + offset + 2); + bfd_put_16 (input_bfd, relocation & 0xffff, + contents + offset + 2 + INST_WORD_SIZE); + } + break; + } + } + + default : + r = _bfd_final_link_relocate (howto, input_bfd, input_section, + contents, offset, + relocation, addend); + break; + } + } + + check_reloc: + + if (r != bfd_reloc_ok) + { + /* FIXME: This should be generic enough to go in a utility. */ + const char *name; + + if (h != NULL) + name = h->root.root.string; + else + { + name = (bfd_elf_string_from_elf_section + (input_bfd, symtab_hdr->sh_link, sym->st_name)); + if (name == NULL || *name == '\0') + name = bfd_section_name (input_bfd, sec); + } + + if (errmsg != NULL) + goto common_error; + + switch (r) + { + case bfd_reloc_overflow: + if (!((*info->callbacks->reloc_overflow) + (info, (h ? &h->root : NULL), name, howto->name, + (bfd_vma) 0, input_bfd, input_section, offset))) + return FALSE; + break; + + case bfd_reloc_undefined: + if (!((*info->callbacks->undefined_symbol) + (info, name, input_bfd, input_section, offset, TRUE))) + return FALSE; + break; + + case bfd_reloc_outofrange: + errmsg = _("internal error: out of range error"); + goto common_error; + + case bfd_reloc_notsupported: + errmsg = _("internal error: unsupported relocation error"); + goto common_error; + + case bfd_reloc_dangerous: + errmsg = _("internal error: dangerous error"); + goto common_error; + + default: + errmsg = _("internal error: unknown error"); + /* Fall through. */ + common_error: + if (!((*info->callbacks->warning) + (info, errmsg, name, input_bfd, input_section, offset))) + return FALSE; + break; + } + } + } + + return ret; +} + +/* Calculate fixup value for reference. */ + +static int +calc_fixup (bfd_vma addr, asection *sec) +{ + int i, fixup = 0; + + if (sec == NULL || sec->relax == NULL) + return 0; + + /* Look for addr in relax table, total fixup value. */ + for (i = 0; i < sec->relax_count; i++) + { + if (addr <= sec->relax[i].addr) + break; + fixup += sec->relax[i].size; + } + + return fixup; +} + +static bfd_boolean +microblaze_elf_relax_section (bfd *abfd, + asection *sec, + struct bfd_link_info *link_info, + bfd_boolean *again) +{ + Elf_Internal_Shdr *symtab_hdr; + Elf_Internal_Rela *internal_relocs; + Elf_Internal_Rela *free_relocs = NULL; + Elf_Internal_Rela *irel, *irelend; + bfd_byte *contents = NULL; + bfd_byte *free_contents = NULL; + int rel_count; + unsigned int shndx; + int i, index; + asection *o; + struct elf_link_hash_entry *sym_hash; + Elf_Internal_Sym *isymbuf, *isymend; + Elf_Internal_Sym *isym; + int symcount; + int offset; + bfd_vma src, dest; + + /* We only do this once per section. We may be able to delete some code + by running multiple passes, but it is not worth it. */ + *again = FALSE; + + /* Only do this for a text section. */ + if (link_info->relocatable + || (sec->flags & SEC_RELOC) == 0 + || (sec->reloc_count == 0)) + return TRUE; + + BFD_ASSERT ((sec->size > 0) || (sec->rawsize > 0)); + + /* If this is the first time we have been called for this section, + initialize the cooked size. */ + if (sec->size == 0) + sec->size = sec->rawsize; + + /* Get symbols for this section. */ + symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents; + symcount = symtab_hdr->sh_size / sizeof (Elf32_External_Sym); + if (isymbuf == NULL) + isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr, symcount, + 0, NULL, NULL, NULL); + BFD_ASSERT (isymbuf != NULL); + + internal_relocs = _bfd_elf_link_read_relocs + (abfd, sec, NULL, NULL, link_info->keep_memory); + if (internal_relocs == NULL) + goto error_return; + if (! link_info->keep_memory) + free_relocs = internal_relocs; + + sec->relax = (struct relax_table *) bfd_malloc ((sec->reloc_count + 1) + * sizeof (struct relax_table)); + if (sec->relax == NULL) + goto error_return; + sec->relax_count = 0; + + irelend = internal_relocs + sec->reloc_count; + rel_count = 0; + for (irel = internal_relocs; irel < irelend; irel++, rel_count++) + { + bfd_vma symval; + if ((ELF32_R_TYPE (irel->r_info) != (int) R_MICROBLAZE_64_PCREL) + && (ELF32_R_TYPE (irel->r_info) != (int) R_MICROBLAZE_64 )) + continue; /* Can't delete this reloc. */ + + /* Get the section contents. */ + if (contents == NULL) + { + if (elf_section_data (sec)->this_hdr.contents != NULL) + contents = elf_section_data (sec)->this_hdr.contents; + else + { + contents = (bfd_byte *) bfd_malloc (sec->size); + if (contents == NULL) + goto error_return; + free_contents = contents; + + if (!bfd_get_section_contents (abfd, sec, contents, + (file_ptr) 0, sec->size)) + goto error_return; + elf_section_data (sec)->this_hdr.contents = contents; + } + } + + /* Get the value of the symbol referred to by the reloc. */ + if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info) + { + /* A local symbol. */ + Elf_Internal_Sym *isym; + asection *sym_sec; + + isym = isymbuf + ELF32_R_SYM (irel->r_info); + if (isym->st_shndx == SHN_UNDEF) + sym_sec = bfd_und_section_ptr; + else if (isym->st_shndx == SHN_ABS) + sym_sec = bfd_abs_section_ptr; + else if (isym->st_shndx == SHN_COMMON) + sym_sec = bfd_com_section_ptr; + else + sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx); + + symval = _bfd_elf_rela_local_sym (abfd, isym, &sym_sec, irel); + } + else + { + unsigned long indx; + struct elf_link_hash_entry *h; + + indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info; + h = elf_sym_hashes (abfd)[indx]; + BFD_ASSERT (h != NULL); + + if (h->root.type != bfd_link_hash_defined + && h->root.type != bfd_link_hash_defweak) + /* This appears to be a reference to an undefined + symbol. Just ignore it--it will be caught by the + regular reloc processing. */ + continue; + + symval = (h->root.u.def.value + + h->root.u.def.section->output_section->vma + + h->root.u.def.section->output_offset); + } + + /* If this is a PC-relative reloc, subtract the instr offset from + the symbol value. */ + if (ELF32_R_TYPE (irel->r_info) == (int) R_MICROBLAZE_64_PCREL) + { + symval = symval + irel->r_addend + - (irel->r_offset + + sec->output_section->vma + + sec->output_offset); + } + else + symval += irel->r_addend; + + if ((symval & 0xffff8000) == 0 + || (symval & 0xffff8000) == 0xffff8000) + { + /* We can delete this instruction. */ + sec->relax[sec->relax_count].addr = irel->r_offset; + sec->relax[sec->relax_count].size = INST_WORD_SIZE; + sec->relax_count++; + + /* Rewrite relocation type. */ + switch ((enum elf_microblaze_reloc_type) ELF32_R_TYPE (irel->r_info)) + { + case R_MICROBLAZE_64_PCREL: + irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), + (int) R_MICROBLAZE_32_PCREL_LO); + break; + case R_MICROBLAZE_64: + irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), + (int) R_MICROBLAZE_32_LO); + break; + default: + /* Cannot happen. */ + BFD_ASSERT (FALSE); + } + } + } /* Loop through all relocations. */ + + /* Loop through the relocs again, and see if anything needs to change. */ + if (sec->relax_count > 0) + { + shndx = _bfd_elf_section_from_bfd_section (abfd, sec); + rel_count = 0; + sec->relax[sec->relax_count].addr = sec->size; + + for (irel = internal_relocs; irel < irelend; irel++, rel_count++) + { + bfd_vma nraddr; + + /* Get the new reloc address. */ + nraddr = irel->r_offset - calc_fixup (irel->r_offset, sec); + switch ((enum elf_microblaze_reloc_type) ELF32_R_TYPE (irel->r_info)) + { + default: + break; + case R_MICROBLAZE_64_PCREL: + break; + case R_MICROBLAZE_64: + case R_MICROBLAZE_32_LO: + /* If this reloc is against a symbol defined in this + section, we must check the addend to see it will put the value in + range to be adjusted, and hence must be changed. */ + if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info) + { + Elf_Internal_Sym *isym; + isym = isymbuf + ELF32_R_SYM (irel->r_info); + /* Only handle relocs against .text. */ + if (isym->st_shndx == shndx + && ELF32_ST_TYPE (isym->st_info) == STT_SECTION) + irel->r_addend -= calc_fixup (irel->r_addend, sec); + } + break; + case R_MICROBLAZE_NONE: + { + /* This was a PC-relative instruction that was + completely resolved. */ + int sfix, efix; + bfd_vma target_address; + target_address = irel->r_addend + irel->r_offset; + sfix = calc_fixup (irel->r_offset, sec); + efix = calc_fixup (target_address, sec); + irel->r_addend -= (efix - sfix); + /* Should use HOWTO. */ + bfd_put_16 (abfd, irel->r_addend, contents + irel->r_offset + 2); + } + break; + case R_MICROBLAZE_64_NONE: + { + /* This was a PC-relative 64-bit instruction that was + completely resolved. */ + int sfix, efix; + bfd_vma target_address; + target_address = irel->r_addend + irel->r_offset + INST_WORD_SIZE; + sfix = calc_fixup (irel->r_offset + INST_WORD_SIZE, sec); + efix = calc_fixup (target_address, sec); + irel->r_addend -= (efix - sfix); + bfd_put_16 (abfd, irel->r_addend, contents + irel->r_offset + + INST_WORD_SIZE + 2); + } + break; + } + irel->r_offset = nraddr; + } /* Change all relocs in this section. */ + + /* Look through all other sections. */ + for (o = abfd->sections; o != NULL; o = o->next) + { + Elf_Internal_Rela *internal_relocs; + Elf_Internal_Rela *irelscan, *irelscanend; + bfd_byte *ocontents; + + if (o == sec + || (o->flags & SEC_RELOC) == 0 + || o->reloc_count == 0) + continue; + + /* We always cache the relocs. Perhaps, if info->keep_memory is + FALSE, we should free them, if we are permitted to. */ + + internal_relocs = _bfd_elf_link_read_relocs (abfd, o, NULL, NULL, TRUE); + if (internal_relocs == NULL) + goto error_return; + + ocontents = NULL; + irelscanend = internal_relocs + o->reloc_count; + for (irelscan = internal_relocs; irelscan < irelscanend; irelscan++) + { + if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32) + { + isym = isymbuf + ELF32_R_SYM (irelscan->r_info); + + /* Look at the reloc only if the value has been resolved. */ + if (isym->st_shndx == shndx + && (ELF32_ST_TYPE (isym->st_info) == STT_SECTION)) + { + if (ocontents == NULL) + { + if (elf_section_data (o)->this_hdr.contents != NULL) + ocontents = elf_section_data (o)->this_hdr.contents; + else + { + /* We always cache the section contents. + Perhaps, if info->keep_memory is FALSE, we + should free them, if we are permitted to. */ + if (o->rawsize == 0) + o->rawsize = o->size; + ocontents = (bfd_byte *) bfd_malloc (o->rawsize); + if (ocontents == NULL) + goto error_return; + if (!bfd_get_section_contents (abfd, o, ocontents, + (file_ptr) 0, + o->rawsize)) + goto error_return; + elf_section_data (o)->this_hdr.contents = ocontents; + } + + } + irelscan->r_addend -= calc_fixup (irelscan->r_addend, sec); + } + else if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_SYM_OP_SYM) + { + isym = isymbuf + ELF32_R_SYM (irelscan->r_info); + + /* Look at the reloc only if the value has been resolved. */ + if (ocontents == NULL) + { + if (elf_section_data (o)->this_hdr.contents != NULL) + ocontents = elf_section_data (o)->this_hdr.contents; + else + { + /* We always cache the section contents. + Perhaps, if info->keep_memory is FALSE, we + should free them, if we are permitted to. */ + + if (o->rawsize == 0) + o->rawsize = o->size; + ocontents = (bfd_byte *) bfd_malloc (o->rawsize); + if (ocontents == NULL) + goto error_return; + if (!bfd_get_section_contents (abfd, o, ocontents, + (file_ptr) 0, + o->rawsize)) + goto error_return; + elf_section_data (o)->this_hdr.contents = ocontents; + } + } + irelscan->r_addend -= calc_fixup (irel->r_addend + + isym->st_value, + sec); + } + } + else if ((ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_PCREL_LO) + || (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_LO)) + { + isym = isymbuf + ELF32_R_SYM (irelscan->r_info); + + /* Look at the reloc only if the value has been resolved. */ + if (isym->st_shndx == shndx + && (ELF32_ST_TYPE (isym->st_info) == STT_SECTION)) + { + bfd_vma immediate; + bfd_vma target_address; + + if (ocontents == NULL) + { + if (elf_section_data (o)->this_hdr.contents != NULL) + ocontents = elf_section_data (o)->this_hdr.contents; + else + { + /* We always cache the section contents. + Perhaps, if info->keep_memory is FALSE, we + should free them, if we are permitted to. */ + if (o->rawsize == 0) + o->rawsize = o->size; + ocontents = (bfd_byte *) bfd_malloc (o->rawsize); + if (ocontents == NULL) + goto error_return; + if (!bfd_get_section_contents (abfd, o, ocontents, + (file_ptr) 0, + o->rawsize)) + goto error_return; + elf_section_data (o)->this_hdr.contents = ocontents; + } + } + + immediate = (unsigned short) bfd_get_16 (abfd, ocontents + + irelscan->r_offset + 2); + target_address = immediate; + offset = calc_fixup (target_address, sec); + immediate -= offset; + irelscan->r_addend -= offset; + bfd_put_16 (abfd, immediate, ocontents + irelscan->r_offset + 2); + } + } + + if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64) + { + isym = isymbuf + ELF32_R_SYM (irelscan->r_info); + + /* Look at the reloc only if the value has been resolved. */ + if (isym->st_shndx == shndx + && (ELF32_ST_TYPE (isym->st_info) == STT_SECTION)) + { + bfd_vma immediate; + + if (ocontents == NULL) + { + if (elf_section_data (o)->this_hdr.contents != NULL) + ocontents = elf_section_data (o)->this_hdr.contents; + else + { + /* We always cache the section contents. + Perhaps, if info->keep_memory is FALSE, we + should free them, if we are permitted to. */ + + if (o->rawsize == 0) + o->rawsize = o->size; + ocontents = (bfd_byte *) bfd_malloc (o->rawsize); + if (ocontents == NULL) + goto error_return; + if (!bfd_get_section_contents (abfd, o, ocontents, + (file_ptr) 0, + o->rawsize)) + goto error_return; + elf_section_data (o)->this_hdr.contents = ocontents; + } + } + immediate = (unsigned short) (bfd_get_16 (abfd, ocontents + + irelscan->r_offset + + 2) << 16) + & 0xffff0000; + immediate += (unsigned short) (bfd_get_16 (abfd, ocontents + + irelscan->r_offset + + INST_WORD_SIZE + 2)) + & 0x0000ffff; + + offset = calc_fixup (irelscan->r_addend, sec); + immediate -= offset; + irelscan->r_addend -= offset; + } + } + else if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_PCREL) + { + isym = isymbuf + ELF32_R_SYM (irelscan->r_info); + + /* Look at the reloc only if the value has been resolved. */ + if (isym->st_shndx == shndx + && (ELF32_ST_TYPE (isym->st_info) == STT_SECTION)) + { + bfd_vma immediate; + bfd_vma target_address; + + if (ocontents == NULL) + { + if (elf_section_data (o)->this_hdr.contents != NULL) + ocontents = elf_section_data (o)->this_hdr.contents; + else + { + /* We always cache the section contents. + Perhaps, if info->keep_memory is FALSE, we + should free them, if we are permitted to. */ + if (o->rawsize == 0) + o->rawsize = o->size; + ocontents = (bfd_byte *) bfd_malloc (o->rawsize); + if (ocontents == NULL) + goto error_return; + if (!bfd_get_section_contents (abfd, o, ocontents, + (file_ptr) 0, + o->rawsize)) + goto error_return; + elf_section_data (o)->this_hdr.contents = ocontents; + } + } + + immediate = (unsigned short) + (bfd_get_16 (abfd, ocontents + irelscan->r_offset + 2) << 16) + & 0xffff0000; + immediate += (unsigned short) + (bfd_get_16 (abfd, ocontents + irelscan->r_offset + + INST_WORD_SIZE + 2)) + & 0x0000ffff; + target_address = immediate; + offset = calc_fixup (target_address, sec); + immediate -= offset; + irelscan->r_addend -= offset; + bfd_put_16 (abfd, ((immediate >> 16) & 0x0000ffff), + ocontents + irelscan->r_offset + 2); + bfd_put_16 (abfd, (immediate & 0x0000ffff), + ocontents + irelscan->r_offset + INST_WORD_SIZE + 2); + } + } + } + } + + /* Adjust the local symbols defined in this section. */ + isymend = isymbuf + symtab_hdr->sh_info; + for (isym = isymbuf; isym < isymend; isym++) + { + if (isym->st_shndx == shndx) + isym->st_value =- calc_fixup (isym->st_value, sec); + } + + /* Now adjust the global symbols defined in this section. */ + isym = isymbuf + symtab_hdr->sh_info; + isymend = isymbuf + (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)); + for (index = 0; isym < isymend; isym++, index++) + { + sym_hash = elf_sym_hashes (abfd)[index]; + if (isym->st_shndx == shndx + && (sym_hash->root.type == bfd_link_hash_defined + || sym_hash->root.type == bfd_link_hash_defweak) + && sym_hash->root.u.def.section == sec) + { + sym_hash->root.u.def.value -= calc_fixup (sym_hash->root.u.def.value, + sec); + } + } + + /* Physically move the code and change the cooked size. */ + dest = sec->relax[0].addr; + for (i = 0; i < sec->relax_count; i++) + { + int len; + src = sec->relax[i].addr + sec->relax[i].size; + len = sec->relax[i+1].addr - sec->relax[i].addr - sec->relax[i].size; + + memmove (contents + dest, contents + src, len); + sec->size -= sec->relax[i].size; + dest += len; + } + + elf_section_data (sec)->relocs = internal_relocs; + free_relocs = NULL; + + elf_section_data (sec)->this_hdr.contents = contents; + free_contents = NULL; + + symtab_hdr->contents = (bfd_byte *) isymbuf; + } + + if (free_relocs != NULL) + { + free (free_relocs); + free_relocs = NULL; + } + + if (free_contents != NULL) + { + if (!link_info->keep_memory) + free (free_contents); + else + /* Cache the section contents for elf_link_input_bfd. */ + elf_section_data (sec)->this_hdr.contents = contents; + free_contents = NULL; + } + + if (sec->relax_count == 0) + { + free (sec->relax); + sec->relax = NULL; + } + return TRUE; + + error_return: + if (free_relocs != NULL) + free (free_relocs); + if (free_contents != NULL) + free (free_contents); + if (sec->relax != NULL) + { + free (sec->relax); + sec->relax = NULL; + sec->relax_count = 0; + } + return FALSE; +} + +/* Return the section that should be marked against GC for a given + relocation. */ + +static asection * +microblaze_elf_gc_mark_hook (asection *sec, + struct bfd_link_info * info ATTRIBUTE_UNUSED, + Elf_Internal_Rela * rel, + struct elf_link_hash_entry * h, + Elf_Internal_Sym * sym) +{ + if (h != NULL) + { + switch (ELF32_R_TYPE (rel->r_info)) + { + case R_MICROBLAZE_GNU_VTINHERIT: + case R_MICROBLAZE_GNU_VTENTRY: + break; + + default: + switch (h->root.type) + { + case bfd_link_hash_defined: + case bfd_link_hash_defweak: + return h->root.u.def.section; + + case bfd_link_hash_common: + return h->root.u.c.p->section; + + default: + break; + } + } + } + else + return bfd_section_from_elf_index (sec->owner, sym->st_shndx); + + return NULL; +} + +/* Update the got entry reference counts for the section being removed. */ + +static bfd_boolean +microblaze_elf_gc_sweep_hook (bfd * abfd ATTRIBUTE_UNUSED, + struct bfd_link_info * info ATTRIBUTE_UNUSED, + asection * sec ATTRIBUTE_UNUSED, + const Elf_Internal_Rela * relocs ATTRIBUTE_UNUSED) +{ + return TRUE; +} + +/* PIC support. */ + +#define PLT_ENTRY_SIZE 16 + +#define PLT_ENTRY_WORD_0 0xb0000000 /* "imm 0". */ +#define PLT_ENTRY_WORD_1 0xe9940000 /* "lwi r12,r20,0" - relocated to lwi r12,r20,func@GOT. */ +#define PLT_ENTRY_WORD_1_NOPIC 0xe9800000 /* "lwi r12,r0,0" - non-PIC object. */ +#define PLT_ENTRY_WORD_2 0x98186000 /* "brad r12". */ +#define PLT_ENTRY_WORD_3 0x80000000 /* "nop". */ + +/* Create .got, .gotplt, and .rela.got sections in DYNOBJ, and set up + shortcuts to them in our hash table. */ + +static bfd_boolean +create_got_section (bfd *dynobj, struct bfd_link_info *info) +{ + struct elf32_mb_link_hash_table *htab; + + if (! _bfd_elf_create_got_section (dynobj, info)) + return FALSE; + htab = elf32_mb_hash_table (info); + htab->sgot = bfd_get_section_by_name (dynobj, ".got"); + htab->sgotplt = bfd_get_section_by_name (dynobj, ".got.plt"); + if (!htab->sgot || !htab->sgotplt) + return FALSE; + + htab->srelgot = bfd_make_section (dynobj, ".rela.got"); + if (htab->srelgot == NULL + || ! bfd_set_section_flags (dynobj, htab->srelgot, SEC_ALLOC + | SEC_LOAD + | SEC_HAS_CONTENTS + | SEC_IN_MEMORY + | SEC_LINKER_CREATED + | SEC_READONLY) + || ! bfd_set_section_alignment (dynobj, htab->srelgot, 2)) + return FALSE; + return TRUE; +} + +/* Look through the relocs for a section during the first phase. */ + +static bfd_boolean +microblaze_elf_check_relocs (bfd * abfd, + struct bfd_link_info * info, + asection * sec, + const Elf_Internal_Rela * relocs) +{ + Elf_Internal_Shdr * symtab_hdr; + struct elf_link_hash_entry ** sym_hashes; + struct elf_link_hash_entry ** sym_hashes_end; + const Elf_Internal_Rela * rel; + const Elf_Internal_Rela * rel_end; + struct elf32_mb_link_hash_table *htab; + bfd_vma *local_got_offsets; + asection *sreloc = NULL; + + if (info->relocatable) + return TRUE; + + htab = elf32_mb_hash_table (info); + local_got_offsets = elf_local_got_offsets (abfd); + symtab_hdr = & elf_tdata (abfd)->symtab_hdr; + sym_hashes = elf_sym_hashes (abfd); + sym_hashes_end = sym_hashes + symtab_hdr->sh_size / sizeof (Elf32_External_Sym); + if (!elf_bad_symtab (abfd)) + sym_hashes_end -= symtab_hdr->sh_info; + + rel_end = relocs + sec->reloc_count; + + for (rel = relocs; rel < rel_end; rel++) + { + unsigned int r_type; + struct elf_link_hash_entry * h; + unsigned long r_symndx; + + r_symndx = ELF32_R_SYM (rel->r_info); + r_type = ELF32_R_TYPE (rel->r_info); + + if (r_symndx < symtab_hdr->sh_info) + h = NULL; + else + h = sym_hashes [r_symndx - symtab_hdr->sh_info]; + + switch (r_type) + { + /* This relocation describes the C++ object vtable hierarchy. + Reconstruct it for later use during GC. */ + case R_MICROBLAZE_GNU_VTINHERIT: + if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset)) + return FALSE; + break; + + /* This relocation describes which C++ vtable entries are actually + used. Record for later use during GC. */ + case R_MICROBLAZE_GNU_VTENTRY: + if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_addend)) + return FALSE; + break; + + /* This relocation requires .plt entry. */ + case R_MICROBLAZE_PLT_64: + if (h != NULL) + { + h->needs_plt = 1; + h->plt.refcount += 1; + } + break; + + /* This relocation requires .got entry. */ + case R_MICROBLAZE_GOT_64: + if (htab->sgot == NULL) + { + if (htab->elf.dynobj == NULL) + htab->elf.dynobj = abfd; + if (!create_got_section (htab->elf.dynobj, info)) + return FALSE; + } + if (h != NULL) + { + h->got.refcount += 1; + } + else + { + bfd_signed_vma *local_got_refcounts; + + /* This is a global offset table entry for a local symbol. */ + local_got_refcounts = elf_local_got_refcounts (abfd); + if (local_got_refcounts == NULL) + { + bfd_size_type size; + + size = symtab_hdr->sh_info; + size *= sizeof (bfd_signed_vma); + local_got_refcounts = bfd_zalloc (abfd, size); + if (local_got_refcounts == NULL) + return FALSE; + elf_local_got_refcounts (abfd) = local_got_refcounts; + } + local_got_refcounts[r_symndx] += 1; + } + break; + + case R_MICROBLAZE_64: + case R_MICROBLAZE_64_PCREL: + case R_MICROBLAZE_32: + { + if (h != NULL && !info->shared) + { + /* we may need a copy reloc. */ + h->non_got_ref = 1; + + /* we may also need a .plt entry. */ + h->plt.refcount += 1; + if (ELF32_R_TYPE (rel->r_info) != R_MICROBLAZE_64_PCREL) + h->pointer_equality_needed = 1; + } + + + /* If we are creating a shared library, and this is a reloc + against a global symbol, or a non PC relative reloc + against a local symbol, then we need to copy the reloc + into the shared library. However, if we are linking with + -Bsymbolic, we do not need to copy a reloc against a + global symbol which is defined in an object we are + including in the link (i.e., DEF_REGULAR is set). At + this point we have not seen all the input files, so it is + possible that DEF_REGULAR is not set now but will be set + later (it is never cleared). In case of a weak definition, + DEF_REGULAR may be cleared later by a strong definition in + a shared library. We account for that possibility below by + storing information in the relocs_copied field of the hash + table entry. A similar situation occurs when creating + shared libraries and symbol visibility changes render the + symbol local. + + If on the other hand, we are creating an executable, we + may need to keep relocations for symbols satisfied by a + dynamic library if we manage to avoid copy relocs for the + symbol. */ + + if ((info->shared + && (sec->flags & SEC_ALLOC) != 0 + && (r_type != R_MICROBLAZE_64_PCREL + || (h != NULL + && (! info->symbolic + || h->root.type == bfd_link_hash_defweak + || !h->def_regular)))) + || (!info->shared + && (sec->flags & SEC_ALLOC) != 0 + && h != NULL + && (h->root.type == bfd_link_hash_defweak + || !h->def_regular))) + { + struct elf32_mb_dyn_relocs *p; + struct elf32_mb_dyn_relocs **head; + + /* When creating a shared object, we must copy these + relocs into the output file. We create a reloc + section in dynobj and make room for the reloc. */ + + if (sreloc == NULL) + { + const char *name; + bfd *dynobj; + unsigned int strndx = elf_elfheader (abfd)->e_shstrndx; + unsigned int shnam = elf_section_data (sec)->rel_hdr.sh_name; + + name = bfd_elf_string_from_elf_section (abfd, strndx, shnam); + if (name == NULL) + return FALSE; + + if (strncmp (name, ".rela", 5) != 0 + || strcmp (bfd_get_section_name (abfd, sec), + name + 5) != 0) + { + (*_bfd_error_handler) + (_("%B: bad relocation section name `%s\'"), + abfd, name); + } + + if (htab->elf.dynobj == NULL) + htab->elf.dynobj = abfd; + dynobj = htab->elf.dynobj; + + sreloc = bfd_get_section_by_name (dynobj, name); + if (sreloc == NULL) + { + flagword flags; + + sreloc = bfd_make_section (dynobj, name); + flags = (SEC_HAS_CONTENTS | SEC_READONLY + | SEC_IN_MEMORY | SEC_LINKER_CREATED); + if ((sec->flags & SEC_ALLOC) != 0) + flags |= SEC_ALLOC | SEC_LOAD; + if (sreloc == NULL + || ! bfd_set_section_flags (dynobj, sreloc, flags) + || ! bfd_set_section_alignment (dynobj, sreloc, 2)) + return FALSE; + } + elf_section_data (sec)->sreloc = sreloc; + } + + /* If this is a global symbol, we count the number of + relocations we need for this symbol. */ + if (h != NULL) + head = &((struct elf32_mb_link_hash_entry *) h)->dyn_relocs; + else + { + /* Track dynamic relocs needed for local syms too. + We really need local syms available to do this + easily. Oh well. */ + + asection *s; + Elf_Internal_Sym *isym; + + isym = bfd_sym_from_r_symndx (&htab->sym_sec, + abfd, r_symndx); + if (isym == NULL) + return FALSE; + + s = bfd_section_from_elf_index (abfd, isym->st_shndx); + if (s == NULL) + return FALSE; + + head = ((struct elf32_mb_dyn_relocs **) + &elf_section_data (s)->local_dynrel); + } + + p = *head; + if (p == NULL || p->sec != sec) + { + bfd_size_type amt = sizeof *p; + p = ((struct elf32_mb_dyn_relocs *) + bfd_alloc (htab->elf.dynobj, amt)); + if (p == NULL) + return FALSE; + p->next = *head; + *head = p; + p->sec = sec; + p->count = 0; + p->pc_count = 0; + } + + p->count += 1; + if (r_type == R_MICROBLAZE_64_PCREL) + p->pc_count += 1; + } + } + break; + } + } + + return TRUE; +} + +static bfd_boolean +microblaze_elf_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info) +{ + struct elf32_mb_link_hash_table *htab; + + htab = elf32_mb_hash_table (info); + if (!htab->sgot && !create_got_section (dynobj, info)) + return FALSE; + + if (!_bfd_elf_create_dynamic_sections (dynobj, info)) + return FALSE; + + htab->splt = bfd_get_section_by_name (dynobj, ".plt"); + htab->srelplt = bfd_get_section_by_name (dynobj, ".rela.plt"); + htab->sdynbss = bfd_get_section_by_name (dynobj, ".dynbss"); + if (!info->shared) + htab->srelbss = bfd_get_section_by_name (dynobj, ".rela.bss"); + + if (!htab->splt || !htab->srelplt || !htab->sdynbss + || (!info->shared && !htab->srelbss)) + abort (); + + return TRUE; +} + +/* Copy the extra info we tack onto an elf_link_hash_entry. */ + +static void +microblaze_elf_copy_indirect_symbol (struct bfd_link_info *info, + struct elf_link_hash_entry *dir, + struct elf_link_hash_entry *ind) +{ + struct elf32_mb_link_hash_entry *edir, *eind; + + edir = (struct elf32_mb_link_hash_entry *) dir; + eind = (struct elf32_mb_link_hash_entry *) ind; + + if (eind->dyn_relocs != NULL) + { + if (edir->dyn_relocs != NULL) + { + struct elf32_mb_dyn_relocs **pp; + struct elf32_mb_dyn_relocs *p; + + if (ind->root.type == bfd_link_hash_indirect) + abort (); + + /* Add reloc counts against the weak sym to the strong sym + list. Merge any entries against the same section. */ + for (pp = &eind->dyn_relocs; (p = *pp) != NULL; ) + { + struct elf32_mb_dyn_relocs *q; + + for (q = edir->dyn_relocs; q != NULL; q = q->next) + if (q->sec == p->sec) + { + q->pc_count += p->pc_count; + q->count += p->count; + *pp = p->next; + break; + } + if (q == NULL) + pp = &p->next; + } + *pp = edir->dyn_relocs; + } + + edir->dyn_relocs = eind->dyn_relocs; + eind->dyn_relocs = NULL; + } + + _bfd_elf_link_hash_copy_indirect (info, dir, ind); +} + +static bfd_boolean +microblaze_elf_adjust_dynamic_symbol (struct bfd_link_info *info, + struct elf_link_hash_entry *h) +{ + struct elf32_mb_link_hash_table *htab; + struct elf32_mb_link_hash_entry * eh; + struct elf32_mb_dyn_relocs *p; + asection *sdynbss, *s; + unsigned int power_of_two; + bfd *dynobj; + + htab = elf32_mb_hash_table (info); + + /* If this is a function, put it in the procedure linkage table. We + will fill in the contents of the procedure linkage table later, + when we know the address of the .got section. */ + if (h->type == STT_FUNC + || h->needs_plt) + { + if (h->plt.refcount <= 0 + || SYMBOL_CALLS_LOCAL (info, h) + || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT + && h->root.type == bfd_link_hash_undefweak)) + { + /* This case can occur if we saw a PLT reloc in an input + file, but the symbol was never referred to by a dynamic + object, or if all references were garbage collected. In + such a case, we don't actually need to build a procedure + linkage table, and we can just do a PC32 reloc instead. */ + h->plt.offset = (bfd_vma) -1; + h->needs_plt = 0; + } + + return TRUE; + } + else + /* It's possible that we incorrectly decided a .plt reloc was + needed for an R_MICROBLAZE_64_PCREL reloc to a non-function sym in + check_relocs. We can't decide accurately between function and + non-function syms in check-relocs; Objects loaded later in + the link may change h->type. So fix it now. */ + h->plt.offset = (bfd_vma) -1; + + /* If this is a weak symbol, and there is a real definition, the + processor independent code will have arranged for us to see the + real definition first, and we can just use the same value. */ + if (h->u.weakdef != NULL) + { + BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined + || h->u.weakdef->root.type == bfd_link_hash_defweak); + h->root.u.def.section = h->u.weakdef->root.u.def.section; + h->root.u.def.value = h->u.weakdef->root.u.def.value; + return TRUE; + } + + /* This is a reference to a symbol defined by a dynamic object which + is not a function. */ + + /* If we are creating a shared library, we must presume that the + only references to the symbol are via the global offset table. + For such cases we need not do anything here; the relocations will + be handled correctly by relocate_section. */ + if (info->shared) + return TRUE; + + /* If there are no references to this symbol that do not use the + GOT, we don't need to generate a copy reloc. */ + if (!h->non_got_ref) + return TRUE; + + /* If -z nocopyreloc was given, we won't generate them either. */ + if (info->nocopyreloc) + { + h->non_got_ref = 0; + return TRUE; + } + + eh = (struct elf32_mb_link_hash_entry *) h; + for (p = eh->dyn_relocs; p != NULL; p = p->next) + { + s = p->sec->output_section; + if (s != NULL && (s->flags & SEC_READONLY) != 0) + break; + } + + /* If we didn't find any dynamic relocs in read-only sections, then + we'll be keeping the dynamic relocs and avoiding the copy reloc. */ + if (p == NULL) + { + h->non_got_ref = 0; + return TRUE; + } + + /* We must allocate the symbol in our .dynbss section, which will + become part of the .bss section of the executable. There will be + an entry for this symbol in the .dynsym section. The dynamic + object will contain position independent code, so all references + from the dynamic object to this symbol will go through the global + offset table. The dynamic linker will use the .dynsym entry to + determine the address it must put in the global offset table, so + both the dynamic object and the regular object will refer to the + same memory location for the variable. */ + + /* We must generate a R_MICROBLAZE_COPY reloc to tell the dynamic linker + to copy the initial value out of the dynamic object and into the + runtime process image. */ + dynobj = elf_hash_table (info)->dynobj; + BFD_ASSERT (dynobj != NULL); + if ((h->root.u.def.section->flags & SEC_ALLOC) != 0) + { + htab->srelbss->size += sizeof (Elf32_External_Rela); + h->needs_copy = 1; + } + + /* We need to figure out the alignment required for this symbol. I + have no idea how ELF linkers handle this. */ + power_of_two = bfd_log2 (h->size); + if (power_of_two > 3) + power_of_two = 3; + + sdynbss = htab->sdynbss; + /* Apply the required alignment. */ + sdynbss->size = BFD_ALIGN (sdynbss->size, (bfd_size_type) (1 << power_of_two)); + if (power_of_two > bfd_get_section_alignment (dynobj, sdynbss)) + { + if (! bfd_set_section_alignment (dynobj, sdynbss, power_of_two)) + return FALSE; + } + + /* Define the symbol as being at this point in the section. */ + h->root.u.def.section = sdynbss; + h->root.u.def.value = sdynbss->size; + + /* Increment the section size to make room for the symbol. */ + sdynbss->size += h->size; + return TRUE; +} + +/* Allocate space in .plt, .got and associated reloc sections for + dynamic relocs. */ + +static bfd_boolean +allocate_dynrelocs (struct elf_link_hash_entry *h, void * dat) +{ + struct bfd_link_info *info; + struct elf32_mb_link_hash_table *htab; + struct elf32_mb_link_hash_entry *eh; + struct elf32_mb_dyn_relocs *p; + + if (h->root.type == bfd_link_hash_indirect) + return TRUE; + + if (h->root.type == bfd_link_hash_warning) + /* When warning symbols are created, they **replace** the "real" + entry in the hash table, thus we never get to see the real + symbol in a hash traversal. So look at it now. */ + h = (struct elf_link_hash_entry *) h->root.u.i.link; + + info = (struct bfd_link_info *) dat; + htab = elf32_mb_hash_table (info); + + if (htab->elf.dynamic_sections_created + && h->plt.refcount > 0) + { + /* Make sure this symbol is output as a dynamic symbol. + Undefined weak syms won't yet be marked as dynamic. */ + if (h->dynindx == -1 + && !h->forced_local) + { + if (! bfd_elf_link_record_dynamic_symbol (info, h)) + return FALSE; + } + + if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, info->shared, h)) + { + asection *s = htab->splt; + + /* The first entry in .plt is reserved. */ + if (s->size == 0) + s->size = PLT_ENTRY_SIZE; + + h->plt.offset = s->size; + + /* If this symbol is not defined in a regular file, and we are + not generating a shared library, then set the symbol to this + location in the .plt. This is required to make function + pointers compare as equal between the normal executable and + the shared library. */ + if (! info->shared + && !h->def_regular) + { + h->root.u.def.section = s; + h->root.u.def.value = h->plt.offset; + } + + /* Make room for this entry. */ + s->size += PLT_ENTRY_SIZE; + + /* We also need to make an entry in the .got.plt section, which + will be placed in the .got section by the linker script. */ + htab->sgotplt->size += 4; + + /* We also need to make an entry in the .rel.plt section. */ + htab->srelplt->size += sizeof (Elf32_External_Rela); + } + else + { + h->plt.offset = (bfd_vma) -1; + h->needs_plt = 0; + } + } + else + { + h->plt.offset = (bfd_vma) -1; + h->needs_plt = 0; + } + + if (h->got.refcount > 0) + { + asection *s; + + /* Make sure this symbol is output as a dynamic symbol. + Undefined weak syms won't yet be marked as dynamic. */ + if (h->dynindx == -1 + && !h->forced_local) + { + if (! bfd_elf_link_record_dynamic_symbol (info, h)) + return FALSE; + } + + s = htab->sgot; + h->got.offset = s->size; + s->size += 4; + htab->srelgot->size += sizeof (Elf32_External_Rela); + } + else + h->got.offset = (bfd_vma) -1; + + eh = (struct elf32_mb_link_hash_entry *) h; + if (eh->dyn_relocs == NULL) + return TRUE; + + /* In the shared -Bsymbolic case, discard space allocated for + dynamic pc-relative relocs against symbols which turn out to be + defined in regular objects. For the normal shared case, discard + space for pc-relative relocs that have become local due to symbol + visibility changes. */ + + if (info->shared) + { + if (h->def_regular + && (h->forced_local + || info->symbolic)) + { + struct elf32_mb_dyn_relocs **pp; + + for (pp = &eh->dyn_relocs; (p = *pp) != NULL; ) + { + p->count -= p->pc_count; + p->pc_count = 0; + if (p->count == 0) + *pp = p->next; + else + pp = &p->next; + } + } + } + else + { + /* For the non-shared case, discard space for relocs against + symbols which turn out to need copy relocs or are not + dynamic. */ + + if (!h->non_got_ref + && ((h->def_dynamic + && !h->def_regular) + || (htab->elf.dynamic_sections_created + && (h->root.type == bfd_link_hash_undefweak + || h->root.type == bfd_link_hash_undefined)))) + { + /* Make sure this symbol is output as a dynamic symbol. + Undefined weak syms won't yet be marked as dynamic. */ + if (h->dynindx == -1 + && !h->forced_local) + { + if (! bfd_elf_link_record_dynamic_symbol (info, h)) + return FALSE; + } + + /* If that succeeded, we know we'll be keeping all the + relocs. */ + if (h->dynindx != -1) + goto keep; + } + + eh->dyn_relocs = NULL; + + keep: ; + } + + /* Finally, allocate space. */ + for (p = eh->dyn_relocs; p != NULL; p = p->next) + { + asection *sreloc = elf_section_data (p->sec)->sreloc; + sreloc->size += p->count * sizeof (Elf32_External_Rela); + } + + return TRUE; +} + +/* Set the sizes of the dynamic sections. */ + +static bfd_boolean +microblaze_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + struct bfd_link_info *info) +{ + struct elf32_mb_link_hash_table *htab; + bfd *dynobj; + asection *s; + bfd *ibfd; + + htab = elf32_mb_hash_table (info); + dynobj = htab->elf.dynobj; + BFD_ASSERT (dynobj != NULL); + + /* Set up .got offsets for local syms, and space for local dynamic + relocs. */ + for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link_next) + { + bfd_signed_vma *local_got; + bfd_signed_vma *end_local_got; + bfd_size_type locsymcount; + Elf_Internal_Shdr *symtab_hdr; + asection *srel; + + if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour) + continue; + + for (s = ibfd->sections; s != NULL; s = s->next) + { + struct elf32_mb_dyn_relocs *p; + + for (p = ((struct elf32_mb_dyn_relocs *) + elf_section_data (s)->local_dynrel); + p != NULL; + p = p->next) + { + if (!bfd_is_abs_section (p->sec) + && bfd_is_abs_section (p->sec->output_section)) + { + /* Input section has been discarded, either because + it is a copy of a linkonce section or due to + linker script /DISCARD/, so we'll be discarding + the relocs too. */ + } + else if (p->count != 0) + { + srel = elf_section_data (p->sec)->sreloc; + srel->size += p->count * sizeof (Elf32_External_Rela); + if ((p->sec->output_section->flags & SEC_READONLY) != 0) + info->flags |= DF_TEXTREL; + } + } + } + + local_got = elf_local_got_refcounts (ibfd); + if (!local_got) + continue; + + symtab_hdr = &elf_tdata (ibfd)->symtab_hdr; + locsymcount = symtab_hdr->sh_info; + end_local_got = local_got + locsymcount; + s = htab->sgot; + srel = htab->srelgot; + + for (; local_got < end_local_got; ++local_got) + { + if (*local_got > 0) + { + *local_got = s->size; + s->size += 4; + if (info->shared) + srel->size += sizeof (Elf32_External_Rela); + } + else + *local_got = (bfd_vma) -1; + } + } + + /* Allocate global sym .plt and .got entries, and space for global + sym dynamic relocs. */ + elf_link_hash_traverse (elf_hash_table (info), allocate_dynrelocs, info); + + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Make space for the trailing nop in .plt. */ + if (htab->splt->size > 0) + htab->splt->size += 4; + } + + /* The check_relocs and adjust_dynamic_symbol entry points have + determined the sizes of the various dynamic sections. Allocate + memory for them. */ + for (s = dynobj->sections; s != NULL; s = s->next) + { + const char *name; + bfd_boolean strip = FALSE; + + if ((s->flags & SEC_LINKER_CREATED) == 0) + continue; + + /* It's OK to base decisions on the section name, because none + of the dynobj section names depend upon the input files. */ + name = bfd_get_section_name (dynobj, s); + + if (strncmp (name, ".rela", 5) == 0) + { + if (s->size == 0) + { + /* If we don't need this section, strip it from the + output file. This is to handle .rela.bss and + .rela.plt. We must create it in + create_dynamic_sections, because it must be created + before the linker maps input sections to output + sections. The linker does that before + adjust_dynamic_symbol is called, and it is that + function which decides whether anything needs to go + into these sections. */ + strip = TRUE; + } + else + { + /* We use the reloc_count field as a counter if we need + to copy relocs into the output file. */ + s->reloc_count = 0; + } + } + else if (s != htab->splt && s != htab->sgot && s != htab->sgotplt) + { + /* It's not one of our sections, so don't allocate space. */ + continue; + } + + if (strip) + { + s->flags |= SEC_EXCLUDE; + continue; + } + + /* Allocate memory for the section contents. */ + /* FIXME: This should be a call to bfd_alloc not bfd_zalloc. + Unused entries should be reclaimed before the section's contents + are written out, but at the moment this does not happen. Thus in + order to prevent writing out garbage, we initialise the section's + contents to zero. */ + s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size); + if (s->contents == NULL && s->size != 0) + return FALSE; + } + + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Add some entries to the .dynamic section. We fill in the + values later, in microblaze_elf_finish_dynamic_sections, but we + must add the entries now so that we get the correct size for + the .dynamic section. The DT_DEBUG entry is filled in by the + dynamic linker and used by the debugger. */ +#define add_dynamic_entry(TAG, VAL) \ + _bfd_elf_add_dynamic_entry (info, TAG, VAL) + + if (info->executable) + { + if (!add_dynamic_entry (DT_DEBUG, 0)) + return FALSE; + } + + if (!add_dynamic_entry (DT_RELA, 0) + || !add_dynamic_entry (DT_RELASZ, 0) + || !add_dynamic_entry (DT_RELAENT, sizeof (Elf32_External_Rela))) + return FALSE; + + if (htab->splt->size != 0) + { + if (!add_dynamic_entry (DT_PLTGOT, 0) + || !add_dynamic_entry (DT_PLTRELSZ, 0) + || !add_dynamic_entry (DT_PLTREL, DT_RELA) + || !add_dynamic_entry (DT_JMPREL, 0) + || !add_dynamic_entry (DT_BIND_NOW, 1)) + return FALSE; + } + + if (info->flags & DF_TEXTREL) + { + if (!add_dynamic_entry (DT_TEXTREL, 0)) + return FALSE; + } + } +#undef add_dynamic_entry + return TRUE; +} + +/* Finish up dynamic symbol handling. We set the contents of various + dynamic sections here. */ + +static bfd_boolean +microblaze_elf_finish_dynamic_symbol (bfd *output_bfd, + struct bfd_link_info *info, + struct elf_link_hash_entry *h, + Elf_Internal_Sym *sym) +{ + bfd *dynobj; + struct elf32_mb_link_hash_table *htab; + + htab = elf32_mb_hash_table (info); + dynobj = htab->elf.dynobj; + + if (h->plt.offset != (bfd_vma) -1) + { + asection *splt; + asection *srela; + asection *sgotplt; + Elf_Internal_Rela rela; + bfd_byte *loc; + bfd_vma plt_index; + bfd_vma got_offset; + bfd_vma got_addr; + + /* This symbol has an entry in the procedure linkage table. Set + it up. */ + BFD_ASSERT (h->dynindx != -1); + + splt = htab->splt; + srela = htab->srelplt; + sgotplt = htab->sgotplt; + BFD_ASSERT (splt != NULL && srela != NULL && sgotplt != NULL); + + plt_index = h->plt.offset / PLT_ENTRY_SIZE - 1; /* first entry reserved. */ + got_offset = (plt_index + 3) * 4; /* 3 reserved ??? */ + got_addr = got_offset; + + /* For non-PIC objects we need absolute address of the GOT entry. */ + if (!info->shared) + got_addr += htab->sgotplt->output_section->vma + sgotplt->output_offset; + + /* Fill in the entry in the procedure linkage table. */ + bfd_put_32 (output_bfd, PLT_ENTRY_WORD_0 + ((got_addr >> 16) & 0xffff), + splt->contents + h->plt.offset); + if (info->shared) + bfd_put_32 (output_bfd, PLT_ENTRY_WORD_1 + (got_addr & 0xffff), + splt->contents + h->plt.offset + 4); + else + bfd_put_32 (output_bfd, PLT_ENTRY_WORD_1_NOPIC + (got_addr & 0xffff), + splt->contents + h->plt.offset + 4); + bfd_put_32 (output_bfd, (bfd_vma) PLT_ENTRY_WORD_2, + splt->contents + h->plt.offset + 8); + bfd_put_32 (output_bfd, (bfd_vma) PLT_ENTRY_WORD_3, + splt->contents + h->plt.offset + 12); + + /* Any additions to the .got section??? */ + /* bfd_put_32 (output_bfd, + splt->output_section->vma + splt->output_offset + h->plt.offset + 4, + sgotplt->contents + got_offset); */ + + /* Fill in the entry in the .rela.plt section. */ + rela.r_offset = (sgotplt->output_section->vma + + sgotplt->output_offset + + got_offset); + rela.r_info = ELF32_R_INFO (h->dynindx, R_MICROBLAZE_JUMP_SLOT); + rela.r_addend = 0; + loc = srela->contents; + loc += plt_index * sizeof (Elf32_External_Rela); + bfd_elf32_swap_reloca_out (output_bfd, &rela, loc); + + if (!h->def_regular) + { + /* Mark the symbol as undefined, rather than as defined in + the .plt section. Zero the value. */ + sym->st_shndx = SHN_UNDEF; + sym->st_value = 0; + } + } + + if (h->got.offset != (bfd_vma) -1) + { + asection *sgot; + asection *srela; + Elf_Internal_Rela rela; + bfd_byte *loc; + + /* This symbol has an entry in the global offset table. Set it + up. */ + + sgot = htab->sgot; + srela = htab->srelgot; + BFD_ASSERT (sgot != NULL && srela != NULL); + + rela.r_offset = (sgot->output_section->vma + + sgot->output_offset + + (h->got.offset &~ (bfd_vma) 1)); + + /* If this is a -Bsymbolic link, and the symbol is defined + locally, we just want to emit a RELATIVE reloc. Likewise if + the symbol was forced to be local because of a version file. + The entry in the global offset table will already have been + initialized in the relocate_section function. */ + if (info->shared + && (info->symbolic || h->dynindx == -1) + && h->def_regular) + { + asection *sec = h->root.u.def.section; + rela.r_info = ELF32_R_INFO (0, R_MICROBLAZE_REL); + rela.r_addend = (h->root.u.def.value + + sec->output_section->vma + + sec->output_offset); + } + else + { + rela.r_info = ELF32_R_INFO (h->dynindx, R_MICROBLAZE_GLOB_DAT); + rela.r_addend = 0; + } + + bfd_put_32 (output_bfd, (bfd_vma) 0, + sgot->contents + (h->got.offset &~ (bfd_vma) 1)); + loc = srela->contents; + loc += srela->reloc_count++ * sizeof (Elf32_External_Rela); + bfd_elf32_swap_reloca_out (output_bfd, &rela, loc); + } + + if (h->needs_copy) + { + asection *s; + Elf_Internal_Rela rela; + bfd_byte *loc; + + /* This symbols needs a copy reloc. Set it up. */ + + BFD_ASSERT (h->dynindx != -1); + + s = bfd_get_section_by_name (h->root.u.def.section->owner, + ".rela.bss"); + BFD_ASSERT (s != NULL); + + rela.r_offset = (h->root.u.def.value + + h->root.u.def.section->output_section->vma + + h->root.u.def.section->output_offset); + rela.r_info = ELF32_R_INFO (h->dynindx, R_MICROBLAZE_COPY); + rela.r_addend = 0; + loc = s->contents + s->reloc_count++ * sizeof (Elf32_External_Rela); + bfd_elf32_swap_reloca_out (output_bfd, &rela, loc); + } + + /* Mark some specially defined symbols as absolute. */ + if (strcmp (h->root.root.string, "_DYNAMIC") == 0 + || strcmp (h->root.root.string, "_GLOBAL_OFFSET_TABLE_") == 0 + || strcmp (h->root.root.string, "_PROCEDURE_LINKAGE_TABLE_") == 0) + sym->st_shndx = SHN_ABS; + + return TRUE; +} + + +/* Finish up the dynamic sections. */ + +static bfd_boolean +microblaze_elf_finish_dynamic_sections (bfd *output_bfd, + struct bfd_link_info *info) +{ + bfd *dynobj; + asection *sdyn, *sgot; + struct elf32_mb_link_hash_table *htab; + + htab = elf32_mb_hash_table (info); + dynobj = htab->elf.dynobj; + + sdyn = bfd_get_section_by_name (dynobj, ".dynamic"); + + if (htab->elf.dynamic_sections_created) + { + asection *splt; + Elf32_External_Dyn *dyncon, *dynconend; + + splt = bfd_get_section_by_name (dynobj, ".plt"); + BFD_ASSERT (splt != NULL && sdyn != NULL); + + dyncon = (Elf32_External_Dyn *) sdyn->contents; + dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size); + for (; dyncon < dynconend; dyncon++) + { + Elf_Internal_Dyn dyn; + const char *name; + bfd_boolean size; + + bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn); + + switch (dyn.d_tag) + { + case DT_PLTGOT: name = ".got.plt"; size = FALSE; break; + case DT_PLTRELSZ: name = ".rela.plt"; size = TRUE; break; + case DT_JMPREL: name = ".rela.plt"; size = FALSE; break; + case DT_RELA: name = ".rela.dyn"; size = FALSE; break; + case DT_RELASZ: name = ".rela.dyn"; size = TRUE; break; + default: name = NULL; size = FALSE; break; + } + + if (name != NULL) + { + asection *s; + + s = bfd_get_section_by_name (output_bfd, name); + if (s == NULL) + dyn.d_un.d_val = 0; + else + { + if (! size) + dyn.d_un.d_ptr = s->vma; + else + dyn.d_un.d_val = s->size; + } + bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon); + } + } + + /* Clear the first entry in the procedure linkage table, + and put a nop in the last four bytes. */ + if (splt->size > 0) + { + memset (splt->contents, 0, PLT_ENTRY_SIZE); + bfd_put_32 (output_bfd, (bfd_vma) 0x80000000 /* nop. */, + splt->contents + splt->size - 4); + } + + elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4; + } + + /* Set the first entry in the global offset table to the address of + the dynamic section. */ + sgot = bfd_get_section_by_name (dynobj, ".got.plt"); + if (sgot && sgot->size > 0) + { + if (sdyn == NULL) + bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents); + else + bfd_put_32 (output_bfd, + sdyn->output_section->vma + sdyn->output_offset, + sgot->contents); + elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4; + } + + if (htab->sgot && htab->sgot->size > 0) + elf_section_data (htab->sgot->output_section)->this_hdr.sh_entsize = 4; + + return TRUE; +} + +/* Hook called by the linker routine which adds symbols from an object + file. We use it to put .comm items in .sbss, and not .bss. */ + +static bfd_boolean +microblaze_elf_add_symbol_hook (bfd *abfd, + struct bfd_link_info *info, + Elf_Internal_Sym *sym, + const char **namep ATTRIBUTE_UNUSED, + flagword *flagsp ATTRIBUTE_UNUSED, + asection **secp, + bfd_vma *valp) +{ + if (sym->st_shndx == SHN_COMMON + && !info->relocatable + && sym->st_size <= elf_gp_size (abfd)) + { + /* Common symbols less than or equal to -G nn bytes are automatically + put into .sbss. */ + *secp = bfd_make_section_anyway (abfd, ".sbss"); + if (*secp == NULL + || ! bfd_set_section_flags (abfd, *secp, SEC_IS_COMMON)) + return FALSE; + + *valp = sym->st_size; + } + + return TRUE; +} + + +#define TARGET_BIG_SYM bfd_elf32_microblaze_vec +#define TARGET_BIG_NAME "elf32-microblaze" + +#define ELF_ARCH bfd_arch_microblaze +#define ELF_MACHINE_CODE EM_MICROBLAZE +#define ELF_MACHINE_ALT1 EM_MICROBLAZE_OLD +#define ELF_MAXPAGESIZE 0x4 /* 4k, if we ever have 'em. */ +#define elf_info_to_howto microblaze_elf_info_to_howto +#define elf_info_to_howto_rel NULL + +#define bfd_elf32_bfd_reloc_type_lookup microblaze_elf_reloc_type_lookup +#define bfd_elf32_bfd_is_local_label_name microblaze_elf_is_local_label_name +#define elf_backend_relocate_section microblaze_elf_relocate_section +#define bfd_elf32_bfd_relax_section microblaze_elf_relax_section +#define bfd_elf32_bfd_reloc_name_lookup microblaze_elf_reloc_name_lookup + +#define elf_backend_gc_mark_hook microblaze_elf_gc_mark_hook +#define elf_backend_gc_sweep_hook microblaze_elf_gc_sweep_hook +#define elf_backend_check_relocs microblaze_elf_check_relocs +#define elf_backend_copy_indirect_symbol microblaze_elf_copy_indirect_symbol +#define bfd_elf32_bfd_link_hash_table_create microblaze_elf_link_hash_table_create +#define elf_backend_can_gc_sections 1 +#define elf_backend_can_refcount 1 +#define elf_backend_want_got_plt 1 +#define elf_backend_plt_readonly 1 +#define elf_backend_got_header_size 12 +#define elf_backend_rela_normal 1 + +#define elf_backend_adjust_dynamic_symbol microblaze_elf_adjust_dynamic_symbol +#define elf_backend_create_dynamic_sections microblaze_elf_create_dynamic_sections +#define elf_backend_finish_dynamic_sections microblaze_elf_finish_dynamic_sections +#define elf_backend_finish_dynamic_symbol microblaze_elf_finish_dynamic_symbol +#define elf_backend_size_dynamic_sections microblaze_elf_size_dynamic_sections +#define elf_backend_add_symbol_hook microblaze_elf_add_symbol_hook + +#include "elf32-target.h" diff --git a/bfd/libbfd.h b/bfd/libbfd.h index 28aa045..0a1cdb1 100644 --- a/bfd/libbfd.h +++ b/bfd/libbfd.h @@ -2072,6 +2072,18 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_LM32_RELATIVE", "BFD_RELOC_MACH_O_SECTDIFF", "BFD_RELOC_MACH_O_PAIR", + "BFD_RELOC_MICROBLAZE_32_LO", + "BFD_RELOC_MICROBLAZE_32_LO_PCREL", + "BFD_RELOC_MICROBLAZE_32_ROSDA", + "BFD_RELOC_MICROBLAZE_32_RWSDA", + "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM", + "BFD_RELOC_MICROBLAZE_64_NONE", + "BFD_RELOC_MICROBLAZE_64_GOTPC", + "BFD_RELOC_MICROBLAZE_64_GOT", + "BFD_RELOC_MICROBLAZE_64_PLT", + "BFD_RELOC_MICROBLAZE_64_GOTOFF", + "BFD_RELOC_MICROBLAZE_32_GOTOFF", + "BFD_RELOC_MICROBLAZE_COPY", "@@overflow: BFD_RELOC_UNUSED@@", }; #endif diff --git a/bfd/reloc.c b/bfd/reloc.c index 2da43f3..545b389 100644 --- a/bfd/reloc.c +++ b/bfd/reloc.c @@ -5193,6 +5193,74 @@ ENUM ENUMDOC Mach-O generic relocations. +ENUM + BFD_RELOC_MICROBLAZE_32_LO +ENUMDOC + This is a 32 bit reloc for the microblaze that stores the + low 16 bits of a value +ENUM + BFD_RELOC_MICROBLAZE_32_LO_PCREL +ENUMDOC + This is a 32 bit pc-relative reloc for the microblaze that + stores the low 16 bits of a value +ENUM + BFD_RELOC_MICROBLAZE_32_ROSDA +ENUMDOC + This is a 32 bit reloc for the microblaze that stores a + value relative to the read-only small data area anchor +ENUM + BFD_RELOC_MICROBLAZE_32_RWSDA +ENUMDOC + This is a 32 bit reloc for the microblaze that stores a + value relative to the read-write small data area anchor +ENUM + BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM +ENUMDOC + This is a 32 bit reloc for the microblaze to handle + expressions of the form "Symbol Op Symbol" +ENUM + BFD_RELOC_MICROBLAZE_64_NONE +ENUMDOC + This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). No relocation is + done here - only used for relaxing +ENUM + BFD_RELOC_MICROBLAZE_64_GOTPC +ENUMDOC + This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). The relocation is + PC-relative GOT offset +ENUM + BFD_RELOC_MICROBLAZE_64_GOT +ENUMDOC + This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). The relocation is + GOT offset +ENUM + BFD_RELOC_MICROBLAZE_64_PLT +ENUMDOC + This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). The relocation is + PC-relative offset into PLT +ENUM + BFD_RELOC_MICROBLAZE_64_GOTOFF +ENUMDOC + This is a 64 bit reloc that stores the 32 bit GOT relative + value in two words (with an imm instruction). The relocation is + relative offset from _GLOBAL_OFFSET_TABLE_ +ENUM + BFD_RELOC_MICROBLAZE_32_GOTOFF +ENUMDOC + This is a 32 bit reloc that stores the 32 bit GOT relative + value in a word. The relocation is relative offset from + _GLOBAL_OFFSET_TABLE_ +ENUM + BFD_RELOC_MICROBLAZE_COPY +ENUMDOC + This is used to tell the dynamic linker to copy the value out of + the dynamic object into the runtime process image. + + ENDSENUM BFD_RELOC_UNUSED CODE_FRAGMENT diff --git a/bfd/section.c b/bfd/section.c index dc8225f..592da69 100644 --- a/bfd/section.c +++ b/bfd/section.c @@ -428,6 +428,13 @@ CODE_FRAGMENT . section size calculated on a previous linker relaxation pass. *} . bfd_size_type rawsize; . +. {* Relaxation table. *} +. struct relax_table *relax; +. +. {* Count of used relaxation table entries. *} +. int relax_count; +. +. . {* If this section is going to be output, then this value is the . offset in *bytes* into the output section of the first byte in the . input section (byte ==> smallest addressable unit on the @@ -517,6 +524,17 @@ CODE_FRAGMENT . } map_head, map_tail; .} asection; . +.{* Relax table contains information about instructions which can +. be removed by relaxation -- replacing a long address with a +. short address. *} +.struct relax_table { +. {* Address where bytes may be deleted. *} +. bfd_vma addr; +. +. {* Number of bytes to be deleted. *} +. int size; +.}; +. .{* These sections are global, and are managed by BFD. The application . and target back end are not permitted to change the values in . these sections. New code should use the section_ptr macros rather @@ -652,8 +670,8 @@ CODE_FRAGMENT . {* has_tls_get_addr_call, has_gp_reloc, need_finalize_relax, *} \ . 0, 0, 0, \ . \ -. {* reloc_done, vma, lma, size, rawsize *} \ -. 0, 0, 0, 0, 0, \ +. {* reloc_done, vma, lma, size, rawsize, relax, relax_count, *} \ +. 0, 0, 0, 0, 0, 0, 0, \ . \ . {* output_offset, output_section, alignment_power, *} \ . 0, (struct bfd_section *) &SEC, 0, \ diff --git a/bfd/targets.c b/bfd/targets.c index 1e5d244..ce01309 100644 --- a/bfd/targets.c +++ b/bfd/targets.c @@ -625,6 +625,7 @@ extern const bfd_target bfd_elf32_mcore_big_vec; extern const bfd_target bfd_elf32_mcore_little_vec; extern const bfd_target bfd_elf32_mep_vec; extern const bfd_target bfd_elf32_mep_little_vec; +extern const bfd_target bfd_elf32_microblaze_vec; extern const bfd_target bfd_elf32_mn10200_vec; extern const bfd_target bfd_elf32_mn10300_vec; extern const bfd_target bfd_elf32_mt_vec; @@ -959,6 +960,7 @@ static const bfd_target * const _bfd_target_vector[] = &bfd_elf32_mcore_big_vec, &bfd_elf32_mcore_little_vec, &bfd_elf32_mep_vec, + &bfd_elf32_microblaze_vec, &bfd_elf32_mn10200_vec, &bfd_elf32_mn10300_vec, &bfd_elf32_mt_vec, diff --git a/binutils/MAINTAINERS b/binutils/MAINTAINERS index c2b7b70..6d31632 100644 --- a/binutils/MAINTAINERS +++ b/binutils/MAINTAINERS @@ -93,6 +93,7 @@ responsibility among the other maintainers. MACH-O Tristan Gingold <gingold@adacore.com> MAXQ Inderpreet Singh <inderpreetb@noida.hcltech.com> MEP Dave Brolley <brolley@redhat.com> + MICROBLAZE Michael Eager <eager@eagercon.com> MIPS Eric Christopher <echristo@apple.com> MMIX Hans-Peter Nilsson <hp@bitrange.com> MN10300 Eric Christopher <echristo@apple.com> diff --git a/binutils/readelf.c b/binutils/readelf.c index 8097121..9e8f48f 100644 --- a/binutils/readelf.c +++ b/binutils/readelf.c @@ -119,6 +119,7 @@ #include "elf/m68hc11.h" #include "elf/mcore.h" #include "elf/mep.h" +#include "elf/microblaze.h" #include "elf/mips.h" #include "elf/mmix.h" #include "elf/mn10200.h" @@ -614,6 +615,8 @@ guess_is_rela (unsigned int e_machine) case EM_XSTORMY16: case EM_XTENSA: case EM_XTENSA_OLD: + case EM_MICROBLAZE: + case EM_MICROBLAZE_OLD: return TRUE; case EM_68HC05: @@ -1197,6 +1200,11 @@ dump_relocations (FILE * file, case EM_CR16_OLD: rtype = elf_cr16_reloc_type (type); break; + + case EM_MICROBLAZE: + case EM_MICROBLAZE_OLD: + rtype = elf_microblaze_reloc_type (type); + break; } if (rtype == NULL) @@ -1865,6 +1873,8 @@ get_machine_name (unsigned e_machine) case EM_CYGNUS_MEP: return "Toshiba MeP Media Engine"; case EM_CR16: case EM_CR16_OLD: return "National Semiconductor's CR16"; + case EM_MICROBLAZE: return "Xilinx MicroBlaze"; + case EM_MICROBLAZE_OLD: return "Xilinx MicroBlaze"; default: snprintf (buff, sizeof (buff), _("<unknown>: 0x%x"), e_machine); return buff; diff --git a/gas/ChangeLog b/gas/ChangeLog index fc5e454..5f7fbb7 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,20 @@ +2009-08-06 Michael Eager <eager@eagercon.com> + + * Makefile.am: add microblaze to CPU_TYPES, config/tc-microblaze.c to + TARGET_CPU_CFILES, config/tc-microblaze.h to TARGET_CPU_HFILES, add + DEP_microblaze_elf target. + * Makefile.in: Regenerate. + * config/tc-microblaze.c: Add MicroBlaze assembler. + * config/tc-microblaze.h: Add header for tc-microblaze.c. + * configure.in: Add microblaze target. + * configure: Regenerate. + * configure.tgt: Same. + * doc/Makefile.am: Add c-microblaze.texi to CPU_DOCS. + * doc/Makefile.in: Same. + * doc/all.texi: Set MICROBLAZE. + * doc/as.texinfo: Add MicroBlaze doc links. + * doc/c-microblaze.texi: New MicroBlaze docs. + 2009-08-06 Nick Clifton <nickc@redhat.com> * config/tc-arm.c (md_assemble): Call mapping_state from inside a diff --git a/gas/Makefile.am b/gas/Makefile.am index 5501325..0ceb546 100644 --- a/gas/Makefile.am +++ b/gas/Makefile.am @@ -72,6 +72,7 @@ CPU_TYPES = \ maxq \ mcore \ mep \ + microblaze \ mips \ mmix \ mn10200 \ @@ -273,6 +274,7 @@ TARGET_CPU_CFILES = \ config/tc-maxq.c \ config/tc-mcore.c \ config/tc-mep.c \ + config/tc-microblaze.c \ config/tc-mips.c \ config/tc-mmix.c \ config/tc-mn10200.c \ @@ -334,6 +336,7 @@ TARGET_CPU_HFILES = \ config/tc-maxq.h \ config/tc-mcore.h \ config/tc-mep.h \ + config/tc-microblaze.h \ config/tc-mips.h \ config/tc-mmix.h \ config/tc-mn10200.h \ @@ -1788,6 +1791,19 @@ DEPTC_mep_elf = \ cgen.h \ dwarf2dbg.h \ subsegs.h +DEPTC_microblaze_elf = \ + $(srcdir)/config/obj-elf.h \ + $(BFDDIR)/elf-bfd.h \ + $(INCDIR)/elf/common.h \ + $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h \ + $(INCDIR)/bfdlink.h \ + $(srcdir)/config/tc-microblaze.h \ + $(INCDIR)/obstack.h \ + $(srcdir)/../opcodes/microblaze-opc.h \ + $(INCDIR)/elf/reloc-macros.h \ + emul.h \ + subsegs.h DEPTC_mips_coff = \ $(BFDDIR)/elf-bfd.h \ $(BFDDIR)/libcoff.h \ @@ -3921,6 +3937,14 @@ DEP_mep_elf = \ $(srcdir)/config/obj-elf.h \ $(srcdir)/config/tc-mep.h \ dwarf2dbg.h +DEP_microblaze_elf = \ + $(srcdir)/config/obj-elf.h \ + $(BFDDIR)/elf-bfd.h \ + $(INCDIR)/elf/common.h \ + $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h \ + $(INCDIR)/bfdlink.h \ + $(srcdir)/config/tc-microblaze.h DEP_mips_coff = \ $(BFDDIR)/libcoff.h \ $(INCDIR)/bfdlink.h \ diff --git a/gas/Makefile.in b/gas/Makefile.in index 5afa750..e0dfd98 100644 --- a/gas/Makefile.in +++ b/gas/Makefile.in @@ -335,6 +335,7 @@ CPU_TYPES = \ maxq \ mcore \ mep \ + microblaze \ mips \ mmix \ mn10200 \ @@ -534,6 +535,7 @@ TARGET_CPU_CFILES = \ config/tc-maxq.c \ config/tc-mcore.c \ config/tc-mep.c \ + config/tc-microblaze.c \ config/tc-mips.c \ config/tc-mmix.c \ config/tc-mn10200.c \ @@ -595,6 +597,7 @@ TARGET_CPU_HFILES = \ config/tc-maxq.h \ config/tc-mcore.h \ config/tc-mep.h \ + config/tc-microblaze.h \ config/tc-mips.h \ config/tc-mmix.h \ config/tc-mn10200.h \ @@ -1555,6 +1558,20 @@ DEPTC_mep_elf = \ dwarf2dbg.h \ subsegs.h +DEPTC_microblaze_elf = \ + $(srcdir)/config/obj-elf.h \ + $(BFDDIR)/elf-bfd.h \ + $(INCDIR)/elf/common.h \ + $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h \ + $(INCDIR)/bfdlink.h \ + $(srcdir)/config/tc-microblaze.h \ + $(INCDIR)/obstack.h \ + $(srcdir)/../opcodes/microblaze-opc.h \ + $(INCDIR)/elf/reloc-macros.h \ + emul.h \ + subsegs.h + DEPTC_mips_coff = \ $(BFDDIR)/elf-bfd.h \ $(BFDDIR)/libcoff.h \ @@ -3850,6 +3867,15 @@ DEP_mep_elf = \ $(srcdir)/config/tc-mep.h \ dwarf2dbg.h +DEP_microblaze_elf = \ + $(srcdir)/config/obj-elf.h \ + $(BFDDIR)/elf-bfd.h \ + $(INCDIR)/elf/common.h \ + $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h \ + $(INCDIR)/bfdlink.h \ + $(srcdir)/config/tc-microblaze.h + DEP_mips_coff = \ $(BFDDIR)/libcoff.h \ $(INCDIR)/bfdlink.h \ diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c new file mode 100644 index 0000000..476e408 --- /dev/null +++ b/gas/config/tc-microblaze.c @@ -0,0 +1,2370 @@ +/* tc-microblaze.c -- Assemble code for Xilinx MicroBlaze + + Copyright 2009 Free Software Foundation. + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include <stdio.h> +#include "as.h" +#include "bfd.h" +#include "subsegs.h" +#define DEFINE_TABLE +#include "../opcodes/microblaze-opc.h" +#include "../opcodes/microblaze-opcm.h" +#include <ctype.h> +#include <string.h> +#include <dwarf2dbg.h> +#include "aout/stab_gnu.h" + +#ifndef streq +#define streq(a,b) (strcmp (a, b) == 0) +#endif + +void microblaze_generate_symbol (char *sym); +static bfd_boolean check_spl_reg (unsigned *); + +/* Several places in this file insert raw instructions into the + object. They should generate the instruction + and then use these four macros to crack the instruction value into + the appropriate byte values. */ +#define INST_BYTE0(x) (target_big_endian ? (((x) >> 24) & 0xFF) : ((x) & 0xFF)) +#define INST_BYTE1(x) (target_big_endian ? (((x) >> 16) & 0xFF) : (((x) >> 8) & 0xFF)) +#define INST_BYTE2(x) (target_big_endian ? (((x) >> 8) & 0xFF) : (((x) >> 16) & 0xFF)) +#define INST_BYTE3(x) (target_big_endian ? ((x) & 0xFF) : (((x) >> 24) & 0xFF)) + +/* This array holds the chars that always start a comment. If the + pre-processor is disabled, these aren't very useful. */ +const char comment_chars[] = "#"; + +const char line_separator_chars[] = ";"; + +/* This array holds the chars that only start a comment at the beginning of + a line. */ +const char line_comment_chars[] = "#"; + +const int md_reloc_size = 8; /* Size of relocation record. */ + +/* Chars that can be used to separate mant + from exp in floating point numbers. */ +const char EXP_CHARS[] = "eE"; + +/* Chars that mean this number is a floating point constant + As in 0f12.456 + or 0d1.2345e12. */ +const char FLT_CHARS[] = "rRsSfFdDxXpP"; + +/* INST_PC_OFFSET and INST_NO_OFFSET are 0 and 1. */ +#define UNDEFINED_PC_OFFSET 2 +#define DEFINED_ABS_SEGMENT 3 +#define DEFINED_PC_OFFSET 4 +#define DEFINED_RO_SEGMENT 5 +#define DEFINED_RW_SEGMENT 6 +#define LARGE_DEFINED_PC_OFFSET 7 +#define GOT_OFFSET 8 +#define PLT_OFFSET 9 +#define GOTOFF_OFFSET 10 + + +/* Initialize the relax table. */ +const relax_typeS md_relax_table[] = +{ + { 1, 1, 0, 0 }, /* 0: Unused. */ + { 1, 1, 0, 0 }, /* 1: Unused. */ + { 1, 1, 0, 0 }, /* 2: Unused. */ + { 1, 1, 0, 0 }, /* 3: Unused. */ + { 32767, -32768, INST_WORD_SIZE, LARGE_DEFINED_PC_OFFSET }, /* 4: DEFINED_PC_OFFSET. */ + { 1, 1, 0, 0 }, /* 5: Unused. */ + { 1, 1, 0, 0 }, /* 6: Unused. */ + { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 }, /* 7: LARGE_DEFINED_PC_OFFSET. */ + { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 }, /* 8: GOT_OFFSET. */ + { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 }, /* 9: PLT_OFFSET. */ + { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 }, /* 10: GOTOFF_OFFSET. */ +}; + +static struct hash_control * opcode_hash_control; /* Opcode mnemonics. */ + +static segT sbss_segment = 0; /* Small bss section. */ +static segT sbss2_segment = 0; /* Section not used. */ +static segT sdata_segment = 0; /* Small data section. */ +static segT sdata2_segment = 0; /* Small read-only section. */ +static segT rodata_segment = 0; /* read-only section. */ + +/* Generate a symbol for stabs information. */ + +void +microblaze_generate_symbol (char *sym) +{ +#define MICROBLAZE_FAKE_LABEL_NAME "XL0\001" + static int microblaze_label_count; + sprintf (sym, "%sL%d", MICROBLAZE_FAKE_LABEL_NAME, microblaze_label_count); + ++microblaze_label_count; +} + +/* Handle the section changing pseudo-ops. */ + +static void +microblaze_s_text (int ignore ATTRIBUTE_UNUSED) +{ +#ifdef OBJ_ELF + obj_elf_text (ignore); +#else + s_text (ignore); +#endif +} + +static void +microblaze_s_data (int ignore ATTRIBUTE_UNUSED) +{ +#ifdef OBJ_ELF + obj_elf_change_section (".data", SHT_PROGBITS, SHF_ALLOC+SHF_WRITE, 0, 0, 0, 0); +#else + s_data (ignore); +#endif +} + +/* Things in the .sdata segment are always considered to be in the small data section. */ + +static void +microblaze_s_sdata (int ignore ATTRIBUTE_UNUSED) +{ +#ifdef OBJ_ELF + obj_elf_change_section (".sdata", SHT_PROGBITS, SHF_ALLOC+SHF_WRITE, 0, 0, 0, 0); +#else + s_data (ignore); +#endif +} + +/* Pseudo op to make file scope bss items. */ + +static void +microblaze_s_lcomm (int xxx ATTRIBUTE_UNUSED) +{ + char *name; + char c; + char *p; + offsetT size; + symbolS *symbolP; + offsetT align; + segT old_sec; + int old_subsec; + char *pfrag; + int align2; + segT current_seg = now_seg; + subsegT current_subseg = now_subseg; + + name = input_line_pointer; + c = get_symbol_end (); + + /* Just after name is now '\0'. */ + p = input_line_pointer; + *p = c; + SKIP_WHITESPACE (); + if (*input_line_pointer != ',') + { + as_bad (_("Expected comma after symbol-name: rest of line ignored.")); + ignore_rest_of_line (); + return; + } + + input_line_pointer++; /* skip ',' */ + if ((size = get_absolute_expression ()) < 0) + { + as_warn (_(".COMMon length (%ld.) <0! Ignored."), (long) size); + ignore_rest_of_line (); + return; + } + + /* The third argument to .lcomm is the alignment. */ + if (*input_line_pointer != ',') + align = 8; + else + { + ++input_line_pointer; + align = get_absolute_expression (); + if (align <= 0) + { + as_warn (_("ignoring bad alignment")); + align = 8; + } + } + + *p = 0; + symbolP = symbol_find_or_make (name); + *p = c; + + if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) + { + as_bad (_("Ignoring attempt to re-define symbol `%s'."), + S_GET_NAME (symbolP)); + ignore_rest_of_line (); + return; + } + + if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size) + { + as_bad (_("Length of .lcomm \"%s\" is already %ld. Not changed to %ld."), + S_GET_NAME (symbolP), + (long) S_GET_VALUE (symbolP), + (long) size); + + ignore_rest_of_line (); + return; + } + + /* Allocate_bss. */ + old_sec = now_seg; + old_subsec = now_subseg; + if (align) + { + /* Convert to a power of 2 alignment. */ + for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2); + if (align != 1) + { + as_bad (_("Common alignment not a power of 2")); + ignore_rest_of_line (); + return; + } + } + else + align2 = 0; + + record_alignment (current_seg, align2); + subseg_set (current_seg, current_subseg); + if (align2) + frag_align (align2, 0, 0); + if (S_GET_SEGMENT (symbolP) == current_seg) + symbol_get_frag (symbolP)->fr_symbol = 0; + symbol_set_frag (symbolP, frag_now); + pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size, + (char *) 0); + *pfrag = 0; + S_SET_SIZE (symbolP, size); + S_SET_SEGMENT (symbolP, current_seg); + subseg_set (current_seg, current_subseg); + demand_empty_rest_of_line (); +} + +static void +microblaze_s_rdata (int localvar) +{ +#ifdef OBJ_ELF + if (localvar == 0) + { + /* rodata. */ + obj_elf_change_section (".rodata", SHT_PROGBITS, SHF_ALLOC, 0, 0, 0, 0); + if (rodata_segment == 0) + rodata_segment = subseg_new (".rodata", 0); + } + else + { + /* 1 .sdata2. */ + obj_elf_change_section (".sdata2", SHT_PROGBITS, SHF_ALLOC, 0, 0, 0, 0); + } +#else + s_data (ignore); +#endif +} + +static void +microblaze_s_bss (int localvar) +{ +#ifdef OBJ_ELF + if (localvar == 0) /* bss. */ + obj_elf_change_section (".bss", SHT_NOBITS, SHF_ALLOC+SHF_WRITE, 0, 0, 0, 0); + else if (localvar == 1) + { + /* sbss. */ + obj_elf_change_section (".sbss", SHT_NOBITS, SHF_ALLOC+SHF_WRITE, 0, 0, 0, 0); + if (sbss_segment == 0) + sbss_segment = subseg_new (".sbss", 0); + } +#else + s_data (ignore); +#endif +} + +/* endp_p is always 1 as this func is called only for .end <funcname> + This func consumes the <funcname> and calls regular processing + s_func(1) with arg 1 (1 for end). */ + +static void +microblaze_s_func (int end_p ATTRIBUTE_UNUSED) +{ + *input_line_pointer = get_symbol_end (); + s_func (1); +} + +/* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ + +static void +microblaze_s_weakext (int ignore ATTRIBUTE_UNUSED) +{ + char *name; + int c; + symbolS *symbolP; + expressionS exp; + + name = input_line_pointer; + c = get_symbol_end (); + symbolP = symbol_find_or_make (name); + S_SET_WEAK (symbolP); + *input_line_pointer = c; + + SKIP_WHITESPACE (); + + if (!is_end_of_line[(unsigned char) *input_line_pointer]) + { + if (S_IS_DEFINED (symbolP)) + { + as_bad ("Ignoring attempt to redefine symbol `%s'.", + S_GET_NAME (symbolP)); + ignore_rest_of_line (); + return; + } + + if (*input_line_pointer == ',') + { + ++input_line_pointer; + SKIP_WHITESPACE (); + } + + expression (&exp); + if (exp.X_op != O_symbol) + { + as_bad ("bad .weakext directive"); + ignore_rest_of_line (); + return; + } + symbol_set_value_expression (symbolP, &exp); + } + + demand_empty_rest_of_line (); +} + +/* This table describes all the machine specific pseudo-ops the assembler + has to support. The fields are: + Pseudo-op name without dot + Function to call to execute this pseudo-op + Integer arg to pass to the function. */ +/* If the pseudo-op is not found in this table, it searches in the obj-elf.c, + and then in the read.c table. */ +const pseudo_typeS md_pseudo_table[] = +{ + {"lcomm", microblaze_s_lcomm, 1}, + {"data", microblaze_s_data, 0}, + {"data8", cons, 1}, /* Same as byte. */ + {"data16", cons, 2}, /* Same as hword. */ + {"data32", cons, 4}, /* Same as word. */ + {"ent", s_func, 0}, /* Treat ent as function entry point. */ + {"end", microblaze_s_func, 1}, /* Treat end as function end point. */ + {"gpword", s_rva, 4}, /* gpword label => store resolved label address in data section. */ + {"weakext", microblaze_s_weakext, 0}, + {"rodata", microblaze_s_rdata, 0}, + {"sdata2", microblaze_s_rdata, 1}, + {"sdata", microblaze_s_sdata, 0}, + {"bss", microblaze_s_bss, 0}, + {"sbss", microblaze_s_bss, 1}, + {"text", microblaze_s_text, 0}, + {"word", cons, 4}, + {"frame", s_ignore, 0}, + {"mask", s_ignore, 0}, /* Emitted by gcc. */ + {NULL, NULL, 0} +}; + +/* This function is called once, at assembler startup time. This should + set up all the tables, etc that the MD part of the assembler needs. */ + +void +md_begin (void) +{ + struct op_code_struct * opcode; + + opcode_hash_control = hash_new (); + + /* Insert unique names into hash table. */ + for (opcode = opcodes; opcode->name; opcode ++) + hash_insert (opcode_hash_control, opcode->name, (char *) opcode); +} + +/* Try to parse a reg name. */ + +static char * +parse_reg (char * s, unsigned * reg) +{ + unsigned tmpreg = 0; + + /* Strip leading whitespace. */ + while (isspace (* s)) + ++ s; + + if (strncasecmp (s, "rpc", 3) == 0) + { + *reg = REG_PC; + return s + 3; + } + else if (strncasecmp (s, "rmsr", 4) == 0) + { + *reg = REG_MSR; + return s + 4; + } + else if (strncasecmp (s, "rear", 4) == 0) + { + *reg = REG_EAR; + return s + 4; + } + else if (strncasecmp (s, "resr", 4) == 0) + { + *reg = REG_ESR; + return s + 4; + } + else if (strncasecmp (s, "rfsr", 4) == 0) + { + *reg = REG_FSR; + return s + 4; + } + else if (strncasecmp (s, "rbtr", 4) == 0) + { + *reg = REG_BTR; + return s + 4; + } + else if (strncasecmp (s, "redr", 4) == 0) + { + *reg = REG_EDR; + return s + 4; + } + /* MMU registers start. */ + else if (strncasecmp (s, "rpid", 4) == 0) + { + *reg = REG_PID; + return s + 4; + } + else if (strncasecmp (s, "rzpr", 4) == 0) + { + *reg = REG_ZPR; + return s + 4; + } + else if (strncasecmp (s, "rtlbx", 5) == 0) + { + *reg = REG_TLBX; + return s + 5; + } + else if (strncasecmp (s, "rtlblo", 6) == 0) + { + *reg = REG_TLBLO; + return s + 6; + } + else if (strncasecmp (s, "rtlbhi", 6) == 0) + { + *reg = REG_TLBHI; + return s + 6; + } + else if (strncasecmp (s, "rtlbsx", 6) == 0) + { + *reg = REG_TLBSX; + return s + 6; + } + /* MMU registers end. */ + else if (strncasecmp (s, "rpvr", 4) == 0) + { + if (isdigit (s[4]) && isdigit (s[5])) + { + tmpreg = (s[4]-'0')*10 + s[5] - '0'; + s += 6; + } + + else if (isdigit (s[4])) + { + tmpreg = s[4] - '0'; + s += 5; + } + else + as_bad (_("register expected, but saw '%.6s'"), s); + if ((int) tmpreg >= MIN_PVR_REGNUM && tmpreg <= MAX_PVR_REGNUM) + *reg = REG_PVR + tmpreg; + else + { + as_bad (_("Invalid register number at '%.6s'"), s); + *reg = REG_PVR; + } + return s; + } + else if (strncasecmp (s, "rsp", 3) == 0) + { + *reg = REG_SP; + return s + 3; + } + else if (strncasecmp (s, "rfsl", 4) == 0) + { + if (isdigit (s[4]) && isdigit (s[5])) + { + tmpreg = (s[4] - '0') * 10 + s[5] - '0'; + s += 6; + } + else if (isdigit (s[4])) + { + tmpreg = s[4] - '0'; + s += 5; + } + else + as_bad (_("register expected, but saw '%.6s'"), s); + + if ((int)tmpreg >= MIN_REGNUM && tmpreg <= MAX_REGNUM) + *reg = tmpreg; + else + { + as_bad (_("Invalid register number at '%.6s'"), s); + *reg = 0; + } + return s; + } + else + { + if (tolower (s[0]) == 'r') + { + if (isdigit (s[1]) && isdigit (s[2])) + { + tmpreg = (s[1] - '0') * 10 + s[2] - '0'; + s += 3; + } + else if (isdigit (s[1])) + { + tmpreg = s[1] - '0'; + s += 2; + } + else + as_bad (_("register expected, but saw '%.6s'"), s); + + if ((int)tmpreg >= MIN_REGNUM && tmpreg <= MAX_REGNUM) + *reg = tmpreg; + else + { + as_bad (_("Invalid register number at '%.6s'"), s); + *reg = 0; + } + return s; + } + } + as_bad (_("register expected, but saw '%.6s'"), s); + *reg = 0; + return s; +} + +static char * +parse_exp (char *s, expressionS *e) +{ + char *save; + char *new; + + /* Skip whitespace. */ + while (isspace (* s)) + ++ s; + + save = input_line_pointer; + input_line_pointer = s; + + expression (e); + + if (e->X_op == O_absent) + as_fatal (_("missing operand")); + + new = input_line_pointer; + input_line_pointer = save; + + return new; +} + +/* Symbol modifiers (@GOT, @PLT, @GOTOFF). */ +#define IMM_GOT 1 +#define IMM_PLT 2 +#define IMM_GOTOFF 3 + +static symbolS * GOT_symbol; + +#define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" + +static char * +parse_imm (char * s, expressionS * e, int min, int max) +{ + char *new; + char *atp; + + /* Find the start of "@GOT" or "@PLT" suffix (if any) */ + for (atp = s; *atp != '@'; atp++) + if (is_end_of_line[(unsigned char) *atp]) + break; + + if (*atp == '@') + { + if (strncmp (atp + 1, "GOTOFF", 5) == 0) + { + *atp = 0; + e->X_md = IMM_GOTOFF; + } + else if (strncmp (atp + 1, "GOT", 3) == 0) + { + *atp = 0; + e->X_md = IMM_GOT; + } + else if (strncmp (atp + 1, "PLT", 3) == 0) + { + *atp = 0; + e->X_md = IMM_PLT; + } + else + { + atp = NULL; + e->X_md = 0; + } + *atp = 0; + } + else + { + atp = NULL; + e->X_md = 0; + } + + if (atp && !GOT_symbol) + { + GOT_symbol = symbol_find_or_make (GOT_SYMBOL_NAME); + } + + new = parse_exp (s, e); + + if (e->X_op == O_absent) + ; /* An error message has already been emitted. */ + else if ((e->X_op != O_constant && e->X_op != O_symbol) ) + as_fatal (_("operand must be a constant or a label")); + else if ((e->X_op == O_constant) && ((int) e->X_add_number < min + || (int) e->X_add_number > max)) + { + as_fatal (_("operand must be absolute in range %d..%d, not %d"), + min, max, (int) e->X_add_number); + } + + if (atp) + { + *atp = '@'; /* restore back (needed?) */ + if (new >= atp) + new += (e->X_md == IMM_GOTOFF)?7:4; + /* sizeof("@GOTOFF", "@GOT" or "@PLT") */ + + } + return new; +} + +static char * +check_got (int * got_type, int * got_len) +{ + char *new; + char *atp; + char *past_got; + int first, second; + char *tmpbuf; + + /* Find the start of "@GOT" or "@PLT" suffix (if any). */ + for (atp = input_line_pointer; *atp != '@'; atp++) + if (is_end_of_line[(unsigned char) *atp]) + return NULL; + + if (strncmp (atp + 1, "GOTOFF", 5) == 0) + { + *got_len = 6; + *got_type = IMM_GOTOFF; + } + else if (strncmp (atp + 1, "GOT", 3) == 0) + { + *got_len = 3; + *got_type = IMM_GOT; + } + else if (strncmp (atp + 1, "PLT", 3) == 0) + { + *got_len = 3; + *got_type = IMM_PLT; + } + else + return NULL; + + if (!GOT_symbol) + GOT_symbol = symbol_find_or_make (GOT_SYMBOL_NAME); + + first = atp - input_line_pointer; + + past_got = atp + *got_len + 1; + for (new = past_got; !is_end_of_line[(unsigned char) *new++]; ) + ; + second = new - past_got; + tmpbuf = xmalloc (first + second + 2); /* One extra byte for ' ' and one for NUL. */ + memcpy (tmpbuf, input_line_pointer, first); + tmpbuf[first] = ' '; /* @GOTOFF is replaced with a single space. */ + memcpy (tmpbuf + first + 1, past_got, second); + tmpbuf[first + second + 1] = '\0'; + + return tmpbuf; +} + +extern void +parse_cons_expression_microblaze (expressionS *exp, int size) +{ + if (size == 4) + { + /* Handle @GOTOFF et.al. */ + char *save, *gotfree_copy; + int got_len, got_type; + + save = input_line_pointer; + gotfree_copy = check_got (& got_type, & got_len); + if (gotfree_copy) + input_line_pointer = gotfree_copy; + + expression (exp); + + if (gotfree_copy) + { + exp->X_md = got_type; + input_line_pointer = save + (input_line_pointer - gotfree_copy) + + got_len; + free (gotfree_copy); + } + } + else + expression (exp); +} + +/* This is the guts of the machine-dependent assembler. STR points to a + machine dependent instruction. This function is supposed to emit + the frags/bytes it assembles to. */ + +static char * str_microblaze_ro_anchor = "RO"; +static char * str_microblaze_rw_anchor = "RW"; + +static bfd_boolean +check_spl_reg (unsigned * reg) +{ + if ((*reg == REG_MSR) || (*reg == REG_PC) + || (*reg == REG_EAR) || (*reg == REG_ESR) + || (*reg == REG_FSR) || (*reg == REG_BTR) || (*reg == REG_EDR) + || (*reg == REG_PID) || (*reg == REG_ZPR) + || (*reg == REG_TLBX) || (*reg == REG_TLBLO) + || (*reg == REG_TLBHI) || (*reg == REG_TLBSX) + || (*reg >= REG_PVR+MIN_PVR_REGNUM && *reg <= REG_PVR+MAX_PVR_REGNUM)) + return TRUE; + + return FALSE; +} + +/* Here we decide which fixups can be adjusted to make them relative to + the beginning of the section instead of the symbol. Basically we need + to make sure that the dynamic relocations are done correctly, so in + some cases we force the original symbol to be used. */ + +int +tc_microblaze_fix_adjustable (struct fix *fixP) +{ + if (GOT_symbol && fixP->fx_subsy == GOT_symbol) + return 0; + + if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GOTOFF + || fixP->fx_r_type == BFD_RELOC_MICROBLAZE_32_GOTOFF + || fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GOT + || fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PLT) + return 0; + + return 1; +} + +void +md_assemble (char * str) +{ + char * op_start; + char * op_end; + struct op_code_struct * opcode, *opcode1; + char * output = NULL; + int nlen = 0; + int i; + unsigned long inst, inst1; + unsigned reg1; + unsigned reg2; + unsigned reg3; + unsigned isize; + unsigned int imm, temp; + expressionS exp; + char name[20]; + + /* Drop leading whitespace. */ + while (isspace (* str)) + str ++; + + /* Find the op code end. */ + for (op_start = op_end = str; + * op_end && nlen < 20 && !is_end_of_line [(int)*op_end] && *op_end != ' '; + op_end++) + { + name[nlen] = op_start[nlen]; + nlen++; + } + + name [nlen] = 0; + + if (nlen == 0) + { + as_bad (_("can't find opcode ")); + return; + } + + opcode = (struct op_code_struct *) hash_find (opcode_hash_control, name); + if (opcode == NULL) + { + as_bad (_("unknown opcode \"%s\""), name); + return; + } + + inst = opcode->bit_sequence; + isize = 4; + + switch (opcode->inst_type) + { + case INST_TYPE_RD_R1_R2: + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ + else + { + as_fatal (_("Error in statement syntax")); + reg1 = 0; + } + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®2); /* Get r1. */ + else + { + as_fatal (_("Error in statement syntax")); + reg2 = 0; + } + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®3); /* Get r2. */ + else + { + as_fatal (_("Error in statement syntax")); + reg3 = 0; + } + + /* Check for spl registers. */ + if (check_spl_reg (& reg1)) + as_fatal (_("Cannot use special register with this instruction")); + if (check_spl_reg (& reg2)) + as_fatal (_("Cannot use special register with this instruction")); + if (check_spl_reg (& reg3)) + as_fatal (_("Cannot use special register with this instruction")); + + if (streq (name, "sub")) + { + /* sub rd, r1, r2 becomes rsub rd, r2, r1. */ + inst |= (reg1 << RD_LOW) & RD_MASK; + inst |= (reg3 << RA_LOW) & RA_MASK; + inst |= (reg2 << RB_LOW) & RB_MASK; + } + else + { + inst |= (reg1 << RD_LOW) & RD_MASK; + inst |= (reg2 << RA_LOW) & RA_MASK; + inst |= (reg3 << RB_LOW) & RB_MASK; + } + output = frag_more (isize); + break; + + case INST_TYPE_RD_R1_IMM: + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ + else + { + as_fatal (_("Error in statement syntax")); + reg1 = 0; + } + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®2); /* Get r1. */ + else + { + as_fatal (_("Error in statement syntax")); + reg2 = 0; + } + if (strcmp (op_end, "")) + op_end = parse_imm (op_end + 1, & exp, MIN_IMM, MAX_IMM); + else + as_fatal (_("Error in statement syntax")); + + /* Check for spl registers. */ + if (check_spl_reg (& reg1)) + as_fatal (_("Cannot use special register with this instruction")); + if (check_spl_reg (& reg2)) + as_fatal (_("Cannot use special register with this instruction")); + + if (exp.X_op != O_constant) + { + char *opc; + relax_substateT subtype; + + if (streq (name, "lmi")) + as_fatal (_("lmi pseudo instruction should not use a label in imm field")); + else if (streq (name, "smi")) + as_fatal (_("smi pseudo instruction should not use a label in imm field")); + + if (reg2 == REG_ROSDP) + opc = str_microblaze_ro_anchor; + else if (reg2 == REG_RWSDP) + opc = str_microblaze_rw_anchor; + else + opc = NULL; + if (exp.X_md == IMM_GOT) + subtype = GOT_OFFSET; + else if (exp.X_md == IMM_PLT) + subtype = PLT_OFFSET; + else if (exp.X_md == IMM_GOTOFF) + subtype = GOTOFF_OFFSET; + else + subtype = opcode->inst_offset_type; + + output = frag_var (rs_machine_dependent, + isize * 2, /* maxm of 2 words. */ + isize, /* minm of 1 word. */ + subtype, /* PC-relative or not. */ + exp.X_add_symbol, + exp.X_add_number, + opc); + imm = 0; + } + else + { + output = frag_more (isize); + imm = exp.X_add_number; + } + + if (streq (name, "lmi") || streq (name, "smi")) + { + /* Load/store 32-d consecutive registers. Used on exit/entry + to subroutines to save and restore registers to stack. + Generate 32-d insts. */ + int count; + + count = 32 - reg1; + if (streq (name, "lmi")) + opcode = (struct op_code_struct *) hash_find (opcode_hash_control, "lwi"); + else + opcode = (struct op_code_struct *) hash_find (opcode_hash_control, "swi"); + if (opcode == NULL) + { + as_bad (_("unknown opcode \"%s\""), "lwi"); + return; + } + inst = opcode->bit_sequence; + inst |= (reg1 << RD_LOW) & RD_MASK; + inst |= (reg2 << RA_LOW) & RA_MASK; + inst |= (imm << IMM_LOW) & IMM_MASK; + + for (i = 0; i < count - 1; i++) + { + output[0] = INST_BYTE0 (inst); + output[1] = INST_BYTE1 (inst); + output[2] = INST_BYTE2 (inst); + output[3] = INST_BYTE3 (inst); + output = frag_more (isize); + imm = imm + 4; + reg1++; + inst = opcode->bit_sequence; + inst |= (reg1 << RD_LOW) & RD_MASK; + inst |= (reg2 << RA_LOW) & RA_MASK; + inst |= (imm << IMM_LOW) & IMM_MASK; + } + } + else + { + temp = imm & 0xFFFF8000; + if ((temp != 0) && (temp != 0xFFFF8000)) + { + /* Needs an immediate inst. */ + opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); + if (opcode1 == NULL) + { + as_bad (_("unknown opcode \"%s\""), "imm"); + return; + } + + inst1 = opcode1->bit_sequence; + inst1 |= ((imm & 0xFFFF0000) >> 16) & IMM_MASK; + output[0] = INST_BYTE0 (inst1); + output[1] = INST_BYTE1 (inst1); + output[2] = INST_BYTE2 (inst1); + output[3] = INST_BYTE3 (inst1); + output = frag_more (isize); + } + inst |= (reg1 << RD_LOW) & RD_MASK; + inst |= (reg2 << RA_LOW) & RA_MASK; + inst |= (imm << IMM_LOW) & IMM_MASK; + } + break; + + case INST_TYPE_RD_R1_IMM5: + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ + else + { + as_fatal (_("Error in statement syntax")); + reg1 = 0; + } + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®2); /* Get r1. */ + else + { + as_fatal (_("Error in statement syntax")); + reg2 = 0; + } + if (strcmp (op_end, "")) + op_end = parse_imm (op_end + 1, & exp, MIN_IMM, MAX_IMM); + else + as_fatal (_("Error in statement syntax")); + + /* Check for spl registers. */ + if (check_spl_reg (®1)) + as_fatal (_("Cannot use special register with this instruction")); + if (check_spl_reg (®2)) + as_fatal (_("Cannot use special register with this instruction")); + + if (exp.X_op != O_constant) + as_warn (_("Symbol used as immediate for shift instruction")); + else + { + output = frag_more (isize); + imm = exp.X_add_number; + } + + if (imm != (imm % 32)) + { + as_warn (_("Shift value > 32. using <value %% 32>")); + imm = imm % 32; + } + inst |= (reg1 << RD_LOW) & RD_MASK; + inst |= (reg2 << RA_LOW) & RA_MASK; + inst |= (imm << IMM_LOW) & IMM5_MASK; + break; + + case INST_TYPE_R1_R2: + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®1); /* Get r1. */ + else + { + as_fatal (_("Error in statement syntax")); + reg1 = 0; + } + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®2); /* Get r2. */ + else + { + as_fatal (_("Error in statement syntax")); + reg2 = 0; + } + + /* Check for spl registers. */ + if (check_spl_reg (& reg1)) + as_fatal (_("Cannot use special register with this instruction")); + if (check_spl_reg (& reg2)) + as_fatal (_("Cannot use special register with this instruction")); + + inst |= (reg1 << RA_LOW) & RA_MASK; + inst |= (reg2 << RB_LOW) & RB_MASK; + output = frag_more (isize); + break; + + case INST_TYPE_RD_R1: + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ + else + { + as_fatal (_("Error in statement syntax")); + reg1 = 0; + } + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®2); /* Get r1. */ + else + { + as_fatal (_("Error in statement syntax")); + reg2 =0; + } + + /* Check for spl registers. */ + if (check_spl_reg (®1)) + as_fatal (_("Cannot use special register with this instruction")); + if (check_spl_reg (®2)) + as_fatal (_("Cannot use special register with this instruction")); + + inst |= (reg1 << RD_LOW) & RD_MASK; + inst |= (reg2 << RA_LOW) & RA_MASK; + output = frag_more (isize); + break; + + case INST_TYPE_RD_RFSL: + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ + else + { + as_fatal (_("Error in statement syntax")); + reg1 = 0; + } + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, &imm); /* Get rfslN. */ + else + { + as_fatal (_("Error in statement syntax")); + imm = 0; + } + + /* Check for spl registers. */ + if (check_spl_reg (®1)) + as_fatal (_("Cannot use special register with this instruction")); + + inst |= (reg1 << RD_LOW) & RD_MASK; + inst |= (imm << IMM_LOW) & RFSL_MASK; + output = frag_more (isize); + break; + + case INST_TYPE_RD_IMM15: + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ + else + { + as_fatal (_("Error in statement syntax")); + reg1 = 0; + } + + if (strcmp (op_end, "")) + op_end = parse_imm (op_end + 1, & exp, MIN_IMM15, MAX_IMM15); + else + as_fatal (_("Error in statement syntax")); + + /* Check for spl registers. */ + if (check_spl_reg (®1)) + as_fatal (_("Cannot use special register with this instruction")); + + if (exp.X_op != O_constant) + as_fatal (_("Symbol used as immediate value for msrset/msrclr instructions")); + else + { + output = frag_more (isize); + imm = exp.X_add_number; + } + inst |= (reg1 << RD_LOW) & RD_MASK; + inst |= (imm << IMM_LOW) & IMM15_MASK; + break; + + case INST_TYPE_R1_RFSL: + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®1); /* Get r1. */ + else + { + as_fatal (_("Error in statement syntax")); + reg1 = 0; + } + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, &imm); /* Get rfslN. */ + else + { + as_fatal (_("Error in statement syntax")); + imm = 0; + } + + /* Check for spl registers. */ + if (check_spl_reg (®1)) + as_fatal (_("Cannot use special register with this instruction")); + + inst |= (reg1 << RA_LOW) & RA_MASK; + inst |= (imm << IMM_LOW) & RFSL_MASK; + output = frag_more (isize); + break; + + case INST_TYPE_RFSL: + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, &imm); /* Get rfslN. */ + else + { + as_fatal (_("Error in statement syntax")); + imm = 0; + } + /* Check for spl registers. */ + if (check_spl_reg (®1)) + as_fatal (_("Cannot use special register with this instruction")); + inst |= (imm << IMM_LOW) & RFSL_MASK; + output = frag_more (isize); + break; + + case INST_TYPE_R1: + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®1); /* Get r1. */ + else + { + as_fatal (_("Error in statement syntax")); + reg1 = 0; + } + + /* Check for spl registers. */ + if (check_spl_reg (®1)) + as_fatal (_("Cannot use special register with this instruction")); + + inst |= (reg1 << RA_LOW) & RA_MASK; + output = frag_more (isize); + break; + + /* For tuqula insn...:) */ + case INST_TYPE_RD: + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ + else + { + as_fatal (_("Error in statement syntax")); + reg1 = 0; + } + + /* Check for spl registers. */ + if (check_spl_reg (®1)) + as_fatal (_("Cannot use special register with this instruction")); + + inst |= (reg1 << RD_LOW) & RD_MASK; + output = frag_more (isize); + break; + + case INST_TYPE_RD_SPECIAL: + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ + else + { + as_fatal (_("Error in statement syntax")); + reg1 = 0; + } + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®2); /* Get r1. */ + else + { + as_fatal (_("Error in statement syntax")); + reg2 = 0; + } + + if (reg2 == REG_MSR) + imm = opcode->immval_mask | REG_MSR_MASK; + else if (reg2 == REG_PC) + imm = opcode->immval_mask | REG_PC_MASK; + else if (reg2 == REG_EAR) + imm = opcode->immval_mask | REG_EAR_MASK; + else if (reg2 == REG_ESR) + imm = opcode->immval_mask | REG_ESR_MASK; + else if (reg2 == REG_FSR) + imm = opcode->immval_mask | REG_FSR_MASK; + else if (reg2 == REG_BTR) + imm = opcode->immval_mask | REG_BTR_MASK; + else if (reg2 == REG_EDR) + imm = opcode->immval_mask | REG_EDR_MASK; + else if (reg2 == REG_PID) + imm = opcode->immval_mask | REG_PID_MASK; + else if (reg2 == REG_ZPR) + imm = opcode->immval_mask | REG_ZPR_MASK; + else if (reg2 == REG_TLBX) + imm = opcode->immval_mask | REG_TLBX_MASK; + else if (reg2 == REG_TLBLO) + imm = opcode->immval_mask | REG_TLBLO_MASK; + else if (reg2 == REG_TLBHI) + imm = opcode->immval_mask | REG_TLBHI_MASK; + else if (reg2 >= (REG_PVR+MIN_PVR_REGNUM) && reg2 <= (REG_PVR+MAX_PVR_REGNUM)) + imm = opcode->immval_mask | REG_PVR_MASK | reg2; + else + as_fatal (_("invalid value for special purpose register")); + inst |= (reg1 << RD_LOW) & RD_MASK; + inst |= (imm << IMM_LOW) & IMM_MASK; + output = frag_more (isize); + break; + + case INST_TYPE_SPECIAL_R1: + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ + else + { + as_fatal (_("Error in statement syntax")); + reg1 = 0; + } + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®2); /* Get r1. */ + else + { + as_fatal (_("Error in statement syntax")); + reg2 = 0; + } + + if (reg1 == REG_MSR) + imm = opcode->immval_mask | REG_MSR_MASK; + else if (reg1 == REG_PC) + imm = opcode->immval_mask | REG_PC_MASK; + else if (reg1 == REG_EAR) + imm = opcode->immval_mask | REG_EAR_MASK; + else if (reg1 == REG_ESR) + imm = opcode->immval_mask | REG_ESR_MASK; + else if (reg1 == REG_FSR) + imm = opcode->immval_mask | REG_FSR_MASK; + else if (reg1 == REG_BTR) + imm = opcode->immval_mask | REG_BTR_MASK; + else if (reg1 == REG_EDR) + imm = opcode->immval_mask | REG_EDR_MASK; + else if (reg1 == REG_PID) + imm = opcode->immval_mask | REG_PID_MASK; + else if (reg1 == REG_ZPR) + imm = opcode->immval_mask | REG_ZPR_MASK; + else if (reg1 == REG_TLBX) + imm = opcode->immval_mask | REG_TLBX_MASK; + else if (reg1 == REG_TLBLO) + imm = opcode->immval_mask | REG_TLBLO_MASK; + else if (reg1 == REG_TLBHI) + imm = opcode->immval_mask | REG_TLBHI_MASK; + else if (reg1 == REG_TLBSX) + imm = opcode->immval_mask | REG_TLBSX_MASK; + else + as_fatal (_("invalid value for special purpose register")); + inst |= (reg2 << RA_LOW) & RA_MASK; + inst |= (imm << IMM_LOW) & IMM_MASK; + output = frag_more (isize); + break; + + case INST_TYPE_RD_R1_SPECIAL: + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ + else + { + as_fatal (_("Error in statement syntax")); + reg1 = 0; + } + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®2); /* Get r1. */ + else + { + as_fatal (_("Error in statement syntax")); + reg2 =0; + } + + /* Check for spl registers. */ + if (check_spl_reg (®1)) + as_fatal (_("Cannot use special register with this instruction")); + if (check_spl_reg (®2)) + as_fatal (_("Cannot use special register with this instruction")); + + /* insn wic ra, rb => wic ra, ra, rb. */ + inst |= (reg1 << RD_LOW) & RD_MASK; + inst |= (reg1 << RA_LOW) & RA_MASK; + inst |= (reg2 << RB_LOW) & RB_MASK; + + output = frag_more (isize); + break; + + case INST_TYPE_RD_R2: + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ + else + { + as_fatal (_("Error in statement syntax")); + reg1 = 0; + } + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®2); /* Get r2. */ + else + { + as_fatal (_("Error in statement syntax")); + reg2 = 0; + } + + /* Check for spl registers. */ + if (check_spl_reg (®1)) + as_fatal (_("Cannot use special register with this instruction")); + if (check_spl_reg (®2)) + as_fatal (_("Cannot use special register with this instruction")); + + inst |= (reg1 << RD_LOW) & RD_MASK; + inst |= (reg2 << RB_LOW) & RB_MASK; + output = frag_more (isize); + break; + + case INST_TYPE_R1_IMM: + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®1); /* Get r1. */ + else + { + as_fatal (_("Error in statement syntax")); + reg1 = 0; + } + if (strcmp (op_end, "")) + op_end = parse_imm (op_end + 1, & exp, MIN_IMM, MAX_IMM); + else + as_fatal (_("Error in statement syntax")); + + /* Check for spl registers. */ + if (check_spl_reg (®1)) + as_fatal (_("Cannot use special register with this instruction")); + + if (exp.X_op != O_constant) + { + char *opc = NULL; + relax_substateT subtype; + + if (exp.X_md == IMM_GOT) + subtype = GOT_OFFSET; + else if (exp.X_md == IMM_PLT) + subtype = PLT_OFFSET; + else + subtype = opcode->inst_offset_type; + output = frag_var (rs_machine_dependent, + isize * 2, /* maxm of 2 words. */ + isize, /* minm of 1 word. */ + subtype, /* PC-relative or not. */ + exp.X_add_symbol, + exp.X_add_number, + opc); + imm = 0; + } + else + { + output = frag_more (isize); + imm = exp.X_add_number; + } + + temp = imm & 0xFFFF8000; + if ((temp != 0) && (temp != 0xFFFF8000)) + { + /* Needs an immediate inst. */ + opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); + if (opcode1 == NULL) + { + as_bad (_("unknown opcode \"%s\""), "imm"); + return; + } + + inst1 = opcode1->bit_sequence; + inst1 |= ((imm & 0xFFFF0000) >> 16) & IMM_MASK; + output[0] = INST_BYTE0 (inst1); + output[1] = INST_BYTE1 (inst1); + output[2] = INST_BYTE2 (inst1); + output[3] = INST_BYTE3 (inst1); + output = frag_more (isize); + } + + inst |= (reg1 << RA_LOW) & RA_MASK; + inst |= (imm << IMM_LOW) & IMM_MASK; + break; + + case INST_TYPE_RD_IMM: + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ + else + { + as_fatal (_("Error in statement syntax")); + reg1 = 0; + } + if (strcmp (op_end, "")) + op_end = parse_imm (op_end + 1, & exp, MIN_IMM, MAX_IMM); + else + as_fatal (_("Error in statement syntax")); + + /* Check for spl registers. */ + if (check_spl_reg (®1)) + as_fatal (_("Cannot use special register with this instruction")); + + if (exp.X_op != O_constant) + { + char *opc = NULL; + relax_substateT subtype; + + if (exp.X_md == IMM_GOT) + subtype = GOT_OFFSET; + else if (exp.X_md == IMM_PLT) + subtype = PLT_OFFSET; + else + subtype = opcode->inst_offset_type; + output = frag_var (rs_machine_dependent, + isize * 2, /* maxm of 2 words. */ + isize, /* minm of 1 word. */ + subtype, /* PC-relative or not. */ + exp.X_add_symbol, + exp.X_add_number, + opc); + imm = 0; + } + else + { + output = frag_more (isize); + imm = exp.X_add_number; + } + + temp = imm & 0xFFFF8000; + if ((temp != 0) && (temp != 0xFFFF8000)) + { + /* Needs an immediate inst. */ + opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); + if (opcode1 == NULL) + { + as_bad (_("unknown opcode \"%s\""), "imm"); + return; + } + + inst1 = opcode1->bit_sequence; + inst1 |= ((imm & 0xFFFF0000) >> 16) & IMM_MASK; + output[0] = INST_BYTE0 (inst1); + output[1] = INST_BYTE1 (inst1); + output[2] = INST_BYTE2 (inst1); + output[3] = INST_BYTE3 (inst1); + output = frag_more (isize); + } + + inst |= (reg1 << RD_LOW) & RD_MASK; + inst |= (imm << IMM_LOW) & IMM_MASK; + break; + + case INST_TYPE_R2: + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®2); /* Get r2. */ + else + { + as_fatal (_("Error in statement syntax")); + reg2 = 0; + } + + /* Check for spl registers. */ + if (check_spl_reg (®2)) + as_fatal (_("Cannot use special register with this instruction")); + + inst |= (reg2 << RB_LOW) & RB_MASK; + output = frag_more (isize); + break; + + case INST_TYPE_IMM: + if (streq (name, "imm")) + as_fatal (_("An IMM instruction should not be present in the .s file")); + + op_end = parse_imm (op_end + 1, & exp, MIN_IMM, MAX_IMM); + + if (exp.X_op != O_constant) + { + char *opc = NULL; + relax_substateT subtype; + + if (exp.X_md == IMM_GOT) + subtype = GOT_OFFSET; + else if (exp.X_md == IMM_PLT) + subtype = PLT_OFFSET; + else + subtype = opcode->inst_offset_type; + output = frag_var (rs_machine_dependent, + isize * 2, /* maxm of 2 words. */ + isize, /* minm of 1 word. */ + subtype, /* PC-relative or not. */ + exp.X_add_symbol, + exp.X_add_number, + opc); + imm = 0; + } + else + { + output = frag_more (isize); + imm = exp.X_add_number; + } + + + temp = imm & 0xFFFF8000; + if ((temp != 0) && (temp != 0xFFFF8000)) + { + /* Needs an immediate inst. */ + opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); + if (opcode1 == NULL) + { + as_bad (_("unknown opcode \"%s\""), "imm"); + return; + } + + inst1 = opcode1->bit_sequence; + inst1 |= ((imm & 0xFFFF0000) >> 16) & IMM_MASK; + output[0] = INST_BYTE0 (inst1); + output[1] = INST_BYTE1 (inst1); + output[2] = INST_BYTE2 (inst1); + output[3] = INST_BYTE3 (inst1); + output = frag_more (isize); + } + inst |= (imm << IMM_LOW) & IMM_MASK; + break; + + case INST_TYPE_NONE: + output = frag_more (isize); + break; + + default: + as_fatal (_("unimplemented opcode \"%s\""), name); + } + + /* Drop whitespace after all the operands have been parsed. */ + while (isspace (* op_end)) + op_end ++; + + /* Give warning message if the insn has more operands than required. */ + if (strcmp (op_end, opcode->name) && strcmp (op_end, "")) + as_warn (_("ignoring operands: %s "), op_end); + + output[0] = INST_BYTE0 (inst); + output[1] = INST_BYTE1 (inst); + output[2] = INST_BYTE2 (inst); + output[3] = INST_BYTE3 (inst); + +#ifdef OBJ_ELF + dwarf2_emit_insn (4); +#endif +} + +symbolS * +md_undefined_symbol (char * name ATTRIBUTE_UNUSED) +{ + return NULL; +} + +/* Various routines to kill one day. */ +/* Equal to MAX_PRECISION in atof-ieee.c */ +#define MAX_LITTLENUMS 6 + +/* Turn a string in input_line_pointer into a floating point constant of type + type, and store the appropriate bytes in *litP. The number of LITTLENUMS + emitted is stored in *sizeP. An error message is returned, or NULL on OK.*/ +char * +md_atof (int type, char * litP, int * sizeP) +{ + int prec; + LITTLENUM_TYPE words[MAX_LITTLENUMS]; + int i; + char * t; + + switch (type) + { + case 'f': + case 'F': + case 's': + case 'S': + prec = 2; + break; + + case 'd': + case 'D': + case 'r': + case 'R': + prec = 4; + break; + + case 'x': + case 'X': + prec = 6; + break; + + case 'p': + case 'P': + prec = 6; + break; + + default: + *sizeP = 0; + return _("Bad call to MD_NTOF()"); + } + + t = atof_ieee (input_line_pointer, type, words); + + if (t) + input_line_pointer = t; + + *sizeP = prec * sizeof (LITTLENUM_TYPE); + + if (! target_big_endian) + { + for (i = prec - 1; i >= 0; i--) + { + md_number_to_chars (litP, (valueT) words[i], + sizeof (LITTLENUM_TYPE)); + litP += sizeof (LITTLENUM_TYPE); + } + } + else + for (i = 0; i < prec; i++) + { + md_number_to_chars (litP, (valueT) words[i], + sizeof (LITTLENUM_TYPE)); + litP += sizeof (LITTLENUM_TYPE); + } + + return NULL; +} + +const char * md_shortopts = ""; + +struct option md_longopts[] = +{ + { NULL, no_argument, NULL, 0} +}; + +size_t md_longopts_size = sizeof (md_longopts); + +int md_short_jump_size; + +void +md_create_short_jump (char * ptr ATTRIBUTE_UNUSED, + addressT from_Nddr ATTRIBUTE_UNUSED, + addressT to_Nddr ATTRIBUTE_UNUSED, + fragS * frag ATTRIBUTE_UNUSED, + symbolS * to_symbol ATTRIBUTE_UNUSED) +{ + as_fatal (_("failed sanity check: short_jump")); +} + +void +md_create_long_jump (char * ptr ATTRIBUTE_UNUSED, + addressT from_Nddr ATTRIBUTE_UNUSED, + addressT to_Nddr ATTRIBUTE_UNUSED, + fragS * frag ATTRIBUTE_UNUSED, + symbolS * to_symbol ATTRIBUTE_UNUSED) +{ + as_fatal (_("failed sanity check: long_jump")); +} + +/* Called after relaxing, change the frags so they know how big they are. */ + +void +md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, + segT sec ATTRIBUTE_UNUSED, + fragS * fragP) +{ + fixS *fixP; + + switch (fragP->fr_subtype) + { + case UNDEFINED_PC_OFFSET: + fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol, + fragP->fr_offset, TRUE, BFD_RELOC_64_PCREL); + fragP->fr_fix += INST_WORD_SIZE * 2; + fragP->fr_var = 0; + break; + case DEFINED_ABS_SEGMENT: + if (fragP->fr_symbol == GOT_symbol) + fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol, + fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64_GOTPC); + else + fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol, + fragP->fr_offset, FALSE, BFD_RELOC_64); + fragP->fr_fix += INST_WORD_SIZE * 2; + fragP->fr_var = 0; + break; + case DEFINED_RO_SEGMENT: + fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol, + fragP->fr_offset, FALSE, BFD_RELOC_MICROBLAZE_32_ROSDA); + fragP->fr_fix += INST_WORD_SIZE; + fragP->fr_var = 0; + break; + case DEFINED_RW_SEGMENT: + fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol, + fragP->fr_offset, FALSE, BFD_RELOC_MICROBLAZE_32_RWSDA); + fragP->fr_fix += INST_WORD_SIZE; + fragP->fr_var = 0; + break; + case DEFINED_PC_OFFSET: + fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol, + fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_32_LO_PCREL); + fragP->fr_fix += INST_WORD_SIZE; + fragP->fr_var = 0; + break; + case LARGE_DEFINED_PC_OFFSET: + fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol, + fragP->fr_offset, TRUE, BFD_RELOC_64_PCREL); + fragP->fr_fix += INST_WORD_SIZE * 2; + fragP->fr_var = 0; + break; + case GOT_OFFSET: + fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol, + fragP->fr_offset, FALSE, BFD_RELOC_MICROBLAZE_64_GOT); + fragP->fr_fix += INST_WORD_SIZE * 2; + fragP->fr_var = 0; + break; + case PLT_OFFSET: + fixP = fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol, + fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64_PLT); + /* fixP->fx_plt = 1; */ + fragP->fr_fix += INST_WORD_SIZE * 2; + fragP->fr_var = 0; + break; + case GOTOFF_OFFSET: + fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol, + fragP->fr_offset, FALSE, BFD_RELOC_MICROBLAZE_64_GOTOFF); + fragP->fr_fix += INST_WORD_SIZE * 2; + fragP->fr_var = 0; + break; + + default: + abort (); + } +} + +/* Applies the desired value to the specified location. + Also sets up addends for 'rela' type relocations. */ +void +md_apply_fix (fixS * fixP, + valueT * valp, + segT segment) +{ + char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; + char * file = fixP->fx_file ? fixP->fx_file : _("unknown"); + const char * symname; + /* Note: use offsetT because it is signed, valueT is unsigned. */ + offsetT val = (offsetT) * valp; + int i; + struct op_code_struct * opcode1; + unsigned long inst1; + + symname = fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : _("<unknown>"); + + /* fixP->fx_offset is supposed to be set up correctly for all + symbol relocations. */ + if (fixP->fx_addsy == NULL) + { + if (!fixP->fx_pcrel) + fixP->fx_offset = val; /* Absolute relocation. */ + else + fprintf (stderr, "NULL symbol PC-relative relocation? offset = %08x, val = %08x\n", + (unsigned int) fixP->fx_offset, (unsigned int) val); + } + + /* If we aren't adjusting this fixup to be against the section + symbol, we need to adjust the value. */ + if (fixP->fx_addsy != NULL) + { + if (S_IS_WEAK (fixP->fx_addsy) + || (symbol_used_in_reloc_p (fixP->fx_addsy) + && (((bfd_get_section_flags (stdoutput, + S_GET_SEGMENT (fixP->fx_addsy)) + & SEC_LINK_ONCE) != 0) + || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)), + ".gnu.linkonce", + sizeof (".gnu.linkonce") - 1)))) + { + val -= S_GET_VALUE (fixP->fx_addsy); + if (val != 0 && ! fixP->fx_pcrel) + { + /* In this case, the bfd_install_relocation routine will + incorrectly add the symbol value back in. We just want + the addend to appear in the object file. + FIXME: If this makes VALUE zero, we're toast. */ + val -= S_GET_VALUE (fixP->fx_addsy); + } + } + } + + /* If the fix is relative to a symbol which is not defined, or not + in the same segment as the fix, we cannot resolve it here. */ + /* fixP->fx_addsy is NULL if valp contains the entire relocation. */ + if (fixP->fx_addsy != NULL + && (!S_IS_DEFINED (fixP->fx_addsy) + || (S_GET_SEGMENT (fixP->fx_addsy) != segment))) + { + fixP->fx_done = 0; +#ifdef OBJ_ELF + /* For ELF we can just return and let the reloc that will be generated + take care of everything. For COFF we still have to insert 'val' + into the insn since the addend field will be ignored. */ + /* return; */ +#endif + } + /* All fixups in the text section must be handled in the linker. */ + else if (segment->flags & SEC_CODE) + fixP->fx_done = 0; + else if (!fixP->fx_pcrel && fixP->fx_addsy != NULL) + fixP->fx_done = 0; + else + fixP->fx_done = 1; + + switch (fixP->fx_r_type) + { + case BFD_RELOC_MICROBLAZE_32_LO: + case BFD_RELOC_MICROBLAZE_32_LO_PCREL: + if (target_big_endian) + { + buf[2] |= ((val >> 8) & 0xff); + buf[3] |= (val & 0xff); + } + else + { + buf[1] |= ((val >> 8) & 0xff); + buf[0] |= (val & 0xff); + } + break; + case BFD_RELOC_MICROBLAZE_32_ROSDA: + case BFD_RELOC_MICROBLAZE_32_RWSDA: + /* Don't do anything if the symbol is not defined. */ + if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) + { + if (((val & 0xFFFF8000) != 0) && ((val & 0xFFFF8000) != 0xFFFF8000)) + as_bad_where (file, fixP->fx_line, + _("pcrel for branch to %s too far (0x%x)"), + symname, (int) val); + if (target_big_endian) + { + buf[2] |= ((val >> 8) & 0xff); + buf[3] |= (val & 0xff); + } + else + { + buf[1] |= ((val >> 8) & 0xff); + buf[0] |= (val & 0xff); + } + } + break; + case BFD_RELOC_32: + case BFD_RELOC_RVA: + case BFD_RELOC_32_PCREL: + case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM: + /* Don't do anything if the symbol is not defined. */ + if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) + { + if (target_big_endian) + { + buf[0] |= ((val >> 24) & 0xff); + buf[1] |= ((val >> 16) & 0xff); + buf[2] |= ((val >> 8) & 0xff); + buf[3] |= (val & 0xff); + } + else + { + buf[3] |= ((val >> 24) & 0xff); + buf[2] |= ((val >> 16) & 0xff); + buf[1] |= ((val >> 8) & 0xff); + buf[0] |= (val & 0xff); + } + } + break; + case BFD_RELOC_64_PCREL: + case BFD_RELOC_64: + /* Add an imm instruction. First save the current instruction. */ + for (i = 0; i < INST_WORD_SIZE; i++) + buf[i + INST_WORD_SIZE] = buf[i]; + + /* Generate the imm instruction. */ + opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); + if (opcode1 == NULL) + { + as_bad (_("unknown opcode \"%s\""), "imm"); + return; + } + + inst1 = opcode1->bit_sequence; + if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) + inst1 |= ((val & 0xFFFF0000) >> 16) & IMM_MASK; + + buf[0] = INST_BYTE0 (inst1); + buf[1] = INST_BYTE1 (inst1); + buf[2] = INST_BYTE2 (inst1); + buf[3] = INST_BYTE3 (inst1); + + /* Add the value only if the symbol is defined. */ + if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) + { + if (target_big_endian) + { + buf[6] |= ((val >> 8) & 0xff); + buf[7] |= (val & 0xff); + } + else + { + buf[5] |= ((val >> 8) & 0xff); + buf[4] |= (val & 0xff); + } + } + break; + + case BFD_RELOC_MICROBLAZE_64_GOTPC: + case BFD_RELOC_MICROBLAZE_64_GOT: + case BFD_RELOC_MICROBLAZE_64_PLT: + case BFD_RELOC_MICROBLAZE_64_GOTOFF: + /* Add an imm instruction. First save the current instruction. */ + for (i = 0; i < INST_WORD_SIZE; i++) + buf[i + INST_WORD_SIZE] = buf[i]; + + /* Generate the imm instruction. */ + opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); + if (opcode1 == NULL) + { + as_bad (_("unknown opcode \"%s\""), "imm"); + return; + } + + inst1 = opcode1->bit_sequence; + + /* We can fixup call to a defined non-global address + within the same section only. */ + buf[0] = INST_BYTE0 (inst1); + buf[1] = INST_BYTE1 (inst1); + buf[2] = INST_BYTE2 (inst1); + buf[3] = INST_BYTE3 (inst1); + return; + + default: + break; + } + + if (fixP->fx_addsy == NULL) + { + /* This fixup has been resolved. Create a reloc in case the linker + moves code around due to relaxing. */ + if (fixP->fx_r_type == BFD_RELOC_64_PCREL) + fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE; + else + fixP->fx_r_type = BFD_RELOC_NONE; + fixP->fx_addsy = section_symbol (absolute_section); + } + return; +} + +void +md_operand (expressionS * expressionP) +{ + /* Ignore leading hash symbol, if present. */ + if (*input_line_pointer == '#') + { + input_line_pointer ++; + expression (expressionP); + } +} + +/* Called just before address relaxation, return the length + by which a fragment must grow to reach it's destination. */ + +int +md_estimate_size_before_relax (fragS * fragP, + segT segment_type) +{ + sbss_segment = bfd_get_section_by_name (stdoutput, ".sbss"); + sbss2_segment = bfd_get_section_by_name (stdoutput, ".sbss2"); + sdata_segment = bfd_get_section_by_name (stdoutput, ".sdata"); + sdata2_segment = bfd_get_section_by_name (stdoutput, ".sdata2"); + + switch (fragP->fr_subtype) + { + case INST_PC_OFFSET: + /* Used to be a PC-relative branch. */ + if (!fragP->fr_symbol) + { + /* We know the abs value: Should never happen. */ + as_bad (_("Absolute PC-relative value in relaxation code. Assembler error.....")); + abort (); + } + else if ((S_GET_SEGMENT (fragP->fr_symbol) == segment_type)) + { + fragP->fr_subtype = DEFINED_PC_OFFSET; + /* Don't know now whether we need an imm instruction. */ + fragP->fr_var = INST_WORD_SIZE; + } + else if (S_IS_DEFINED (fragP->fr_symbol) + && (((S_GET_SEGMENT (fragP->fr_symbol))->flags & SEC_CODE) == 0)) + { + /* Cannot have a PC-relative branch to a diff segment. */ + as_bad (_("PC relative branch to label %s which is not in the instruction space"), + S_GET_NAME (fragP->fr_symbol)); + fragP->fr_subtype = UNDEFINED_PC_OFFSET; + fragP->fr_var = INST_WORD_SIZE*2; + } + else + { + fragP->fr_subtype = UNDEFINED_PC_OFFSET; + fragP->fr_var = INST_WORD_SIZE*2; + } + break; + + case INST_NO_OFFSET: + /* Used to be a reference to somewhere which was unknown. */ + if (fragP->fr_symbol) + { + if (fragP->fr_opcode == NULL) + { + /* Used as an absolute value. */ + fragP->fr_subtype = DEFINED_ABS_SEGMENT; + /* Variable part does not change. */ + fragP->fr_var = INST_WORD_SIZE*2; + } + else if (streq (fragP->fr_opcode, str_microblaze_ro_anchor)) + { + /* It is accessed using the small data read only anchor. */ + if ((S_GET_SEGMENT (fragP->fr_symbol) == &bfd_com_section) + || (S_GET_SEGMENT (fragP->fr_symbol) == sdata2_segment) + || (S_GET_SEGMENT (fragP->fr_symbol) == sbss2_segment) + || (! S_IS_DEFINED (fragP->fr_symbol))) + { + fragP->fr_subtype = DEFINED_RO_SEGMENT; + fragP->fr_var = INST_WORD_SIZE; + } + else + { + /* Variable not in small data read only segment accessed + using small data read only anchor. */ + char *file = fragP->fr_file ? fragP->fr_file : _("unknown"); + + as_bad_where (file, fragP->fr_line, + _("Variable is accessed using small data read " + "only anchor, but it is not in the small data " + "read only section")); + fragP->fr_subtype = DEFINED_RO_SEGMENT; + fragP->fr_var = INST_WORD_SIZE; + } + } + else if (streq (fragP->fr_opcode, str_microblaze_rw_anchor)) + { + if ((S_GET_SEGMENT (fragP->fr_symbol) == &bfd_com_section) + || (S_GET_SEGMENT (fragP->fr_symbol) == sdata_segment) + || (S_GET_SEGMENT (fragP->fr_symbol) == sbss_segment) + || (!S_IS_DEFINED (fragP->fr_symbol))) + { + /* It is accessed using the small data read write anchor. */ + fragP->fr_subtype = DEFINED_RW_SEGMENT; + fragP->fr_var = INST_WORD_SIZE; + } + else + { + char *file = fragP->fr_file ? fragP->fr_file : _("unknown"); + + as_bad_where (file, fragP->fr_line, + _("Variable is accessed using small data read " + "write anchor, but it is not in the small data " + "read write section")); + fragP->fr_subtype = DEFINED_RW_SEGMENT; + fragP->fr_var = INST_WORD_SIZE; + } + } + else + { + as_bad (_("Incorrect fr_opcode value in frag. Internal error.....")); + abort (); + } + } + else + { + /* We know the abs value: Should never happen. */ + as_bad (_("Absolute value in relaxation code. Assembler error.....")); + abort (); + } + break; + + case UNDEFINED_PC_OFFSET: + case LARGE_DEFINED_PC_OFFSET: + case DEFINED_ABS_SEGMENT: + case GOT_OFFSET: + case PLT_OFFSET: + case GOTOFF_OFFSET: + fragP->fr_var = INST_WORD_SIZE*2; + break; + case DEFINED_RO_SEGMENT: + case DEFINED_RW_SEGMENT: + case DEFINED_PC_OFFSET: + fragP->fr_var = INST_WORD_SIZE; + break; + default: + abort (); + } + + return fragP->fr_var; +} + +/* Put number into target byte order. */ + +void +md_number_to_chars (char * ptr, valueT use, int nbytes) +{ + if (target_big_endian) + number_to_chars_bigendian (ptr, use, nbytes); + else + number_to_chars_littleendian (ptr, use, nbytes); +} + +/* Round up a section size to the appropriate boundary. */ + +valueT +md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) +{ + return size; /* Byte alignment is fine. */ +} + + +/* The location from which a PC relative jump should be calculated, + given a PC relative reloc. */ + +long +md_pcrel_from_section (fixS * fixp, segT sec ATTRIBUTE_UNUSED) +{ +#ifdef OBJ_ELF + /* If the symbol is undefined or defined in another section + we leave the add number alone for the linker to fix it later. + Only account for the PC pre-bump (No PC-pre-bump on the Microblaze). */ + + if (fixp->fx_addsy != (symbolS *) NULL + && (!S_IS_DEFINED (fixp->fx_addsy) + || (S_GET_SEGMENT (fixp->fx_addsy) != sec))) + return 0; + else + { + /* The case where we are going to resolve things... */ + if (fixp->fx_r_type == BFD_RELOC_64_PCREL) + return fixp->fx_where + fixp->fx_frag->fr_address + INST_WORD_SIZE; + else + return fixp->fx_where + fixp->fx_frag->fr_address; + } +#endif +} + + +#define F(SZ,PCREL) (((SZ) << 1) + (PCREL)) +#define MAP(SZ,PCREL,TYPE) case F (SZ, PCREL): code = (TYPE); break + +arelent * +tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp) +{ + arelent * rel; + bfd_reloc_code_real_type code; + + switch (fixp->fx_r_type) + { + case BFD_RELOC_NONE: + case BFD_RELOC_MICROBLAZE_64_NONE: + case BFD_RELOC_32: + case BFD_RELOC_MICROBLAZE_32_LO: + case BFD_RELOC_MICROBLAZE_32_LO_PCREL: + case BFD_RELOC_RVA: + case BFD_RELOC_64: + case BFD_RELOC_64_PCREL: + case BFD_RELOC_MICROBLAZE_32_ROSDA: + case BFD_RELOC_MICROBLAZE_32_RWSDA: + case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM: + case BFD_RELOC_MICROBLAZE_64_GOTPC: + case BFD_RELOC_MICROBLAZE_64_GOT: + case BFD_RELOC_MICROBLAZE_64_PLT: + case BFD_RELOC_MICROBLAZE_64_GOTOFF: + case BFD_RELOC_MICROBLAZE_32_GOTOFF: + code = fixp->fx_r_type; + break; + + default: + switch (F (fixp->fx_size, fixp->fx_pcrel)) + { + MAP (1, 0, BFD_RELOC_8); + MAP (2, 0, BFD_RELOC_16); + MAP (4, 0, BFD_RELOC_32); + MAP (1, 1, BFD_RELOC_8_PCREL); + MAP (2, 1, BFD_RELOC_16_PCREL); + MAP (4, 1, BFD_RELOC_32_PCREL); + default: + code = fixp->fx_r_type; + as_bad (_("Can not do %d byte %srelocation"), + fixp->fx_size, + fixp->fx_pcrel ? _("pc-relative") : ""); + } + break; + } + + rel = (arelent *) xmalloc (sizeof (arelent)); + rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); + + if (code == BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM) + *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_subsy); + else + *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); + + rel->address = fixp->fx_frag->fr_address + fixp->fx_where; + /* Always pass the addend along! */ + rel->addend = fixp->fx_offset; + rel->howto = bfd_reloc_type_lookup (stdoutput, code); + + if (rel->howto == NULL) + { + as_bad_where (fixp->fx_file, fixp->fx_line, + _("Cannot represent relocation type %s"), + bfd_get_reloc_code_name (code)); + + /* Set howto to a garbage value so that we can keep going. */ + rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); + gas_assert (rel->howto != NULL); + } + return rel; +} + +int +md_parse_option (int c, char * arg ATTRIBUTE_UNUSED) +{ + switch (c) + { + default: + return 0; + } + return 1; +} + +void +md_show_usage (FILE * stream ATTRIBUTE_UNUSED) +{ + /* fprintf(stream, _("\ + MicroBlaze options:\n\ + -noSmall Data in the comm and data sections do not go into the small data section\n")); */ +} + + +/* Create a fixup for a cons expression. If parse_cons_expression_microblaze + found a machine specific op in an expression, + then we create relocs accordingly. */ + +void +cons_fix_new_microblaze (fragS * frag, + int where, + int size, + expressionS *exp) +{ + + bfd_reloc_code_real_type r; + + if ((exp->X_op == O_subtract) && (exp->X_add_symbol) && + (exp->X_op_symbol) && (now_seg != absolute_section) && (size == 4) + && (!S_IS_LOCAL (exp->X_op_symbol))) + r = BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM; + else if (exp->X_md == IMM_GOTOFF && exp->X_op == O_symbol_rva) + { + exp->X_op = O_symbol; + r = BFD_RELOC_MICROBLAZE_32_GOTOFF; + } + else + { + switch (size) + { + case 1: + r = BFD_RELOC_8; + break; + case 2: + r = BFD_RELOC_16; + break; + case 4: + r = BFD_RELOC_32; + break; + case 8: + r = BFD_RELOC_64; + break; + default: + as_bad (_("unsupported BFD relocation size %u"), size); + r = BFD_RELOC_32; + break; + } + } + fix_new_exp (frag, where, size, exp, 0, r); +} diff --git a/gas/config/tc-microblaze.h b/gas/config/tc-microblaze.h new file mode 100644 index 0000000..db8d227 --- /dev/null +++ b/gas/config/tc-microblaze.h @@ -0,0 +1,114 @@ +/* tc-microblaze.h -- Header file for tc-microblaze.c. + + Copyright 2009 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#ifndef TC_MICROBLAZE +#define TC_MICROBLAZE 1 + +#define TARGET_ARCH bfd_arch_microblaze +/* Used to initialise target_big_endian. */ +#define TARGET_BYTES_BIG_ENDIAN 1 + +#define IGNORE_NONSTANDARD_ESCAPES + +#define TC_RELOC_MANGLE(a,b,c) tc_reloc_mangle (a, b, c) + +/* We need to handle expressions of type "symbol op symbol" and create + relocs for such expressions as -relax in linker can change the value + of such expressions */ +#define TC_CONS_FIX_NEW cons_fix_new_microblaze +#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) parse_cons_expression_microblaze (EXP, NBYTES) +extern void parse_cons_expression_microblaze PARAMS ((expressionS *, int)); + +#define TC_FORCE_RELOCATION_SECTION(FIXP,SEG) 1 +#define UNDEFINED_DIFFERENCE_OK 1 + +#define TC_FORCE_RELOCATION_LOCAL(FIX) \ + (!(FIX)->fx_pcrel \ + || (FIX)->fx_r_type == BFD_RELOC_MICROBLAZE_64_GOT \ + || (FIX)->fx_r_type == BFD_RELOC_MICROBLAZE_64_PLT \ + || (FIX)->fx_r_type == BFD_RELOC_MICROBLAZE_64_GOTOFF \ + || (FIX)->fx_r_type == BFD_RELOC_MICROBLAZE_32_GOTOFF \ + || TC_FORCE_RELOCATION (FIX)) + +#define tc_fix_adjustable(X) tc_microblaze_fix_adjustable(X) +extern int tc_microblaze_fix_adjustable (struct fix *); + +extern const struct relax_type md_relax_table[]; +#define TC_GENERIC_RELAX_TABLE md_relax_table + +/* We don't need to handle .word strangely. */ +#define WORKING_DOT_WORD + +#define LISTING_HEADER "Xilinx MicroBlaze GAS Listing" +#define LISTING_LHS_CONT_LINES 4 + +#define NEED_FX_R_TYPE 1 + +/* We want local label support. */ +#define LOCAL_LABELS_FB 1 + +/* Want the section information too... */ +#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC) + +#define MD_APPLY_FIX3 /* We want the segment as well. */ + +/* We set the fx_done field appropriately in md_apply_fix. */ +#define TC_HANDLES_FX_DONE + +#ifdef OBJ_ELF + +#define TARGET_FORMAT (target_big_endian ? "elf32-microblaze" : "elf32-microblaze-little") + +#define ELF_TC_SPECIAL_SECTIONS \ + { ".sdata", SHT_PROGBITS, SHF_ALLOC + SHF_WRITE }, \ + { ".sbss", SHT_NOBITS, SHF_ALLOC + SHF_WRITE }, \ + { ".sdata2", SHT_PROGBITS, SHF_ALLOC }, \ + { ".sbss2", SHT_PROGBITS, SHF_ALLOC }, \ +/* Other special sections not generated by the assembler: .reginfo, + .liblist, .conflict, .gptab, .got, .dynamic, .rel.dyn. */ + +#endif /* OBJ_ELF */ + +#ifndef TARGET_FORMAT +# error No target format specified. +#endif + +#include "write.h" /* For definition of fixS */ + +extern void md_begin (void); +extern void md_assemble (char *); +extern symbolS * md_undefined_symbol (char *); +extern char * md_atof (int, char *, int *); +extern int md_parse_option (int, char *); +extern void md_show_usage (FILE *); +extern void md_convert_frag (bfd *, segT, fragS *); +extern void md_operand (expressionS *); +extern int md_estimate_size_before_relax (fragS *, segT); +extern void md_number_to_chars (char *, valueT, int); +extern valueT md_section_align (segT, valueT); +extern long md_pcrel_from_section (fixS *, segT); +extern arelent * tc_gen_reloc (asection *, fixS *); +extern void cons_fix_new_microblaze (fragS *, int, int, expressionS *); +extern void md_apply_fix3 (fixS *, valueT *, segT); + +#define EXTERN_FORCE_RELOC -1 + +#endif /* TC_MICROBLAZE */ diff --git a/gas/config/tc-tic4x.c b/gas/config/tc-tic4x.c index 478a04e..e77661b 100644 --- a/gas/config/tc-tic4x.c +++ b/gas/config/tc-tic4x.c @@ -1285,8 +1285,8 @@ tic4x_inst_add (const tic4x_inst_t *insts) d = name; /* We do not care about INSNs that is not a part of our - oplevel setting */ - if (!insts->oplevel & tic4x_oplevel) + oplevel setting. */ + if ((insts->oplevel & tic4x_oplevel) == 0) return ok; while (1) diff --git a/gas/configure b/gas/configure index ec23638..a5fcc2d 100755 --- a/gas/configure +++ b/gas/configure @@ -12042,6 +12042,9 @@ _ACEOF echo "$as_me: WARNING: GAS support for ${generic_target} is preliminary and a work in progress" >&2;} ;; + microblaze*) + ;; + mips-sony-bsd*) ;; mips-*-bsd*) diff --git a/gas/configure.in b/gas/configure.in index 011e886..7d4da95 100644 --- a/gas/configure.in +++ b/gas/configure.in @@ -137,6 +137,9 @@ for this_target in $target $canon_targets ; do AC_MSG_WARN(GAS support for ${generic_target} is preliminary and a work in progress) ;; + microblaze*) + ;; + mips-sony-bsd*) ;; mips-*-bsd*) diff --git a/gas/configure.tgt b/gas/configure.tgt index 1539706..777f798 100644 --- a/gas/configure.tgt +++ b/gas/configure.tgt @@ -55,6 +55,7 @@ case ${cpu} in m683??) cpu_type=m68k ;; maxq) cpu_type=maxq ;; mep-*-elf) cpu_type=mep endian=big ;; + microblaze*) cpu_type=microblaze ;; mips*el) cpu_type=mips endian=little ;; mips*) cpu_type=mips endian=big ;; mt) cpu_type=mt endian=big ;; @@ -279,6 +280,8 @@ case ${generic_target} in mcore-*-elf) fmt=elf ;; mcore-*-pe) fmt=coff em=pe bfd_gas=yes ;; + microblaze-*-*) fmt=elf ;; + # don't change em like *-*-bsd does mips-sony-bsd*) fmt=ecoff ;; mips-*-ultrix*) fmt=ecoff endian=little ;; @@ -425,7 +428,7 @@ case ${generic_target} in esac case ${cpu_type} in - alpha | arm | i386 | ia64 | mips | ns32k | pdp11 | ppc | sparc | z80 | z8k) + alpha | arm | i386 | ia64 | microblaze | mips | ns32k | pdp11 | ppc | sparc | z80 | z8k) bfd_gas=yes ;; esac diff --git a/gas/doc/Makefile.am b/gas/doc/Makefile.am index 6a02ccf..1a91757 100644 --- a/gas/doc/Makefile.am +++ b/gas/doc/Makefile.am @@ -49,6 +49,7 @@ CPU_DOCS = \ c-m32r.texi \ c-m68hc11.texi \ c-m68k.texi \ + c-microblaze.texi \ c-mips.texi \ c-mmix.texi \ c-mt.texi \ diff --git a/gas/doc/Makefile.in b/gas/doc/Makefile.in index 847b352a..de4d839 100644 --- a/gas/doc/Makefile.in +++ b/gas/doc/Makefile.in @@ -270,6 +270,7 @@ CPU_DOCS = \ c-m32r.texi \ c-m68hc11.texi \ c-m68k.texi \ + c-microblaze.texi \ c-mips.texi \ c-mmix.texi \ c-mt.texi \ diff --git a/gas/doc/all.texi b/gas/doc/all.texi index 9a94e6b..9bca41d 100644 --- a/gas/doc/all.texi +++ b/gas/doc/all.texi @@ -50,6 +50,7 @@ @set M68HC11 @set M680X0 @set MCORE +@set MICROBLAZE @set MIPS @set MMIX @set MS1 diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo index 3af86f8..ae56183 100644 --- a/gas/doc/as.texinfo +++ b/gas/doc/as.texinfo @@ -363,6 +363,10 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. [@b{-jsri2bsr}] [@b{-sifilter}] [@b{-relax}] [@b{-mcpu=[210|340]}] @end ifset +@ifset MICROBLAZE +@emph{Target MICROBLAZE options:} +@c MicroBlaze has no machine-dependent assembler options. +@end ifset @ifset MIPS @emph{Target MIPS options:} @@ -6766,6 +6770,9 @@ subject, see the hardware manufacturer's manual. @ifset M68HC11 * M68HC11-Dependent:: M68HC11 and 68HC12 Dependent Features @end ifset +@ifset MICROBLAZE +* MicroBlaze-Dependent:: MICROBLAZE Dependent Features +@end ifset @ifset MIPS * MIPS-Dependent:: MIPS Dependent Features @end ifset @@ -6934,6 +6941,10 @@ family. @include c-m68hc11.texi @end ifset +@ifset MICROBLAZE +@include c-microblaze.texi +@end ifset + @ifset MIPS @include c-mips.texi @end ifset diff --git a/gas/testsuite/gas/arm/align.d b/gas/testsuite/gas/arm/align.d index 92aff42..a15ed8c 100644 --- a/gas/testsuite/gas/arm/align.d +++ b/gas/testsuite/gas/arm/align.d @@ -1,6 +1,7 @@ # name: ARM V6t2 Alignment # as: -march=armv6kt2 # objdump: -dr --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* .*: +file format .*arm.* diff --git a/include/ChangeLog b/include/ChangeLog index c681a33..b8d14ec 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,7 @@ +2009-08-06 Michael Eager <eager@eagercon.com> + + * dis-asm.h: Decl print_insn_microblaze(). + 2009-07-24 Ian Lance Taylor <iant@google.com> * libiberty.h (crc32): Declare. diff --git a/include/dis-asm.h b/include/dis-asm.h index b7949c1..47236a0 100644 --- a/include/dis-asm.h +++ b/include/dis-asm.h @@ -265,6 +265,7 @@ extern int print_insn_maxq_big (bfd_vma, disassemble_info *); extern int print_insn_maxq_little (bfd_vma, disassemble_info *); extern int print_insn_mcore (bfd_vma, disassemble_info *); extern int print_insn_mep (bfd_vma, disassemble_info *); +extern int print_insn_microblaze (bfd_vma, disassemble_info *); extern int print_insn_mmix (bfd_vma, disassemble_info *); extern int print_insn_mn10200 (bfd_vma, disassemble_info *); extern int print_insn_mn10300 (bfd_vma, disassemble_info *); diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog index 113403d..8b045d4 100644 --- a/include/elf/ChangeLog +++ b/include/elf/ChangeLog @@ -1,3 +1,8 @@ +2009-08-06 Michael Eager <eager@eagercon.com> + + * elf/common.h: Define EM_MICROBLAZE & EM_MICROBLAZE_OLD. + * elf/microblaze.h: New reloc definitions. + 2009-07-30 Alan Modra <amodra@bigpond.net.au> * ppc64.h: Add R_PPC64_JMP_IREL, R_PPC64_REL16, R_PPC64_REL16_LO, diff --git a/include/elf/common.h b/include/elf/common.h index 33ec16a..a229a12 100644 --- a/include/elf/common.h +++ b/include/elf/common.h @@ -241,6 +241,8 @@ #define EM_L1OM 180 /* Intel L1OM */ #define EM_INTEL181 181 /* Reserved by Intel */ #define EM_INTEL182 182 /* Reserved by Intel */ +#define EM_MICROBLAZE 183 /* Xilinx MicroBlaze */ + /* If it is necessary to assign new unofficial EM_* values, please pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision @@ -344,6 +346,8 @@ /* Old Sunplus S+core7 backend magic number. Written in the absence of an ABI. */ #define EM_SCORE_OLD 95 +#define EM_MICROBLAZE_OLD 0xbaab /* Old MicroBlaze */ + /* See the above comment before you add a new EM_* value here. */ /* Values for e_version. */ diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h new file mode 100644 index 0000000..5999cb0 --- /dev/null +++ b/include/elf/microblaze.h @@ -0,0 +1,63 @@ +/* Xilinx MicroBlaze support for BFD. + + Copyright 2009 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + + +/* This file holds definitions specific to the MICROBLAZE ELF ABI. */ +#ifndef _ELF_MICROBLAZE_H +#define _ELF_MICROBLAZE_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_microblaze_reloc_type) + RELOC_NUMBER (R_MICROBLAZE_NONE, 0) + RELOC_NUMBER (R_MICROBLAZE_32, 1) + RELOC_NUMBER (R_MICROBLAZE_32_PCREL, 2) + RELOC_NUMBER (R_MICROBLAZE_64_PCREL, 3) + RELOC_NUMBER (R_MICROBLAZE_32_PCREL_LO, 4) + RELOC_NUMBER (R_MICROBLAZE_64, 5) + RELOC_NUMBER (R_MICROBLAZE_32_LO, 6) + RELOC_NUMBER (R_MICROBLAZE_SRO32, 7) + RELOC_NUMBER (R_MICROBLAZE_SRW32, 8) + RELOC_NUMBER (R_MICROBLAZE_64_NONE, 9) + RELOC_NUMBER (R_MICROBLAZE_32_SYM_OP_SYM, 10) + RELOC_NUMBER (R_MICROBLAZE_GNU_VTINHERIT, 11) + RELOC_NUMBER (R_MICROBLAZE_GNU_VTENTRY, 12) + RELOC_NUMBER (R_MICROBLAZE_GOTPC_64, 13) /* PC-relative GOT offset. */ + RELOC_NUMBER (R_MICROBLAZE_GOT_64, 14) /* GOT entry offset. */ + RELOC_NUMBER (R_MICROBLAZE_PLT_64, 15) /* PLT offset (PC-relative). */ + RELOC_NUMBER (R_MICROBLAZE_REL, 16) /* Adjust by program base. */ + RELOC_NUMBER (R_MICROBLAZE_JUMP_SLOT, 17) /* Create PLT entry. */ + RELOC_NUMBER (R_MICROBLAZE_GLOB_DAT, 18) /* Create GOT entry. */ + RELOC_NUMBER (R_MICROBLAZE_GOTOFF_64, 19) /* Offset relative to GOT. */ + RELOC_NUMBER (R_MICROBLAZE_GOTOFF_32, 20) /* Offset relative to GOT. */ + RELOC_NUMBER (R_MICROBLAZE_COPY, 21) /* Runtime copy. */ + +END_RELOC_NUMBERS (R_MICROBLAZE_max) + +/* Global base address names. */ +#define RO_SDA_ANCHOR_NAME "_SDA2_BASE_" +#define RW_SDA_ANCHOR_NAME "_SDA_BASE_" + +/* Section Attributes. */ +#define SHF_MICROBLAZE_NOREAD 0x80000000 + +#endif /* _ELF_MICROBLAZE_H */ diff --git a/ld/ChangeLog b/ld/ChangeLog index 742b567..554687f 100644 --- a/ld/ChangeLog +++ b/ld/ChangeLog @@ -1,3 +1,13 @@ +2009-08-06 Michael Eager <eager@eagercon.com> + + * Makefile.am: Add eelf32mb_linux.o, eelf32microblaze.o to + ALL_EMULATIONS, targets. + * Makefile.in: Regenerate. + * configure.tgt: Add microblaze*-linux*, microblaze* targets. + * emulparams/elf32mb_linux.sh: New. + * emulparams/elf32microblaze.sh. New. + * scripttempl/elfmicroblaze.sc: New. + 2009-08-05 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com> * emulparams/elf32_spu.sh (OTHER_READONLY_SECTIONS): Add .fixup diff --git a/ld/Makefile.am b/ld/Makefile.am index b4e291c..785966d 100644 --- a/ld/Makefile.am +++ b/ld/Makefile.am @@ -191,6 +191,8 @@ ALL_EMULATIONS = \ eelf32m32c.o \ eelf32mcore.o \ eelf32mep.o \ + eelf32mb_linux.o \ + eelf32microblaze.o \ eelf32mipswindiss.o \ eelf32mt.o \ eelf32openrisc.o \ @@ -858,6 +860,12 @@ eelf32lmip.c: $(srcdir)/emulparams/elf32lmip.sh \ $(srcdir)/emulparams/elf32bmip.sh $(ELF_DEPS) \ $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} ${GENSCRIPTS} elf32lmip "$(tdir_elf32lmip)" +eelf32mb_linux.c: $(srcdir)/emulparams/elf32mb_linux.sh \ + $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} + ${GENSCRIPTS} elf32mb_linux "$(tdir_microblaze)" + eelf32microblaze.c: $(srcdir)/emulparams/elf32microblaze.sh \ + $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elfmicroblaze.sc ${GEN_DEPENDS} + ${GENSCRIPTS} elf32microblaze "$(tdir_microblaze)" eelf32mipswindiss.c: $(srcdir)/emulparams/elf32mipswindiss.sh $(ELF_DEPS) \ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} ${GENSCRIPTS} elf32mipswindiss "$(tdir_elf32mipswindiss)" diff --git a/ld/Makefile.in b/ld/Makefile.in index 213f3ea..9c768c4 100644 --- a/ld/Makefile.in +++ b/ld/Makefile.in @@ -456,6 +456,8 @@ ALL_EMULATIONS = \ eelf32m32c.o \ eelf32mcore.o \ eelf32mep.o \ + eelf32mb_linux.o \ + eelf32microblaze.o \ eelf32mipswindiss.o \ eelf32mt.o \ eelf32openrisc.o \ @@ -1705,6 +1707,12 @@ eelf32lmip.c: $(srcdir)/emulparams/elf32lmip.sh \ $(srcdir)/emulparams/elf32bmip.sh $(ELF_DEPS) \ $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} ${GENSCRIPTS} elf32lmip "$(tdir_elf32lmip)" +eelf32mb_linux.c: $(srcdir)/emulparams/elf32mb_linux.sh \ + $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} + ${GENSCRIPTS} elf32mb_linux "$(tdir_microblaze)" + eelf32microblaze.c: $(srcdir)/emulparams/elf32microblaze.sh \ + $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elfmicroblaze.sc ${GEN_DEPENDS} + ${GENSCRIPTS} elf32microblaze "$(tdir_microblaze)" eelf32mipswindiss.c: $(srcdir)/emulparams/elf32mipswindiss.sh $(ELF_DEPS) \ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} ${GENSCRIPTS} elf32mipswindiss "$(tdir_elf32mipswindiss)" diff --git a/ld/configure.tgt b/ld/configure.tgt index fcb8eeb..d6d86ab 100644 --- a/ld/configure.tgt +++ b/ld/configure.tgt @@ -361,6 +361,9 @@ mcore-*-pe) targ_emul=mcorepe ; mcore-*-elf) targ_emul=elf32mcore ;; mep-*-elf) targ_emul=elf32mep ;; +microblaze*-linux*) + targ_emul="elf32mb_linux" ;; +microblaze*) targ_emul=elf32microblaze ;; mips*-*-pe) targ_emul=mipspe ; targ_extra_ofiles="deffilep.o pe-dll.o" ;; mips*-dec-ultrix*) targ_emul=mipslit ;; diff --git a/ld/emulparams/elf32mb_linux.sh b/ld/emulparams/elf32mb_linux.sh new file mode 100644 index 0000000..3503bb1 --- /dev/null +++ b/ld/emulparams/elf32mb_linux.sh @@ -0,0 +1,17 @@ +SCRIPT_NAME=elf +OUTPUT_FORMAT="elf32-microblaze" +TEXT_START_ADDR=0x10000000 +NONPAGED_TEXT_START_ADDR=0x28 +ALIGNMENT=4 +MAXPAGESIZE=0x1000 +COMMONPAGESIZE=0x1000 +ARCH=microblaze + +NOP=0x80000000 + +TEMPLATE_NAME=elf32 +GENERATE_SHLIB_SCRIPT=yes +GENERATE_PIE_SCRIPT=yes +NO_SMALL_DATA=yes +SEPARATE_GOTPLT=12 + diff --git a/ld/emulparams/elf32microblaze.sh b/ld/emulparams/elf32microblaze.sh new file mode 100644 index 0000000..ccc20d1 --- /dev/null +++ b/ld/emulparams/elf32microblaze.sh @@ -0,0 +1,23 @@ +SCRIPT_NAME=elfmicroblaze +OUTPUT_FORMAT="elf32-microblaze" +#TEXT_START_ADDR=0 +NONPAGED_TEXT_START_ADDR=0x28 +ALIGNMENT=4 +MAXPAGESIZE=4 +ARCH=microblaze +EMBEDDED=yes + +NOP=0x80000000 + +# Hmmm, there's got to be a better way. This sets the stack to the +# top of the simulator memory (2^19 bytes). +#PAGE_SIZE=0x1000 +#DATA_ADDR=0x10000 +#OTHER_RELOCATING_SECTIONS='.stack 0x7000 : { _stack = .; *(.stack) }' +#$@{RELOCATING+ PROVIDE (__stack = 0x7000);@} +#OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);' + +TEMPLATE_NAME=elf32 +#GENERATE_SHLIB_SCRIPT=yes + + diff --git a/ld/scripttempl/elf32cr16.sc b/ld/scripttempl/elf32cr16.sc index 69b66e5..7c357c1 100644 --- a/ld/scripttempl/elf32cr16.sc +++ b/ld/scripttempl/elf32cr16.sc @@ -133,21 +133,21 @@ SECTIONS The heap and stack are aligned to the bus width, as a speed optimization for accessing data located there. */ - .heap : + .heap (NOLOAD) : { . = ALIGN(4); __HEAP_START = .; . += 0x2000; __HEAP_MAX = .; } > ram - .stack : + .stack (NOLOAD) : { . = ALIGN(4); . += 0x6000; __STACK_START = .; } > ram - .istack : + .istack (NOLOAD) : { . = ALIGN(4); . += 0x100; diff --git a/ld/scripttempl/elf32cr16c.sc b/ld/scripttempl/elf32cr16c.sc index 70cbb59..56bab60 100644 --- a/ld/scripttempl/elf32cr16c.sc +++ b/ld/scripttempl/elf32cr16c.sc @@ -31,18 +31,18 @@ SECTIONS there. The alignment to 4 bytes is compatible for both the CR16C bus width (2 bytes) and CR16CPlus bus width (4 bytes). */ - .text : { __TEXT_START = .; *(.text) __TEXT_END = .; } > rom - .rdata : { __RDATA_START = .; *(.rdata_4) *(.rdata_2) *(.rdata_1) __RDATA_END = .; } > near_rom - .ctor ALIGN(4) : { __CTOR_LIST = .; *(.ctors) __CTOR_END = .; } > near_rom - .dtor ALIGN(4) : { __DTOR_LIST = .; *(.dtors) __DTOR_END = .; } > near_rom - .data : { __DATA_START = .; *(.data_4) *(.data_2) *(.data_1) *(.data) __DATA_END = .; } > ram AT > rom - .bss (NOLOAD) : { __BSS_START = .; *(.bss_4) *(.bss_2) *(.bss_1) *(.bss) *(COMMON) __BSS_END = .; } > ram - .nrdata : { __NRDATA_START = .; *(.nrdat_4) *(.nrdat_2) *(.nrdat_1) __NRDATA_END = .; } > near_rom - .ndata : { __NDATA_START = .; *(.ndata_4) *(.ndata_2) *(.ndata_1) __NDATA_END = .; } > near_ram AT > rom - .nbss (NOLOAD) : { __NBSS_START = .; *(.nbss_4) *(.nbss_2) *(.nbss_1) *(.ncommon) __NBSS_END = .; } > near_ram - .heap : { . = ALIGN(4); __HEAP_START = .; . += 0x2000; __HEAP_MAX = .; } > near_ram - .stack : { . = ALIGN(4); . += 0x6000; __STACK_START = .; } > ram - .istack : { . = ALIGN(2); . += 0x100; __ISTACK_START = .; } > ram + .text : { __TEXT_START = .; *(.text) __TEXT_END = .; } > rom + .rdata : { __RDATA_START = .; *(.rdata_4) *(.rdata_2) *(.rdata_1) __RDATA_END = .; } > near_rom + .ctor ALIGN(4) : { __CTOR_LIST = .; *(.ctors) __CTOR_END = .; } > near_rom + .dtor ALIGN(4) : { __DTOR_LIST = .; *(.dtors) __DTOR_END = .; } > near_rom + .data : { __DATA_START = .; *(.data_4) *(.data_2) *(.data_1) *(.data) __DATA_END = .; } > ram AT > rom + .bss (NOLOAD) : { __BSS_START = .; *(.bss_4) *(.bss_2) *(.bss_1) *(.bss) *(COMMON) __BSS_END = .; } > ram + .nrdata : { __NRDATA_START = .; *(.nrdat_4) *(.nrdat_2) *(.nrdat_1) __NRDATA_END = .; } > near_rom + .ndata : { __NDATA_START = .; *(.ndata_4) *(.ndata_2) *(.ndata_1) __NDATA_END = .; } > near_ram AT > rom + .nbss (NOLOAD) : { __NBSS_START = .; *(.nbss_4) *(.nbss_2) *(.nbss_1) *(.ncommon) __NBSS_END = .; } > near_ram + .heap (NOLOAD) : { . = ALIGN(4); __HEAP_START = .; . += 0x2000; __HEAP_MAX = .; } > near_ram + .stack (NOLOAD) : { . = ALIGN(4); . += 0x6000; __STACK_START = .; } > ram + .istack (NOLOAD) : { . = ALIGN(2); . += 0x100; __ISTACK_START = .; } > ram } __DATA_IMAGE_START = LOADADDR(.data); diff --git a/ld/scripttempl/elf32crx.sc b/ld/scripttempl/elf32crx.sc index c3d6751..514254a 100644 --- a/ld/scripttempl/elf32crx.sc +++ b/ld/scripttempl/elf32crx.sc @@ -135,21 +135,21 @@ SECTIONS The heap and stack are aligned to the bus width, as a speed optimization for accessing data located there. */ - .heap : + .heap (NOLOAD) : { . = ALIGN(4); __HEAP_START = .; . += 0x2000; __HEAP_MAX = .; } > ram - .stack : + .stack (NOLOAD) : { . = ALIGN(4); . += 0x6000; __STACK_START = .; } > ram - .istack : + .istack (NOLOAD) : { . = ALIGN(4); . += 0x100; diff --git a/ld/scripttempl/elfmicroblaze.sc b/ld/scripttempl/elfmicroblaze.sc new file mode 100644 index 0000000..7677261 --- /dev/null +++ b/ld/scripttempl/elfmicroblaze.sc @@ -0,0 +1,222 @@ +# Adapted from mips.sc +# These variables may be overridden by the emulation file. The +# defaults are appropriate for a DECstation running Ultrix. +test -z "$ENTRY" && ENTRY=_start + +#test -z "$TEXT_START_ADDR" && TEXT_START_ADDR="0x0" + +CTOR=".ctors ${CONSTRUCTING-0} : + { + ${CONSTRUCTING+${CTOR_START}} + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + + KEEP (*crtbegin.o(.ctors)) + + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + ${CONSTRUCTING+${CTOR_END}} + }" + +DTOR=" .dtors ${CONSTRUCTING-0} : + { + ${CONSTRUCTING+${DTOR_START}} + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + ${CONSTRUCTING+${DTOR_END}} + }" + +cat <<EOF +OUTPUT_FORMAT("${OUTPUT_FORMAT}", "${BIG_OUTPUT_FORMAT}", + "${LITTLE_OUTPUT_FORMAT}") +/*${LIB_SEARCH_DIRS}*/ +${RELOCATING+${LIB_SEARCH_DIRS}} + +ENTRY(${ENTRY}) + +_TEXT_START_ADDR = DEFINED(_TEXT_START_ADDR) ? _TEXT_START_ADDR : 0x50; +_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x0; +_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400; + +SECTIONS +{ + .vectors.reset 0x0 : { KEEP (*(.vectors.reset)) } = 0 + .vectors.sw_exception 0x8 : { KEEP (*(.vectors.sw_exception)) } = 0 + .vectors.interrupt 0x10 : { KEEP (*(.vectors.interrupt)) } = 0 + .vectors.debug_sw_break 0x18 : { KEEP (*(.vectors.debug_sw_break)) } = 0 + .vectors.hw_exception 0x20 : { KEEP (*(.vectors.hw_exception)) } = 0 + + ${RELOCATING+. = _TEXT_START_ADDR;} + + ${RELOCATING+ _ftext = .;} + .text : { + ${RELOCATING+*(.text)} + ${RELOCATING+*(.text.*)} + ${RELOCATING+*(.gnu.linkonce.t.*)} + } + ${RELOCATING+ _etext = .;} + + .init : { KEEP (*(.init)) } =0 + .fini : { KEEP (*(.fini)) } =0 + + ${RELOCATING+PROVIDE (__CTOR_LIST__ = .);} + ${RELOCATING+PROVIDE (___CTOR_LIST__ = .);} + ${RELOCATING+${CTOR}} + ${RELOCATING+PROVIDE (__CTOR_END__ = .);} + ${RELOCATING+PROVIDE (___CTOR_END__ = .);} + + ${RELOCATING+PROVIDE (__DTOR_LIST__ = .);} + ${RELOCATING+PROVIDE (___DTOR_LIST__ = .);} + ${RELOCATING+${DTOR}} + ${RELOCATING+PROVIDE (__DTOR_END__ = .);} + ${RELOCATING+PROVIDE (___DTOR_END__ = .);} + + ${RELOCATING+ . = ALIGN(4);} + ${RELOCATING+ _frodata = . ;} + .rodata : { + ${RELOCATING+*(.rodata)} + ${RELOCATING+*(.rodata.*)} + ${RELOCATING+*(.gnu.linkonce.r.*)} + ${CONSTRUCTING+CONSTRUCTORS}; /* Is this needed? */ + } + ${RELOCATING+ _erodata = .;} + + /* Alignments by 8 to ensure that _SDA2_BASE_ on a word boundary */ + /* Note that .sdata2 and .sbss2 must be contiguous */ + ${RELOCATING+. = ALIGN(8);} + ${RELOCATING+ _ssrw = .;} + .sdata2 : { + ${RELOCATING+*(.sdata2)} + ${RELOCATING+*(.sdata2.*)} + ${RELOCATING+*(.gnu.linkonce.s2.*)} + } + ${RELOCATING+. = ALIGN(4);} + .sbss2 : { + ${RELOCATING+PROVIDE (__sbss2_start = .);} + ${RELOCATING+*(.sbss2)} + ${RELOCATING+*(.sbss2.*)} + ${RELOCATING+*(.gnu.linkonce.sb2.*)} + ${RELOCATING+PROVIDE (__sbss2_end = .);} + } + ${RELOCATING+. = ALIGN(8);} + ${RELOCATING+ _essrw = .;} + ${RELOCATING+ _ssrw_size = _essrw - _ssrw;} + ${RELOCATING+ PROVIDE (_SDA2_BASE_ = _ssrw + (_ssrw_size / 2 ));} + + ${RELOCATING+ . = ALIGN(4);} + ${RELOCATING+ _fdata = .;} + .data : { + ${RELOCATING+*(.data)} + ${RELOCATING+*(.gnu.linkonce.d.*)} + ${CONSTRUCTING+CONSTRUCTORS}; /* Is this needed? */ + } + ${RELOCATING+ _edata = . ;} + + /* Added to handle pic code */ + .got : { + ${RELOCATING+*(.got)} + } + + .got1 : { + ${RELOCATING+*(.got1)} + } + + .got2 : { + ${RELOCATING+*(.got2)} + } + + /* Added by Sathya to handle C++ exceptions */ + .eh_frame : { + ${RELOCATING+*(.eh_frame)} + } + + .jcr : { + ${RELOCATING+*(.jcr)} + } + + .gcc_except_table : { + ${RELOCATING+*(.gcc_except_table)} + } + + /* Alignments by 8 to ensure that _SDA_BASE_ on a word boundary */ + /* Note that .sdata and .sbss must be contiguous */ + ${RELOCATING+. = ALIGN(8);} + ${RELOCATING+ _ssro = .;} + .sdata : { + ${RELOCATING+*(.sdata)} + ${RELOCATING+*(.sdata.*)} + ${RELOCATING+*(.gnu.linkonce.s.*)} + } + ${RELOCATING+. = ALIGN(4);} + .sbss : { + ${RELOCATING+PROVIDE (__sbss_start = .);} + ${RELOCATING+*(.sbss)} + ${RELOCATING+*(.sbss.*)} + ${RELOCATING+*(.gnu.linkonce.sb.*)} + ${RELOCATING+PROVIDE (__sbss_end = .);} + } + ${RELOCATING+. = ALIGN(8);} + ${RELOCATING+ _essro = .;} + ${RELOCATING+ _ssro_size = _essro - _ssro;} + ${RELOCATING+PROVIDE (_SDA_BASE_ = _ssro + (_ssro_size / 2 ));} + + ${RELOCATING+ . = ALIGN(4);} + ${RELOCATING+ _fbss = .;} + .bss : { + ${RELOCATING+PROVIDE (__bss_start = .);} + ${RELOCATING+*(.bss)} + ${RELOCATING+*(.bss.*)} + ${RELOCATING+*(.gnu.linkonce.b.*)} + ${RELOCATING+*(COMMON)} + ${RELOCATING+. = ALIGN(4);} + + ${RELOCATING+PROVIDE (__bss_end = .);} + + } + + ${RELOCATING+ . = ALIGN(4);} + + .heap : { + ${RELOCATING+ _heap = .;} + ${RELOCATING+ _heap_start = .;} + ${RELOCATING+ . += _HEAP_SIZE;} + ${RELOCATING+ _heap_end = .;} + } + + ${RELOCATING+ . = ALIGN(4);} + + .stack : { + ${RELOCATING+ _stack_end = .;} + ${RELOCATING+ . += _STACK_SIZE;} + ${RELOCATING+ . = ALIGN(8);} + ${RELOCATING+ _stack = .;} + ${RELOCATING+ _end = .;} + } + + .tdata : { + ${RELOCATING+*(.tdata)} + ${RELOCATING+*(.tdata.*)} + ${RELOCATING+*(.gnu.linkonce.td.*)} + } + .tbss : { + ${RELOCATING+*(.tbss)} + ${RELOCATING+*(.tbss.*)} + ${RELOCATING+*(.gnu.linkonce.tb.*)} + } +} +EOF diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 4799105..ea06335 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,16 @@ +2009-08-06 Michael Eager <eager@eagercon.com> + + * Makefile.am: Add microblaze-opc.h to HFILES, microblaze-dis.c to + CFILES, microblaze-dis.lo to ALL_MACHINES, targets. + * Makefile.in: Regenerate. + * configure.in: Add bfd_microblaze_arch target. + * configure: Regenerate. + * disassemble.c: Define ARCH_microblaze, return + print_insn_microblaze(). + * microblaze-dis.c: New MicroBlaze disassembler. + * microblaze-opc.h: New MicroBlaze opcode definitions. + * microblaze-opcm.h: New MicroBlaze opcode types. + 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * configure.in: Handle bfd_l1om_arch. diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am index d2a76c7..077a9da 100644 --- a/opcodes/Makefile.am +++ b/opcodes/Makefile.am @@ -49,6 +49,7 @@ HFILES = \ m32r-desc.h m32r-opc.h \ mcore-opc.h \ mep-desc.h mep-opc.h \ + microblaze-opc.h \ mt-desc.h mt-opc.h \ openrisc-desc.h openrisc-opc.h \ score-opc.h \ @@ -160,6 +161,7 @@ CFILES = \ mep-ibld.c \ mep-opc.c \ mips-dis.c \ + microblaze-dis.c \ mips-opc.c \ mips16-opc.c \ m10200-dis.c \ @@ -315,6 +317,7 @@ ALL_MACHINES = \ mep-ibld.lo \ mep-opc.lo \ mips-dis.lo \ + microblaze-dis.lo \ mips-opc.lo \ mips16-opc.lo \ mmix-dis.lo \ @@ -1798,6 +1801,11 @@ mep-opc.lo: \ mep-desc.h \ mep-opc.h \ sysdep.h +microblaze-dis.lo: \ + microblaze-dis.c \ + microblaze-opc.h \ + $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h mips-dis.lo: \ mips-dis.c \ $(BFDDIR)/elf-bfd.h \ diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in index 9dc3c55..7554a37 100644 --- a/opcodes/Makefile.in +++ b/opcodes/Makefile.in @@ -287,6 +287,7 @@ HFILES = \ m32r-desc.h m32r-opc.h \ mcore-opc.h \ mep-desc.h mep-opc.h \ + microblaze-opc.h \ mt-desc.h mt-opc.h \ openrisc-desc.h openrisc-opc.h \ score-opc.h \ @@ -399,6 +400,7 @@ CFILES = \ mep-ibld.c \ mep-opc.c \ mips-dis.c \ + microblaze-dis.c \ mips-opc.c \ mips16-opc.c \ m10200-dis.c \ @@ -554,6 +556,7 @@ ALL_MACHINES = \ mep-ibld.lo \ mep-opc.lo \ mips-dis.lo \ + microblaze-dis.lo \ mips-opc.lo \ mips16-opc.lo \ mmix-dis.lo \ @@ -2363,6 +2366,11 @@ mep-opc.lo: \ mep-desc.h \ mep-opc.h \ sysdep.h +microblaze-dis.lo: \ + microblaze-dis.c \ + microblaze-opc.h \ + $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h mips-dis.lo: \ mips-dis.c \ $(BFDDIR)/elf-bfd.h \ diff --git a/opcodes/configure b/opcodes/configure index a363a7e..12d0f45 100755 --- a/opcodes/configure +++ b/opcodes/configure @@ -12787,6 +12787,7 @@ if test x${all_targets} = xfalse ; then bfd_maxq_arch) ta="$ta maxq-dis.lo" ;; bfd_mcore_arch) ta="$ta mcore-dis.lo" ;; bfd_mep_arch) ta="$ta mep-asm.lo mep-desc.lo mep-dis.lo mep-ibld.lo mep-opc.lo" using_cgen=yes ;; + bfd_microblaze_arch) ta="$ta microblaze-dis.lo" ;; bfd_mips_arch) ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo" ;; bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;; bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;; diff --git a/opcodes/configure.in b/opcodes/configure.in index b6a960a..c634470 100644 --- a/opcodes/configure.in +++ b/opcodes/configure.in @@ -238,6 +238,7 @@ if test x${all_targets} = xfalse ; then bfd_maxq_arch) ta="$ta maxq-dis.lo" ;; bfd_mcore_arch) ta="$ta mcore-dis.lo" ;; bfd_mep_arch) ta="$ta mep-asm.lo mep-desc.lo mep-dis.lo mep-ibld.lo mep-opc.lo" using_cgen=yes ;; + bfd_microblaze_arch) ta="$ta microblaze-dis.lo" ;; bfd_mips_arch) ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo" ;; bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;; bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;; diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index 9c226ba..7c4f734 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -56,6 +56,7 @@ #define ARCH_maxq #define ARCH_mcore #define ARCH_mep +#define ARCH_microblaze #define ARCH_mips #define ARCH_mmix #define ARCH_mn10200 @@ -264,6 +265,11 @@ disassembler (abfd) disassemble = print_insn_mt; break; #endif +#ifdef ARCH_microblaze + case bfd_arch_microblaze: + disassemble = print_insn_microblaze; + break; +#endif #ifdef ARCH_msp430 case bfd_arch_msp430: disassemble = print_insn_msp430; diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c new file mode 100644 index 0000000..178415e --- /dev/null +++ b/opcodes/microblaze-dis.c @@ -0,0 +1,527 @@ +/* Disassemble Xilinx microblaze instructions. + + Copyright 2009 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + + +#include "sysdep.h" +#define STATIC_TABLE +#define DEFINE_TABLE + +#include "microblaze-opc.h" +#include "dis-asm.h" +#include <strings.h> + +#define get_field_rd(instr) get_field (instr, RD_MASK, RD_LOW) +#define get_field_r1(instr) get_field (instr, RA_MASK, RA_LOW) +#define get_field_r2(instr) get_field (instr, RB_MASK, RB_LOW) +#define get_int_field_imm(instr) ((instr & IMM_MASK) >> IMM_LOW) +#define get_int_field_r1(instr) ((instr & RA_MASK) >> RA_LOW) + +static char * +get_field (long instr, long mask, unsigned short low) +{ + char tmpstr[25]; + + sprintf (tmpstr, "%s%d", register_prefix, (int)((instr & mask) >> low)); + return (strdup (tmpstr)); +} + +static char * +get_field_imm (long instr) +{ + char tmpstr[25]; + + sprintf (tmpstr, "%d", (short)((instr & IMM_MASK) >> IMM_LOW)); + return (strdup (tmpstr)); +} + +static char * +get_field_imm5 (long instr) +{ + char tmpstr[25]; + + sprintf (tmpstr, "%d", (short)((instr & IMM5_MASK) >> IMM_LOW)); + return (strdup (tmpstr)); +} + +static char * +get_field_rfsl (long instr) +{ + char tmpstr[25]; + + sprintf (tmpstr, "%s%d", fsl_register_prefix, + (short)((instr & RFSL_MASK) >> IMM_LOW)); + return (strdup (tmpstr)); +} + +static char * +get_field_imm15 (long instr) +{ + char tmpstr[25]; + + sprintf (tmpstr, "%d", (short)((instr & IMM15_MASK) >> IMM_LOW)); + return (strdup (tmpstr)); +} + +static char * +get_field_special (long instr, struct op_code_struct * op) +{ + char tmpstr[25]; + char spr[6]; + + switch ((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask)) + { + case REG_MSR_MASK : + strcpy (spr, "msr"); + break; + case REG_PC_MASK : + strcpy (spr, "pc"); + break; + case REG_EAR_MASK : + strcpy (spr, "ear"); + break; + case REG_ESR_MASK : + strcpy (spr, "esr"); + break; + case REG_FSR_MASK : + strcpy (spr, "fsr"); + break; + case REG_BTR_MASK : + strcpy (spr, "btr"); + break; + case REG_EDR_MASK : + strcpy (spr, "edr"); + break; + case REG_PID_MASK : + strcpy (spr, "pid"); + break; + case REG_ZPR_MASK : + strcpy (spr, "zpr"); + break; + case REG_TLBX_MASK : + strcpy (spr, "tlbx"); + break; + case REG_TLBLO_MASK : + strcpy (spr, "tlblo"); + break; + case REG_TLBHI_MASK : + strcpy (spr, "tlbhi"); + break; + case REG_TLBSX_MASK : + strcpy (spr, "tlbsx"); + break; + default : + if (((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) & 0xE000) + == REG_PVR_MASK) + { + sprintf (tmpstr, "%spvr%d", register_prefix, + (unsigned short)(((instr & IMM_MASK) >> IMM_LOW) + ^ op->immval_mask) ^ REG_PVR_MASK); + return (strdup (tmpstr)); + } + else + strcpy (spr, "pc"); + break; + } + + sprintf (tmpstr, "%s%s", register_prefix, spr); + return (strdup (tmpstr)); +} + +static unsigned long +read_insn_microblaze (bfd_vma memaddr, + struct disassemble_info *info, + struct op_code_struct **opr) +{ + unsigned char ibytes[4]; + int status; + struct op_code_struct * op; + unsigned long inst; + + status = info->read_memory_func (memaddr, ibytes, 4, info); + + if (status != 0) + { + info->memory_error_func (status, memaddr, info); + return 0; + } + + if (info->endian == BFD_ENDIAN_BIG) + inst = (ibytes[0] << 24) | (ibytes[1] << 16) | (ibytes[2] << 8) | ibytes[3]; + else if (info->endian == BFD_ENDIAN_LITTLE) + inst = (ibytes[3] << 24) | (ibytes[2] << 16) | (ibytes[1] << 8) | ibytes[0]; + else + abort (); + + /* Just a linear search of the table. */ + for (op = opcodes; op->name != 0; op ++) + if (op->bit_sequence == (inst & op->opcode_mask)) + break; + + *opr = op; + return inst; +} + + +int +print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) +{ + fprintf_ftype fprintf = info->fprintf_func; + void * stream = info->stream; + unsigned long inst, prev_inst; + struct op_code_struct * op, *pop; + int immval = 0; + bfd_boolean immfound = FALSE; + static bfd_vma prev_insn_addr = -1; /* Init the prev insn addr. */ + static int prev_insn_vma = -1; /* Init the prev insn vma. */ + int curr_insn_vma = info->buffer_vma; + + info->bytes_per_chunk = 4; + + inst = read_insn_microblaze (memaddr, info, &op); + if (inst == 0) + return -1; + + if (prev_insn_vma == curr_insn_vma) + { + if (memaddr-(info->bytes_per_chunk) == prev_insn_addr) + { + prev_inst = read_insn_microblaze (prev_insn_addr, info, &pop); + if (prev_inst == 0) + return -1; + if (pop->instr == imm) + { + immval = (get_int_field_imm (prev_inst) << 16) & 0xffff0000; + immfound = TRUE; + } + else + { + immval = 0; + immfound = FALSE; + } + } + } + + /* Make curr insn as prev insn. */ + prev_insn_addr = memaddr; + prev_insn_vma = curr_insn_vma; + + if (op->name == NULL) + fprintf (stream, ".short 0x%04x", inst); + else + { + fprintf (stream, "%s", op->name); + + switch (op->inst_type) + { + case INST_TYPE_RD_R1_R2: + fprintf (stream, "\t%s, %s, %s", get_field_rd (inst), + get_field_r1(inst), get_field_r2 (inst)); + break; + case INST_TYPE_RD_R1_IMM: + fprintf (stream, "\t%s, %s, %s", get_field_rd (inst), + get_field_r1(inst), get_field_imm (inst)); + if (info->print_address_func && get_int_field_r1 (inst) == 0 + && info->symbol_at_address_func) + { + if (immfound) + immval |= (get_int_field_imm (inst) & 0x0000ffff); + else + { + immval = get_int_field_imm (inst); + if (immval & 0x8000) + immval |= 0xFFFF0000; + } + if (immval > 0 && info->symbol_at_address_func (immval, info)) + { + fprintf (stream, "\t// "); + info->print_address_func (immval, info); + } + } + break; + case INST_TYPE_RD_R1_IMM5: + fprintf (stream, "\t%s, %s, %s", get_field_rd (inst), + get_field_r1(inst), get_field_imm5 (inst)); + break; + case INST_TYPE_RD_RFSL: + fprintf (stream, "\t%s, %s", get_field_rd (inst), get_field_rfsl (inst)); + break; + case INST_TYPE_R1_RFSL: + fprintf (stream, "\t%s, %s", get_field_r1 (inst), get_field_rfsl (inst)); + break; + case INST_TYPE_RD_SPECIAL: + fprintf (stream, "\t%s, %s", get_field_rd (inst), + get_field_special (inst, op)); + break; + case INST_TYPE_SPECIAL_R1: + fprintf (stream, "\t%s, %s", get_field_special (inst, op), + get_field_r1(inst)); + break; + case INST_TYPE_RD_R1: + fprintf (stream, "\t%s, %s", get_field_rd (inst), get_field_r1 (inst)); + break; + case INST_TYPE_R1_R2: + fprintf (stream, "\t%s, %s", get_field_r1 (inst), get_field_r2 (inst)); + break; + case INST_TYPE_R1_IMM: + fprintf (stream, "\t%s, %s", get_field_r1 (inst), get_field_imm (inst)); + /* The non-pc relative instructions are returns, which shouldn't + have a label printed. */ + if (info->print_address_func && op->inst_offset_type == INST_PC_OFFSET + && info->symbol_at_address_func) + { + if (immfound) + immval |= (get_int_field_imm (inst) & 0x0000ffff); + else + { + immval = get_int_field_imm (inst); + if (immval & 0x8000) + immval |= 0xFFFF0000; + } + immval += memaddr; + if (immval > 0 && info->symbol_at_address_func (immval, info)) + { + fprintf (stream, "\t// "); + info->print_address_func (immval, info); + } + else + { + fprintf (stream, "\t\t// "); + fprintf (stream, "%x", immval); + } + } + break; + case INST_TYPE_RD_IMM: + fprintf (stream, "\t%s, %s", get_field_rd (inst), get_field_imm (inst)); + if (info->print_address_func && info->symbol_at_address_func) + { + if (immfound) + immval |= (get_int_field_imm (inst) & 0x0000ffff); + else + { + immval = get_int_field_imm (inst); + if (immval & 0x8000) + immval |= 0xFFFF0000; + } + if (op->inst_offset_type == INST_PC_OFFSET) + immval += (int) memaddr; + if (info->symbol_at_address_func (immval, info)) + { + fprintf (stream, "\t// "); + info->print_address_func (immval, info); + } + } + break; + case INST_TYPE_IMM: + fprintf (stream, "\t%s", get_field_imm (inst)); + if (info->print_address_func && info->symbol_at_address_func + && op->instr != imm) + { + if (immfound) + immval |= (get_int_field_imm (inst) & 0x0000ffff); + else + { + immval = get_int_field_imm (inst); + if (immval & 0x8000) + immval |= 0xFFFF0000; + } + if (op->inst_offset_type == INST_PC_OFFSET) + immval += (int) memaddr; + if (immval > 0 && info->symbol_at_address_func (immval, info)) + { + fprintf (stream, "\t// "); + info->print_address_func (immval, info); + } + else if (op->inst_offset_type == INST_PC_OFFSET) + { + fprintf (stream, "\t\t// "); + fprintf (stream, "%x", immval); + } + } + break; + case INST_TYPE_RD_R2: + fprintf (stream, "\t%s, %s", get_field_rd (inst), get_field_r2 (inst)); + break; + case INST_TYPE_R2: + fprintf (stream, "\t%s", get_field_r2 (inst)); + break; + case INST_TYPE_R1: + fprintf (stream, "\t%s", get_field_r1 (inst)); + break; + case INST_TYPE_RD_R1_SPECIAL: + fprintf (stream, "\t%s, %s", get_field_rd (inst), get_field_r2 (inst)); + break; + case INST_TYPE_RD_IMM15: + fprintf (stream, "\t%s, %s", get_field_rd (inst), get_field_imm15 (inst)); + break; + /* For tuqula instruction */ + case INST_TYPE_RD: + fprintf (stream, "\t%s", get_field_rd (inst)); + break; + case INST_TYPE_RFSL: + fprintf (stream, "\t%s", get_field_rfsl (inst)); + break; + default: + /* If the disassembler lags the instruction set. */ + fprintf (stream, "\tundecoded operands, inst is 0x%04x", inst); + break; + } + } + + /* Say how many bytes we consumed. */ + return 4; +} +#if 0 +static enum microblaze_instr +get_insn_microblaze (long inst, + bfd_boolean *isunsignedimm, + enum microblaze_instr_type *insn_type, + short *delay_slots) +{ + struct op_code_struct * op; + *isunsignedimm = FALSE; + + /* Just a linear search of the table. */ + for (op = opcodes; op->name != 0; op ++) + if (op->bit_sequence == (inst & op->opcode_mask)) + break; + + if (op->name == 0) + return invalid_inst; + else + { + *isunsignedimm = (op->inst_type == INST_TYPE_RD_R1_UNSIGNED_IMM); + *insn_type = op->instr_type; + *delay_slots = op->delay_slots; + return op->instr; + } +} + +short +get_delay_slots_microblaze (long inst) +{ + bfd_boolean isunsignedimm; + enum microblaze_instr_type insn_type; + enum microblaze_instr op; + short delay_slots; + + op = get_insn_microblaze (inst, &isunsignedimm, &insn_type, &delay_slots); + if (op == invalid_inst) + return 0; + else + return delay_slots; +} + +enum microblaze_instr +microblaze_decode_insn (long insn, int *rd, int *ra, int *rb, int *imm) +{ + enum microblaze_instr op; + bfd_boolean t1; + enum microblaze_instr_type t2; + short t3; + + op = get_insn_microblaze (insn, &t1, &t2, &t3); + *rd = (insn & RD_MASK) >> RD_LOW; + *ra = (insn & RA_MASK) >> RA_LOW; + *rb = (insn & RB_MASK) >> RB_LOW; + t3 = (insn & IMM_MASK) >> IMM_LOW; + *imm = (int) t3; + return (op); +} + +unsigned long +microblaze_get_target_address (long inst, bfd_boolean immfound, int immval, + long pcval, long r1val, long r2val, + bfd_boolean *targetvalid, + bfd_boolean *unconditionalbranch) +{ + struct op_code_struct * op; + long targetaddr = 0; + + *unconditionalbranch = FALSE; + /* Just a linear search of the table. */ + for (op = opcodes; op->name != 0; op ++) + if (op->bit_sequence == (inst & op->opcode_mask)) + break; + + if (op->name == 0) + { + *targetvalid = FALSE; + } + else if (op->instr_type == branch_inst) + { + switch (op->inst_type) + { + case INST_TYPE_R2: + *unconditionalbranch = TRUE; + /* Fall through. */ + case INST_TYPE_RD_R2: + case INST_TYPE_R1_R2: + targetaddr = r2val; + *targetvalid = TRUE; + if (op->inst_offset_type == INST_PC_OFFSET) + targetaddr += pcval; + break; + case INST_TYPE_IMM: + *unconditionalbranch = TRUE; + /* Fall through. */ + case INST_TYPE_RD_IMM: + case INST_TYPE_R1_IMM: + if (immfound) + { + targetaddr = (immval << 16) & 0xffff0000; + targetaddr |= (get_int_field_imm (inst) & 0x0000ffff); + } + else + { + targetaddr = get_int_field_imm (inst); + if (targetaddr & 0x8000) + targetaddr |= 0xFFFF0000; + } + if (op->inst_offset_type == INST_PC_OFFSET) + targetaddr += pcval; + *targetvalid = TRUE; + break; + default: + *targetvalid = FALSE; + break; + } + } + else if (op->instr_type == return_inst) + { + if (immfound) + { + targetaddr = (immval << 16) & 0xffff0000; + targetaddr |= (get_int_field_imm (inst) & 0x0000ffff); + } + else + { + targetaddr = get_int_field_imm (inst); + if (targetaddr & 0x8000) + targetaddr |= 0xFFFF0000; + } + targetaddr += r1val; + *targetvalid = TRUE; + } + else + *targetvalid = FALSE; + return targetaddr; +} +#endif diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h new file mode 100644 index 0000000..02ac83f --- /dev/null +++ b/opcodes/microblaze-opc.h @@ -0,0 +1,409 @@ +/* microblaze-opc.h -- MicroBlaze Opcodes + + Copyright 2009 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + + +#ifndef MICROBLAZE_OPC +#define MICROBLAZE_OPC + +#include "microblaze-opcm.h" + + +#define INST_TYPE_RD_R1_R2 0 +#define INST_TYPE_RD_R1_IMM 1 +#define INST_TYPE_RD_R1_UNSIGNED_IMM 2 +#define INST_TYPE_RD_R1 3 +#define INST_TYPE_RD_R2 4 +#define INST_TYPE_RD_IMM 5 +#define INST_TYPE_R2 6 +#define INST_TYPE_R1_R2 7 +#define INST_TYPE_R1_IMM 8 +#define INST_TYPE_IMM 9 +#define INST_TYPE_SPECIAL_R1 10 +#define INST_TYPE_RD_SPECIAL 11 +#define INST_TYPE_R1 12 +/* New instn type for barrel shift imms. */ +#define INST_TYPE_RD_R1_IMM5 13 +#define INST_TYPE_RD_RFSL 14 +#define INST_TYPE_R1_RFSL 15 + +/* New insn type for insn cache. */ +#define INST_TYPE_RD_R1_SPECIAL 16 + +/* New insn type for msrclr, msrset insns. */ +#define INST_TYPE_RD_IMM15 17 + +/* New insn type for tuqula rd - addik rd, r0, 42. */ +#define INST_TYPE_RD 18 + +/* New insn type for t*put. */ +#define INST_TYPE_RFSL 19 + +#define INST_TYPE_NONE 25 + + + +/* Instructions where the label address is resolved as a PC offset + (for branch label). */ +#define INST_PC_OFFSET 1 +/* Instructions where the label address is resolved as an absolute + value (for data mem or abs address). */ +#define INST_NO_OFFSET 0 + +#define IMMVAL_MASK_NON_SPECIAL 0x0000 +#define IMMVAL_MASK_MTS 0x4000 +#define IMMVAL_MASK_MFS 0x0000 + +#define OPCODE_MASK_H 0xFC000000 /* High 6 bits only. */ +#define OPCODE_MASK_H1 0xFFE00000 /* High 11 bits. */ +#define OPCODE_MASK_H2 0xFC1F0000 /* High 6 and bits 20-16. */ +#define OPCODE_MASK_H12 0xFFFF0000 /* High 16. */ +#define OPCODE_MASK_H4 0xFC0007FF /* High 6 and low 11 bits. */ +#define OPCODE_MASK_H13S 0xFFE0EFF0 /* High 11 and 15:1 bits and last + nibble of last byte for spr. */ +#define OPCODE_MASK_H23S 0xFC1FC000 /* High 6, 20-16 and 15:1 bits and last + nibble of last byte for spr. */ +#define OPCODE_MASK_H34 0xFC00FFFF /* High 6 and low 16 bits. */ +#define OPCODE_MASK_H14 0xFFE007FF /* High 11 and low 11 bits. */ +#define OPCODE_MASK_H24 0xFC1F07FF /* High 6, bits 20-16 and low 11 bits. */ +#define OPCODE_MASK_H124 0xFFFF07FF /* High 16, and low 11 bits. */ +#define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits. */ +#define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */ +#define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */ +#define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */ +#define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */ + +/* New Mask for msrset, msrclr insns. */ +#define OPCODE_MASK_H23N 0xFC1F8000 /* High 6 and bits 11 - 16. */ + +#define DELAY_SLOT 1 +#define NO_DELAY_SLOT 0 + +#define MAX_OPCODES 280 + +struct op_code_struct +{ + char * name; + short inst_type; /* Registers and immediate values involved. */ + short inst_offset_type; /* Immediate vals offset from PC? (= 1 for branches). */ + short delay_slots; /* Info about delay slots needed after this instr. */ + short immval_mask; + unsigned long bit_sequence; /* All the fixed bits for the op are set and + all the variable bits (reg names, imm vals) + are set to 0. */ + unsigned long opcode_mask; /* Which bits define the opcode. */ + enum microblaze_instr instr; + enum microblaze_instr_type instr_type; + /* More info about output format here. */ +} opcodes[MAX_OPCODES] = +{ + {"add", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000000, OPCODE_MASK_H4, add, arithmetic_inst }, + {"rsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H4, rsub, arithmetic_inst }, + {"addc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000000, OPCODE_MASK_H4, addc, arithmetic_inst }, + {"rsubc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x0C000000, OPCODE_MASK_H4, rsubc, arithmetic_inst }, + {"addk", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x10000000, OPCODE_MASK_H4, addk, arithmetic_inst }, + {"rsubk", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000000, OPCODE_MASK_H4, rsubk, arithmetic_inst }, + {"cmp", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000001, OPCODE_MASK_H4, cmp, arithmetic_inst }, + {"cmpu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000003, OPCODE_MASK_H4, cmpu, arithmetic_inst }, + {"addkc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x18000000, OPCODE_MASK_H4, addkc, arithmetic_inst }, + {"rsubkc",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x1C000000, OPCODE_MASK_H4, rsubkc, arithmetic_inst }, + {"addi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, addi, arithmetic_inst }, + {"rsubi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, rsubi, arithmetic_inst }, + {"addic", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, addic, arithmetic_inst }, + {"rsubic",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, rsubic, arithmetic_inst }, + {"addik", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, addik, arithmetic_inst }, + {"rsubik",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, rsubik, arithmetic_inst }, + {"addikc",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, addikc, arithmetic_inst }, + {"rsubikc",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, rsubikc, arithmetic_inst }, + {"mul", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000000, OPCODE_MASK_H4, mul, mult_inst }, + {"mulh", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000001, OPCODE_MASK_H4, mulh, mult_inst }, + {"mulhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000003, OPCODE_MASK_H4, mulhu, mult_inst }, + {"mulhsu",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000002, OPCODE_MASK_H4, mulhsu, mult_inst }, + {"idiv", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x48000000, OPCODE_MASK_H4, idiv, div_inst }, + {"idivu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x48000002, OPCODE_MASK_H4, idivu, div_inst }, + {"bsll", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000400, OPCODE_MASK_H3, bsll, barrel_shift_inst }, + {"bsra", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000200, OPCODE_MASK_H3, bsra, barrel_shift_inst }, + {"bsrl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000000, OPCODE_MASK_H3, bsrl, barrel_shift_inst }, + {"get", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000000, OPCODE_MASK_H32, get, anyware_inst }, + {"put", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008000, OPCODE_MASK_H32, put, anyware_inst }, + {"nget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004000, OPCODE_MASK_H32, nget, anyware_inst }, + {"nput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C000, OPCODE_MASK_H32, nput, anyware_inst }, + {"cget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002000, OPCODE_MASK_H32, cget, anyware_inst }, + {"cput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A000, OPCODE_MASK_H32, cput, anyware_inst }, + {"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst }, + {"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst }, + {"muli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst }, + {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst }, + {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst }, + {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst }, + {"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, or, logical_inst }, + {"and", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, and, logical_inst }, + {"xor", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, xor, logical_inst }, + {"andn", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000000, OPCODE_MASK_H4, andn, logical_inst }, + {"pcmpbf",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000400, OPCODE_MASK_H4, pcmpbf, logical_inst }, + {"pcmpbc",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000400, OPCODE_MASK_H4, pcmpbc, logical_inst }, + {"pcmpeq",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000400, OPCODE_MASK_H4, pcmpeq, logical_inst }, + {"pcmpne",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000400, OPCODE_MASK_H4, pcmpne, logical_inst }, + {"sra", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000001, OPCODE_MASK_H34, sra, logical_inst }, + {"src", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000021, OPCODE_MASK_H34, src, logical_inst }, + {"srl", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000041, OPCODE_MASK_H34, srl, logical_inst }, + {"sext8", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000060, OPCODE_MASK_H34, sext8, logical_inst }, + {"sext16",INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000061, OPCODE_MASK_H34, sext16, logical_inst }, + {"wic", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst }, + {"wdc", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst }, + {"wdc.clear", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst }, + {"wdc.flush", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst }, + {"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst }, + {"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst }, + {"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst }, + {"brd", INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98100000, OPCODE_MASK_H124, brd, branch_inst }, + {"brld", INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98140000, OPCODE_MASK_H24, brld, branch_inst }, + {"bra", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98080000, OPCODE_MASK_H124, bra, branch_inst }, + {"brad", INST_TYPE_R2, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98180000, OPCODE_MASK_H124, brad, branch_inst }, + {"brald", INST_TYPE_RD_R2, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x981C0000, OPCODE_MASK_H24, brald, branch_inst }, + {"brk", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x980C0000, OPCODE_MASK_H24, microblaze_brk, branch_inst }, + {"beq", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C000000, OPCODE_MASK_H14, beq, branch_inst }, + {"beqd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E000000, OPCODE_MASK_H14, beqd, branch_inst }, + {"bne", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C200000, OPCODE_MASK_H14, bne, branch_inst }, + {"bned", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E200000, OPCODE_MASK_H14, bned, branch_inst }, + {"blt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C400000, OPCODE_MASK_H14, blt, branch_inst }, + {"bltd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E400000, OPCODE_MASK_H14, bltd, branch_inst }, + {"ble", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C600000, OPCODE_MASK_H14, ble, branch_inst }, + {"bled", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E600000, OPCODE_MASK_H14, bled, branch_inst }, + {"bgt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C800000, OPCODE_MASK_H14, bgt, branch_inst }, + {"bgtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E800000, OPCODE_MASK_H14, bgtd, branch_inst }, + {"bge", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9CA00000, OPCODE_MASK_H14, bge, branch_inst }, + {"bged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9EA00000, OPCODE_MASK_H14, bged, branch_inst }, + {"ori", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, ori, logical_inst }, + {"andi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, andi, logical_inst }, + {"xori", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, xori, logical_inst }, + {"andni", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, andni, logical_inst }, + {"imm", INST_TYPE_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB0000000, OPCODE_MASK_H12, imm, immediate_inst }, + {"rtsd", INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000000, OPCODE_MASK_H1, rtsd, return_inst }, + {"rtid", INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6200000, OPCODE_MASK_H1, rtid, return_inst }, + {"rtbd", INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6400000, OPCODE_MASK_H1, rtbd, return_inst }, + {"rted", INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6800000, OPCODE_MASK_H1, rted, return_inst }, + {"bri", INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8000000, OPCODE_MASK_H12, bri, branch_inst }, + {"brid", INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8100000, OPCODE_MASK_H12, brid, branch_inst }, + {"brlid", INST_TYPE_RD_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8140000, OPCODE_MASK_H2, brlid, branch_inst }, + {"brai", INST_TYPE_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8080000, OPCODE_MASK_H12, brai, branch_inst }, + {"braid", INST_TYPE_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8180000, OPCODE_MASK_H12, braid, branch_inst }, + {"bralid",INST_TYPE_RD_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB81C0000, OPCODE_MASK_H2, bralid, branch_inst }, + {"brki", INST_TYPE_RD_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB80C0000, OPCODE_MASK_H2, brki, branch_inst }, + {"beqi", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC000000, OPCODE_MASK_H1, beqi, branch_inst }, + {"beqid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE000000, OPCODE_MASK_H1, beqid, branch_inst }, + {"bnei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC200000, OPCODE_MASK_H1, bnei, branch_inst }, + {"bneid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE200000, OPCODE_MASK_H1, bneid, branch_inst }, + {"blti", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC400000, OPCODE_MASK_H1, blti, branch_inst }, + {"bltid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE400000, OPCODE_MASK_H1, bltid, branch_inst }, + {"blei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC600000, OPCODE_MASK_H1, blei, branch_inst }, + {"bleid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE600000, OPCODE_MASK_H1, bleid, branch_inst }, + {"bgti", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC800000, OPCODE_MASK_H1, bgti, branch_inst }, + {"bgtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE800000, OPCODE_MASK_H1, bgtid, branch_inst }, + {"bgei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBCA00000, OPCODE_MASK_H1, bgei, branch_inst }, + {"bgeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst }, + {"lbu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst }, + {"lhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst }, + {"lw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst }, + {"lwx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst }, + {"sb", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst }, + {"sh", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst }, + {"sw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst }, + {"swx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst }, + {"lbui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst }, + {"lhui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst }, + {"lwi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, lwi, memory_load_inst }, + {"sbi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF0000000, OPCODE_MASK_H, sbi, memory_store_inst }, + {"shi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF4000000, OPCODE_MASK_H, shi, memory_store_inst }, + {"swi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, swi, memory_store_inst }, + {"nop", INST_TYPE_NONE, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H1234, invalid_inst, logical_inst }, /* translates to or r0, r0, r0. */ + {"la", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* la translates to addik. */ + {"tuqula",INST_TYPE_RD, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3000002A, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* tuqula rd translates to addik rd, r0, 42. */ + {"not", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA800FFFF, OPCODE_MASK_H34, invalid_inst, logical_inst }, /* not translates to xori rd,ra,-1. */ + {"neg", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0. */ + {"rtb", INST_TYPE_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000004, OPCODE_MASK_H1, invalid_inst, return_inst }, /* rtb translates to rts rd, 4. */ + {"sub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra. */ + {"lmi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst }, + {"smi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, + {"msrset",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94100000, OPCODE_MASK_H23N, msrset, special_inst }, + {"msrclr",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94110000, OPCODE_MASK_H23N, msrclr, special_inst }, + {"fadd", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000000, OPCODE_MASK_H4, fadd, arithmetic_inst }, + {"frsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000080, OPCODE_MASK_H4, frsub, arithmetic_inst }, + {"fmul", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000100, OPCODE_MASK_H4, fmul, arithmetic_inst }, + {"fdiv", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000180, OPCODE_MASK_H4, fdiv, arithmetic_inst }, + {"fcmp.lt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000210, OPCODE_MASK_H4, fcmp_lt, arithmetic_inst }, + {"fcmp.eq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000220, OPCODE_MASK_H4, fcmp_eq, arithmetic_inst }, + {"fcmp.le", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000230, OPCODE_MASK_H4, fcmp_le, arithmetic_inst }, + {"fcmp.gt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000240, OPCODE_MASK_H4, fcmp_gt, arithmetic_inst }, + {"fcmp.ne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000250, OPCODE_MASK_H4, fcmp_ne, arithmetic_inst }, + {"fcmp.ge", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000260, OPCODE_MASK_H4, fcmp_ge, arithmetic_inst }, + {"fcmp.un", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000200, OPCODE_MASK_H4, fcmp_un, arithmetic_inst }, + {"flt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000280, OPCODE_MASK_H4, flt, arithmetic_inst }, + {"fint", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000300, OPCODE_MASK_H4, fint, arithmetic_inst }, + {"fsqrt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000380, OPCODE_MASK_H4, fsqrt, arithmetic_inst }, + {"tget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001000, OPCODE_MASK_H32, tget, anyware_inst }, + {"tcget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003000, OPCODE_MASK_H32, tcget, anyware_inst }, + {"tnget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005000, OPCODE_MASK_H32, tnget, anyware_inst }, + {"tncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007000, OPCODE_MASK_H32, tncget, anyware_inst }, + {"tput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009000, OPCODE_MASK_H32, tput, anyware_inst }, + {"tcput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B000, OPCODE_MASK_H32, tcput, anyware_inst }, + {"tnput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D000, OPCODE_MASK_H32, tnput, anyware_inst }, + {"tncput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F000, OPCODE_MASK_H32, tncput, anyware_inst }, + + {"eget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000400, OPCODE_MASK_H32, eget, anyware_inst }, + {"ecget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002400, OPCODE_MASK_H32, ecget, anyware_inst }, + {"neget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004400, OPCODE_MASK_H32, neget, anyware_inst }, + {"necget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006400, OPCODE_MASK_H32, necget, anyware_inst }, + {"eput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008400, OPCODE_MASK_H32, eput, anyware_inst }, + {"ecput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A400, OPCODE_MASK_H32, ecput, anyware_inst }, + {"neput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C400, OPCODE_MASK_H32, neput, anyware_inst }, + {"necput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E400, OPCODE_MASK_H32, necput, anyware_inst }, + + {"teget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001400, OPCODE_MASK_H32, teget, anyware_inst }, + {"tecget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003400, OPCODE_MASK_H32, tecget, anyware_inst }, + {"tneget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005400, OPCODE_MASK_H32, tneget, anyware_inst }, + {"tnecget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007400, OPCODE_MASK_H32, tnecget, anyware_inst }, + {"teput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009400, OPCODE_MASK_H32, teput, anyware_inst }, + {"tecput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B400, OPCODE_MASK_H32, tecput, anyware_inst }, + {"tneput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D400, OPCODE_MASK_H32, tneput, anyware_inst }, + {"tnecput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F400, OPCODE_MASK_H32, tnecput, anyware_inst }, + + {"aget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000800, OPCODE_MASK_H32, aget, anyware_inst }, + {"caget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002800, OPCODE_MASK_H32, caget, anyware_inst }, + {"naget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004800, OPCODE_MASK_H32, naget, anyware_inst }, + {"ncaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006800, OPCODE_MASK_H32, ncaget, anyware_inst }, + {"aput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008800, OPCODE_MASK_H32, aput, anyware_inst }, + {"caput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A800, OPCODE_MASK_H32, caput, anyware_inst }, + {"naput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C800, OPCODE_MASK_H32, naput, anyware_inst }, + {"ncaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E800, OPCODE_MASK_H32, ncaput, anyware_inst }, + + {"taget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001800, OPCODE_MASK_H32, taget, anyware_inst }, + {"tcaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003800, OPCODE_MASK_H32, tcaget, anyware_inst }, + {"tnaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005800, OPCODE_MASK_H32, tnaget, anyware_inst }, + {"tncaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007800, OPCODE_MASK_H32, tncaget, anyware_inst }, + {"taput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009800, OPCODE_MASK_H32, taput, anyware_inst }, + {"tcaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B800, OPCODE_MASK_H32, tcaput, anyware_inst }, + {"tnaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D800, OPCODE_MASK_H32, tnaput, anyware_inst }, + {"tncaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F800, OPCODE_MASK_H32, tncaput, anyware_inst }, + + {"eaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000C00, OPCODE_MASK_H32, eget, anyware_inst }, + {"ecaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002C00, OPCODE_MASK_H32, ecget, anyware_inst }, + {"neaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004C00, OPCODE_MASK_H32, neget, anyware_inst }, + {"necaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006C00, OPCODE_MASK_H32, necget, anyware_inst }, + {"eaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008C00, OPCODE_MASK_H32, eput, anyware_inst }, + {"ecaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00AC00, OPCODE_MASK_H32, ecput, anyware_inst }, + {"neaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00CC00, OPCODE_MASK_H32, neput, anyware_inst }, + {"necaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00EC00, OPCODE_MASK_H32, necput, anyware_inst }, + + {"teaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001C00, OPCODE_MASK_H32, teaget, anyware_inst }, + {"tecaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003C00, OPCODE_MASK_H32, tecaget, anyware_inst }, + {"tneaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005C00, OPCODE_MASK_H32, tneaget, anyware_inst }, + {"tnecaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007C00, OPCODE_MASK_H32, tnecaget, anyware_inst }, + {"teaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009C00, OPCODE_MASK_H32, teaput, anyware_inst }, + {"tecaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00BC00, OPCODE_MASK_H32, tecaput, anyware_inst }, + {"tneaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00DC00, OPCODE_MASK_H32, tneaput, anyware_inst }, + {"tnecaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00FC00, OPCODE_MASK_H32, tnecaput, anyware_inst }, + + {"getd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000000, OPCODE_MASK_H34C, getd, anyware_inst }, + {"tgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000080, OPCODE_MASK_H34C, tgetd, anyware_inst }, + {"cgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000100, OPCODE_MASK_H34C, cgetd, anyware_inst }, + {"tcgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000180, OPCODE_MASK_H34C, tcgetd, anyware_inst }, + {"ngetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000200, OPCODE_MASK_H34C, ngetd, anyware_inst }, + {"tngetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000280, OPCODE_MASK_H34C, tngetd, anyware_inst }, + {"ncgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000300, OPCODE_MASK_H34C, ncgetd, anyware_inst }, + {"tncgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000380, OPCODE_MASK_H34C, tncgetd, anyware_inst }, + {"putd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000400, OPCODE_MASK_H34C, putd, anyware_inst }, + {"tputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000480, OPCODE_MASK_H34C, tputd, anyware_inst }, + {"cputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000500, OPCODE_MASK_H34C, cputd, anyware_inst }, + {"tcputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000580, OPCODE_MASK_H34C, tcputd, anyware_inst }, + {"nputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000600, OPCODE_MASK_H34C, nputd, anyware_inst }, + {"tnputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000680, OPCODE_MASK_H34C, tnputd, anyware_inst }, + {"ncputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000700, OPCODE_MASK_H34C, ncputd, anyware_inst }, + {"tncputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000780, OPCODE_MASK_H34C, tncputd, anyware_inst }, + + {"egetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000020, OPCODE_MASK_H34C, egetd, anyware_inst }, + {"tegetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000A0, OPCODE_MASK_H34C, tegetd, anyware_inst }, + {"ecgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000120, OPCODE_MASK_H34C, ecgetd, anyware_inst }, + {"tecgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001A0, OPCODE_MASK_H34C, tecgetd, anyware_inst }, + {"negetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000220, OPCODE_MASK_H34C, negetd, anyware_inst }, + {"tnegetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002A0, OPCODE_MASK_H34C, tnegetd, anyware_inst }, + {"necgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000320, OPCODE_MASK_H34C, necgetd, anyware_inst }, + {"tnecgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003A0, OPCODE_MASK_H34C, tnecgetd, anyware_inst }, + {"eputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000420, OPCODE_MASK_H34C, eputd, anyware_inst }, + {"teputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004A0, OPCODE_MASK_H34C, teputd, anyware_inst }, + {"ecputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000520, OPCODE_MASK_H34C, ecputd, anyware_inst }, + {"tecputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005A0, OPCODE_MASK_H34C, tecputd, anyware_inst }, + {"neputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000620, OPCODE_MASK_H34C, neputd, anyware_inst }, + {"tneputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006A0, OPCODE_MASK_H34C, tneputd, anyware_inst }, + {"necputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000720, OPCODE_MASK_H34C, necputd, anyware_inst }, + {"tnecputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007A0, OPCODE_MASK_H34C, tnecputd, anyware_inst }, + + {"agetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000040, OPCODE_MASK_H34C, agetd, anyware_inst }, + {"tagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000C0, OPCODE_MASK_H34C, tagetd, anyware_inst }, + {"cagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000140, OPCODE_MASK_H34C, cagetd, anyware_inst }, + {"tcagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001C0, OPCODE_MASK_H34C, tcagetd, anyware_inst }, + {"nagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000240, OPCODE_MASK_H34C, nagetd, anyware_inst }, + {"tnagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002C0, OPCODE_MASK_H34C, tnagetd, anyware_inst }, + {"ncagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000340, OPCODE_MASK_H34C, ncagetd, anyware_inst }, + {"tncagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003C0, OPCODE_MASK_H34C, tncagetd, anyware_inst }, + {"aputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000440, OPCODE_MASK_H34C, aputd, anyware_inst }, + {"taputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004C0, OPCODE_MASK_H34C, taputd, anyware_inst }, + {"caputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000540, OPCODE_MASK_H34C, caputd, anyware_inst }, + {"tcaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005C0, OPCODE_MASK_H34C, tcaputd, anyware_inst }, + {"naputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000640, OPCODE_MASK_H34C, naputd, anyware_inst }, + {"tnaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006C0, OPCODE_MASK_H34C, tnaputd, anyware_inst }, + {"ncaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000740, OPCODE_MASK_H34C, ncaputd, anyware_inst }, + {"tncaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007C0, OPCODE_MASK_H34C, tncaputd, anyware_inst }, + + {"eagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000060, OPCODE_MASK_H34C, eagetd, anyware_inst }, + {"teagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000E0, OPCODE_MASK_H34C, teagetd, anyware_inst }, + {"ecagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000160, OPCODE_MASK_H34C, ecagetd, anyware_inst }, + {"tecagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001E0, OPCODE_MASK_H34C, tecagetd, anyware_inst }, + {"neagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000260, OPCODE_MASK_H34C, neagetd, anyware_inst }, + {"tneagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002E0, OPCODE_MASK_H34C, tneagetd, anyware_inst }, + {"necagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000360, OPCODE_MASK_H34C, necagetd, anyware_inst }, + {"tnecagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003E0, OPCODE_MASK_H34C, tnecagetd, anyware_inst }, + {"eaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000460, OPCODE_MASK_H34C, eaputd, anyware_inst }, + {"teaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004E0, OPCODE_MASK_H34C, teaputd, anyware_inst }, + {"ecaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000560, OPCODE_MASK_H34C, ecaputd, anyware_inst }, + {"tecaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005E0, OPCODE_MASK_H34C, tecaputd, anyware_inst }, + {"neaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000660, OPCODE_MASK_H34C, neaputd, anyware_inst }, + {"tneaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006E0, OPCODE_MASK_H34C, tneaputd, anyware_inst }, + {"necaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000760, OPCODE_MASK_H34C, necaputd, anyware_inst }, + {"tnecaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007E0, OPCODE_MASK_H34C, tnecaputd, anyware_inst }, + {"", 0, 0, 0, 0, 0, 0, 0, 0}, +}; + +/* Prefix for register names. */ +char register_prefix[] = "r"; +char special_register_prefix[] = "spr"; +char fsl_register_prefix[] = "rfsl"; +char pvr_register_prefix[] = "rpvr"; + + +/* #defines for valid immediate range. */ +#define MIN_IMM ((int) 0x80000000) +#define MAX_IMM ((int) 0x7fffffff) + +#define MIN_IMM15 ((int) 0x0000) +#define MAX_IMM15 ((int) 0x7fff) + +#endif /* MICROBLAZE_OPC */ + diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h new file mode 100644 index 0000000..10acacf --- /dev/null +++ b/opcodes/microblaze-opcm.h @@ -0,0 +1,139 @@ +/* microblaze-opcm.h -- Header used in microblaze-opc.h + + Copyright 2009 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + + +#ifndef MICROBLAZE_OPCM +#define MICROBLAZE_OPCM + +enum microblaze_instr +{ + add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, cmp, cmpu, + addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul, + mulh, mulhu, mulhsu, + idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput, + ncget, ncput, muli, bslli, bsrai, bsrli, mului, or, and, xor, + andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16, + wic, wdc, wdcclear, wdcflush, mts, mfs, br, brd, + brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt, + bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni, + imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid, + brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti, + bgtid, bgei, bgeid, lbu, lhu, lw, lwx, sb, sh, sw, swx, lbui, lhui, lwi, + sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv, + fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt, + fint, fsqrt, + tget, tcget, tnget, tncget, tput, tcput, tnput, tncput, + eget, ecget, neget, necget, eput, ecput, neput, necput, + teget, tecget, tneget, tnecget, teput, tecput, tneput, tnecput, + aget, caget, naget, ncaget, aput, caput, naput, ncaput, + taget, tcaget, tnaget, tncaget, taput, tcaput, tnaput, tncaput, + eaget, ecaget, neaget, necaget, eaput, ecaput, neaput, necaput, + teaget, tecaget, tneaget, tnecaget, teaput, tecaput, tneaput, tnecaput, + getd, tgetd, cgetd, tcgetd, ngetd, tngetd, ncgetd, tncgetd, + putd, tputd, cputd, tcputd, nputd, tnputd, ncputd, tncputd, + egetd, tegetd, ecgetd, tecgetd, negetd, tnegetd, necgetd, tnecgetd, + eputd, teputd, ecputd, tecputd, neputd, tneputd, necputd, tnecputd, + agetd, tagetd, cagetd, tcagetd, nagetd, tnagetd, ncagetd, tncagetd, + aputd, taputd, caputd, tcaputd, naputd, tnaputd, ncaputd, tncaputd, + eagetd, teagetd, ecagetd, tecagetd, neagetd, tneagetd, necagetd, tnecagetd, + eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd, + invalid_inst +}; + +enum microblaze_instr_type +{ + arithmetic_inst, logical_inst, mult_inst, div_inst, branch_inst, + return_inst, immediate_inst, special_inst, memory_load_inst, + memory_store_inst, barrel_shift_inst, anyware_inst +}; + +#define INST_WORD_SIZE 4 + +/* Gen purpose regs go from 0 to 31. */ +/* Mask is reg num - max_reg_num, ie reg_num - 32 in this case. */ + +#define REG_PC_MASK 0x8000 +#define REG_MSR_MASK 0x8001 +#define REG_EAR_MASK 0x8003 +#define REG_ESR_MASK 0x8005 +#define REG_FSR_MASK 0x8007 +#define REG_BTR_MASK 0x800b +#define REG_EDR_MASK 0x800d +#define REG_PVR_MASK 0xa000 + +#define REG_PID_MASK 0x9000 +#define REG_ZPR_MASK 0x9001 +#define REG_TLBX_MASK 0x9002 +#define REG_TLBLO_MASK 0x9003 +#define REG_TLBHI_MASK 0x9004 +#define REG_TLBSX_MASK 0x9005 + +#define MIN_REGNUM 0 +#define MAX_REGNUM 31 + +#define MIN_PVR_REGNUM 0 +#define MAX_PVR_REGNUM 15 + +#define REG_PC 32 /* PC. */ +#define REG_MSR 33 /* Machine status reg. */ +#define REG_EAR 35 /* Exception reg. */ +#define REG_ESR 37 /* Exception reg. */ +#define REG_FSR 39 /* FPU Status reg. */ +#define REG_BTR 43 /* Branch Target reg. */ +#define REG_EDR 45 /* Exception reg. */ +#define REG_PVR 40960 /* Program Verification reg. */ + +#define REG_PID 36864 /* MMU: Process ID reg. */ +#define REG_ZPR 36865 /* MMU: Zone Protect reg. */ +#define REG_TLBX 36866 /* MMU: TLB Index reg. */ +#define REG_TLBLO 36867 /* MMU: TLB Low reg. */ +#define REG_TLBHI 36868 /* MMU: TLB High reg. */ +#define REG_TLBSX 36869 /* MMU: TLB Search Index reg. */ + +/* Alternate names for gen purpose regs. */ +#define REG_SP 1 /* stack pointer. */ +#define REG_ROSDP 2 /* read-only small data pointer. */ +#define REG_RWSDP 13 /* read-write small data pointer. */ + +/* Assembler Register - Used in Delay Slot Optimization. */ +#define REG_AS 18 +#define REG_ZERO 0 + +#define RD_LOW 21 /* Low bit for RD. */ +#define RA_LOW 16 /* Low bit for RA. */ +#define RB_LOW 11 /* Low bit for RB. */ +#define IMM_LOW 0 /* Low bit for immediate. */ + +#define RD_MASK 0x03E00000 +#define RA_MASK 0x001F0000 +#define RB_MASK 0x0000F800 +#define IMM_MASK 0x0000FFFF + +/* Imm mask for barrel shifts. */ +#define IMM5_MASK 0x0000001F + +/* FSL imm mask for get, put instructions. */ +#define RFSL_MASK 0x000000F + +/* Imm mask for msrset, msrclr instructions. */ +#define IMM15_MASK 0x00007FFF + +#endif /* MICROBLAZE-OPCM */ |