diff options
| -rw-r--r-- | gas/ChangeLog | 7 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/advsimd-fp16.d | 12 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/advsimd-fp16.s | 3 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/aarch64-tbl.h | 8 |
5 files changed, 31 insertions, 4 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index e4db0f0..7292178 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,10 @@ +2016-09-29 Jiong Wang <jiong.wang@arm.com> + + PR target/20553 + * testsuite/gas/aarch64/advsimd-fp16.s (indexed_elem): New high index + testcases for H and S variants. New low index testcases for D variant. + * testsuite/gas/aarch64/advsimd-fp16.d: Update expected results. + 2016-09-29 Alan Modra <amodra@gmail.com> * config/tc-ppc.c (md_assemble): Handle PPC_OPERAND_OPTIONAL32. diff --git a/gas/testsuite/gas/aarch64/advsimd-fp16.d b/gas/testsuite/gas/aarch64/advsimd-fp16.d index b29c9da..d7ab5fe 100644 --- a/gas/testsuite/gas/aarch64/advsimd-fp16.d +++ b/gas/testsuite/gas/aarch64/advsimd-fp16.d @@ -435,6 +435,9 @@ Disassembly of section \.text: [0-9a-f]+: 0f031041 fmla v1.4h, v2.4h, v3.h\[0\] [0-9a-f]+: 4f001000 fmla v0.8h, v0.8h, v0.h\[0\] [0-9a-f]+: 4f031041 fmla v1.8h, v2.8h, v3.h\[0\] + [0-9a-f]+: 4fca10a1 fmla v1.2d, v5.2d, v10.d\[0\] + [0-9a-f]+: 0fab1808 fmla v8.2s, v0.2s, v11.s\[3\] + [0-9a-f]+: 0f3f1920 fmla v0.4h, v9.4h, v15.h\[7\] [0-9a-f]+: 4fc35841 fmls v1.2d, v2.2d, v3.d\[1\] [0-9a-f]+: 0f835841 fmls v1.2s, v2.2s, v3.s\[2\] [0-9a-f]+: 4fa35041 fmls v1.4s, v2.4s, v3.s\[1\] @@ -442,6 +445,9 @@ Disassembly of section \.text: [0-9a-f]+: 0f035041 fmls v1.4h, v2.4h, v3.h\[0\] [0-9a-f]+: 4f005000 fmls v0.8h, v0.8h, v0.h\[0\] [0-9a-f]+: 4f035041 fmls v1.8h, v2.8h, v3.h\[0\] + [0-9a-f]+: 4fca50a1 fmls v1.2d, v5.2d, v10.d\[0\] + [0-9a-f]+: 0fab5808 fmls v8.2s, v0.2s, v11.s\[3\] + [0-9a-f]+: 0f3f5920 fmls v0.4h, v9.4h, v15.h\[7\] [0-9a-f]+: 4fc39841 fmul v1.2d, v2.2d, v3.d\[1\] [0-9a-f]+: 0f839841 fmul v1.2s, v2.2s, v3.s\[2\] [0-9a-f]+: 4fa39041 fmul v1.4s, v2.4s, v3.s\[1\] @@ -449,6 +455,9 @@ Disassembly of section \.text: [0-9a-f]+: 0f039041 fmul v1.4h, v2.4h, v3.h\[0\] [0-9a-f]+: 4f009000 fmul v0.8h, v0.8h, v0.h\[0\] [0-9a-f]+: 4f039041 fmul v1.8h, v2.8h, v3.h\[0\] + [0-9a-f]+: 4fca90a1 fmul v1.2d, v5.2d, v10.d\[0\] + [0-9a-f]+: 0fab9808 fmul v8.2s, v0.2s, v11.s\[3\] + [0-9a-f]+: 0f3f9920 fmul v0.4h, v9.4h, v15.h\[7\] [0-9a-f]+: 6fc39841 fmulx v1.2d, v2.2d, v3.d\[1\] [0-9a-f]+: 2f839841 fmulx v1.2s, v2.2s, v3.s\[2\] [0-9a-f]+: 6fa39041 fmulx v1.4s, v2.4s, v3.s\[1\] @@ -456,6 +465,9 @@ Disassembly of section \.text: [0-9a-f]+: 2f039041 fmulx v1.4h, v2.4h, v3.h\[0\] [0-9a-f]+: 6f009000 fmulx v0.8h, v0.8h, v0.h\[0\] [0-9a-f]+: 6f039041 fmulx v1.8h, v2.8h, v3.h\[0\] + [0-9a-f]+: 6fca90a1 fmulx v1.2d, v5.2d, v10.d\[0\] + [0-9a-f]+: 2fab9808 fmulx v8.2s, v0.2s, v11.s\[3\] + [0-9a-f]+: 2f3f9920 fmulx v0.4h, v9.4h, v15.h\[7\] [0-9a-f]+: 5fc31841 fmla d1, d2, v3.d\[1\] [0-9a-f]+: 5fa31041 fmla s1, s2, v3.s\[1\] [0-9a-f]+: 5f131041 fmla h1, h2, v3.h\[1\] diff --git a/gas/testsuite/gas/aarch64/advsimd-fp16.s b/gas/testsuite/gas/aarch64/advsimd-fp16.s index 8be4854..6b86ded 100644 --- a/gas/testsuite/gas/aarch64/advsimd-fp16.s +++ b/gas/testsuite/gas/aarch64/advsimd-fp16.s @@ -165,6 +165,9 @@ \op v1.4h, v2.4h, v3.h[0] \op v0.8h, v0.8h, v0.h[0] \op v1.8h, v2.8h, v3.h[0] + \op v1.2d, v5.2d, v10.d[0] + \op v8.2s, v0.2s, v11.s[3] + \op v0.4h, v9.4h, v15.h[7] .endm indexed_elem fmla diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 98866ef..d58f5d8 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2016-09-29 Jiong Wang <jiong.wang@arm.com> + + PR target/20553 + * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field. + 2016-09-29 Alan Modra <amodra@gmail.com> * ppc-opc.c (L): Make compulsory. diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 096211e..81f86c6 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2067,11 +2067,11 @@ struct aarch64_opcode aarch64_opcode_table[] = SIMD_INSN ("sqdmulh", 0x0f00c000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), SIMD_INSN ("sqrdmulh",0x0f00d000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), SIMD_INSN ("fmla", 0x0f801000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ), - SF16_INSN ("fmla", 0x0f001000, 0xbfe0fc00, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ), + SF16_INSN ("fmla", 0x0f001000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ), SIMD_INSN ("fmls", 0x0f805000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ), - SF16_INSN ("fmls", 0x0f005000, 0xbfe0fc00, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ), + SF16_INSN ("fmls", 0x0f005000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ), SIMD_INSN ("fmul", 0x0f809000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ), - SF16_INSN ("fmul", 0x0f009000, 0xbfe0fc00, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ), + SF16_INSN ("fmul", 0x0f009000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ), SIMD_INSN ("mla", 0x2f000000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), SIMD_INSN ("umlal", 0x2f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), SIMD_INSN ("umlal2", 0x6f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), @@ -2081,7 +2081,7 @@ struct aarch64_opcode aarch64_opcode_table[] = SIMD_INSN ("umull", 0x2f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), SIMD_INSN ("umull2", 0x6f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), SIMD_INSN ("fmulx", 0x2f809000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ), - SF16_INSN ("fmulx", 0x2f009000, 0xbfe0fc00, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ), + SF16_INSN ("fmulx", 0x2f009000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ), RDMA_INSN ("sqrdmlah",0x2f00d000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), RDMA_INSN ("sqrdmlsh",0x2f00f000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), /* AdvSIMD EXT. */ |