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-rw-r--r--bfd/ChangeLog6
-rw-r--r--bfd/elf32-arm.c75
-rw-r--r--gas/ChangeLog12
-rw-r--r--gas/testsuite/gas/arm/armv8_1-m-bf-rel.d4
-rw-r--r--gas/testsuite/gas/arm/armv8_1-m-bf-rela.d12
-rw-r--r--gas/testsuite/gas/arm/armv8_1-m-bf.d4
-rw-r--r--gas/testsuite/gas/arm/armv8_1-m-bfcsel.d4
-rw-r--r--gas/testsuite/gas/arm/armv8_1-m-bfl-rel.d4
-rw-r--r--gas/testsuite/gas/arm/armv8_1-m-bfl-rela.d12
-rw-r--r--gas/testsuite/gas/arm/armv8_1-m-bfl.d4
-rw-r--r--gas/testsuite/gas/arm/armv8_1-m-loloop.d10
-rw-r--r--ld/ChangeLog7
-rw-r--r--ld/testsuite/ld-arm/arm-elf.exp9
-rw-r--r--ld/testsuite/ld-arm/bfs-0.s12
-rw-r--r--ld/testsuite/ld-arm/bfs-1.s9
-rw-r--r--ld/testsuite/ld-arm/branch-futures.d17
16 files changed, 117 insertions, 84 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 2e7158f..81885bd 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,9 @@
+2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ PR 24460
+ * elf32-arm.c (get_value_helper): Remove.
+ (elf32_arm_final_link_relocate): Fix branch future relocations.
+
2019-05-21 Tamar Christina <tamar.christina@arm.com>
PR ld/24373
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index 418458c..7f08526 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -10293,59 +10293,6 @@ identify_add_or_sub (bfd_vma insn)
return 0;
}
-/* Helper function to compute the Addend for Armv8.1-M Mainline relocations. */
-static bfd_vma
-get_value_helper (bfd_vma plt_offset,
- asection *splt,
- asection *input_section,
- asection *sym_sec,
- struct elf_link_hash_entry * h,
- struct bfd_link_info *info,
- bfd *input_bfd,
- Elf_Internal_Rela *rel,
- const char *sym_name,
- unsigned char st_type,
- struct elf32_arm_link_hash_table *globals,
- bfd_boolean *unresolved_reloc_p)
-{
- bfd_vma value = 0;
- enum arm_st_branch_type branch_type;
- enum elf32_arm_stub_type stub_type = arm_stub_none;
- struct elf32_arm_stub_hash_entry *stub_entry;
- struct elf32_arm_link_hash_entry *hash
- = (struct elf32_arm_link_hash_entry *)h;
-
-
- if (plt_offset != (bfd_vma) -1)
- {
- value = (splt->output_section->vma
- + splt->output_offset
- + plt_offset);
- value -= PLT_THUMB_STUB_SIZE;
- *unresolved_reloc_p = FALSE;
- }
-
- stub_type = arm_type_of_stub (info, input_section, rel,
- st_type, &branch_type,
- hash, value, sym_sec,
- input_bfd, sym_name);
-
- if (stub_type != arm_stub_none)
- {
- stub_entry = elf32_arm_get_stub_entry (input_section,
- sym_sec, h,
- rel, globals,
- stub_type);
- if (stub_entry != NULL)
- {
- value = (stub_entry->stub_offset
- + stub_entry->stub_sec->output_offset
- + stub_entry->stub_sec->output_section->vma);
- }
- }
- return value;
-}
-
/* Perform a relocation as part of a final link. */
static bfd_reloc_status_type
@@ -12968,14 +12915,10 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
addend |= (immC << 1);
addend |= 1;
/* Sign extend. */
- addend = (addend & 0x10000) ? addend - (1 << 17) : addend;
+ signed_addend = (addend & 0x10000) ? addend - (1 << 17) : addend;
}
- value = get_value_helper (plt_offset, splt, input_section, sym_sec, h,
- info, input_bfd, rel, sym_name, st_type,
- globals, unresolved_reloc_p);
-
- relocation = value + addend;
+ relocation = value + signed_addend;
relocation -= (input_section->output_section->vma
+ input_section->output_offset
+ rel->r_offset);
@@ -13014,13 +12957,10 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
addend |= 1;
/* Sign extend. */
addend = (addend & 0x1000) ? addend - (1 << 13) : addend;
+ signed_addend = addend;
}
- value = get_value_helper (plt_offset, splt, input_section, sym_sec, h,
- info, input_bfd, rel, sym_name, st_type,
- globals, unresolved_reloc_p);
-
- relocation = value + addend;
+ relocation = value + signed_addend;
relocation -= (input_section->output_section->vma
+ input_section->output_offset
+ rel->r_offset);
@@ -13059,13 +12999,10 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
addend |= 1;
/* Sign extend. */
addend = (addend & 0x40000) ? addend - (1 << 19) : addend;
+ signed_addend = addend;
}
- value = get_value_helper (plt_offset, splt, input_section, sym_sec, h,
- info, input_bfd, rel, sym_name, st_type,
- globals, unresolved_reloc_p);
-
- relocation = value + addend;
+ relocation = value + signed_addend;
relocation -= (input_section->output_section->vma
+ input_section->output_offset
+ rel->r_offset);
diff --git a/gas/ChangeLog b/gas/ChangeLog
index fbfa00b..90fc3c3 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,15 @@
+2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * testsuite/gas/arm/armv8_1-m-bf.d: Allow different branch target naming
+ conventions.
+ * testsuite/gas/arm/armv8_1-m-bfl.d: Likewise.
+ * testsuite/gas/arm/armv8_1-m-bfcsel.d: Likewise.
+ * testsuite/gas/arm/armv8_1-m-loloop.d: Likewise.
+ * testsuite/gas/arm/armv8_1-m-bf-rel.d: Skip for vxworks.
+ * testsuite/gas/arm/armv8_1-m-bf-rela.d: New test.
+ * testsuite/gas/arm/armv8_1-m-bfl-rel.d: Skip for vxworks.
+ * testsuite/gas/arm/armv8_1-m-bfl-rela.d: New test.
+
2019-05-21 John Darrington <john@darrington.wattle.id.au>
* expr.c (literal_prefix_dollar_hex): New variable.
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-rel.d b/gas/testsuite/gas/arm/armv8_1-m-bf-rel.d
index e429c13..bdb265c 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-bf-rel.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf-rel.d
@@ -1,7 +1,7 @@
-#name: Valid Armv8.1-M Mainline BF instruction with relocation
+#name: Valid Armv8.1-M Mainline BF instruction with REL
#as: -march=armv8.1-m.main
#objdump: -dr --prefix-addresses --show-raw-insn
-#skip: *-*-pe *-wince-*
+#skip: *-*-pe *-wince-* *-vxworks
.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-rela.d b/gas/testsuite/gas/arm/armv8_1-m-bf-rela.d
new file mode 100644
index 0000000..d363d09
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf-rela.d
@@ -0,0 +1,12 @@
+#name: Valid Armv8.1-M Mainline BF instruction with RELA
+#as: -march=armv8.1-m.main
+#objdump: -dr --prefix-addresses --show-raw-insn
+#source:armv8_1-m-bf-rel.s
+#noskip: *-vxworks
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f0c0 e001 bf 2, 00000004 <.target\+0x4>
+ 0: R_ARM_THM_BF16 .target-0x4
+
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf.d b/gas/testsuite/gas/arm/armv8_1-m-bf.d
index dd30b2a..99de065 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-bf.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf.d
@@ -5,9 +5,9 @@
.*: +file format .*arm.*
Disassembly of section .text:
-0[0-9a-f]+ <[^>]+> f0c0 e803 bf 2, 0000000a <foo\+0xa>
+0[0-9a-f]+ <[^>]+> f0c0 e803 bf 2, 0000000a <.*>
0[0-9a-f]+ <[^>]+> 4609 mov r1, r1
-0[0-9a-f]+ <[^>]+> f140 e801 bf 4, 0000000c <foo\+0xc>
+0[0-9a-f]+ <[^>]+> f140 e801 bf 4, 0000000c <.*>
0[0-9a-f]+ <[^>]+> 460a mov r2, r1
0[0-9a-f]+ <[^>]+> 4613 mov r3, r2
0[0-9a-f]+ <[^>]+> 4614 mov r4, r2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfcsel.d b/gas/testsuite/gas/arm/armv8_1-m-bfcsel.d
index a498f06..b66e929 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-bfcsel.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfcsel.d
@@ -5,8 +5,8 @@
.*: +file format .*arm.*
Disassembly of section .text:
-0[0-9a-f]+ <[^>]+> f080 e803 bfcsel 2, 0000000a <foo\+0xa>, 4, eq
+0[0-9a-f]+ <[^>]+> f080 e803 bfcsel 2, 0000000a <.*>, 4, eq
0[0-9a-f]+ <[^>]+> 4609 mov r1, r1
-0[0-9a-f]+ <[^>]+> d000 beq.n 0000000a <foo\+0xa>
+0[0-9a-f]+ <[^>]+> d000 beq.n 0000000a <.*>
0[0-9a-f]+ <[^>]+> 4613 mov r3, r2
0[0-9a-f]+ <[^>]+> 4614 mov r4, r2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfl-rel.d b/gas/testsuite/gas/arm/armv8_1-m-bfl-rel.d
index 13c6bf1..951074c 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-bfl-rel.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfl-rel.d
@@ -1,7 +1,7 @@
-#name: Valid Armv8.1-M Mainline BFL instruction with relocation
+#name: Valid Armv8.1-M Mainline BFL instruction with REL
#as: -march=armv8.1-m.main
#objdump: -dr --prefix-addresses --show-raw-insn
-#skip: *-*-pe *-wince-*
+#skip: *-*-pe *-wince-* *-vxworks
.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfl-rela.d b/gas/testsuite/gas/arm/armv8_1-m-bfl-rela.d
new file mode 100644
index 0000000..291d10b
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfl-rela.d
@@ -0,0 +1,12 @@
+#name: Valid Armv8.1-M Mainline BFL instruction with RELA
+#as: -march=armv8.1-m.main
+#objdump: -dr --prefix-addresses --show-raw-insn
+#source: armv8_1-m-bfl-rel.s
+#noskip: *-vxworks
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f080 c001 bfl 2, 00000004 <.target\+0x4>
+ 0: R_ARM_THM_BF18 .target-0x4
+
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfl.d b/gas/testsuite/gas/arm/armv8_1-m-bfl.d
index e15636b..b28d0b1 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-bfl.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfl.d
@@ -5,9 +5,9 @@
.*: +file format .*arm.*
Disassembly of section .text:
-0[0-9a-f]+ <[^>]+> f080 c803 bfl 2, 0000000a <foo\+0xa>
+0[0-9a-f]+ <[^>]+> f080 c803 bfl 2, 0000000a <.*>
0[0-9a-f]+ <[^>]+> 4608 mov r0, r1
-0[0-9a-f]+ <[^>]+> f100 c801 bfl 4, 0000000c <foo\+0xc>
+0[0-9a-f]+ <[^>]+> f100 c801 bfl 4, 0000000c <.*>
0[0-9a-f]+ <[^>]+> 460a mov r2, r1
0[0-9a-f]+ <[^>]+> 4613 mov r3, r2
0[0-9a-f]+ <[^>]+> 4614 mov r4, r2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-loloop.d b/gas/testsuite/gas/arm/armv8_1-m-loloop.d
index 1e02b82..20506c6 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-loloop.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-loloop.d
@@ -6,12 +6,12 @@
.*: +file format .*arm.*
Disassembly of section .text:
-0[0-9a-f]+ <[^>]+> f042 c00d wls lr, r2, 0000001c <foo\+0x1c>
+0[0-9a-f]+ <[^>]+> f042 c00d wls lr, r2, 0000001c <.*>
0[0-9a-f]+ <[^>]+> f042 e001 dls lr, r2
0[0-9a-f]+ <[^>]+> f04e e001 dls lr, lr
-0[0-9a-f]+ <[^>]+> f00f c009 le lr, 00000000 <foo>
-0[0-9a-f]+ <[^>]+> f02f c00b le 00000000 <foo>
-0[0-9a-f]+ <[^>]+> f00f c24b le lr, fffffb84 <foo\+0xfffffb84>
-0[0-9a-f]+ <[^>]+> f02f c007 le 00000010 <foo\+0x10>
+0[0-9a-f]+ <[^>]+> f00f c009 le lr, 00000000 <.*>
+0[0-9a-f]+ <[^>]+> f02f c00b le 00000000 <.*>
+0[0-9a-f]+ <[^>]+> f00f c24b le lr, fffffb84 <.*>
+0[0-9a-f]+ <[^>]+> f02f c007 le 00000010 <.*>
0[0-9a-f]+ <[^>]+> 4613 mov r3, r2
#...
diff --git a/ld/ChangeLog b/ld/ChangeLog
index 77beea0..05af393 100644
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,10 @@
+2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * testsuite/ld-arm/arm-elf.exp: Add tests
+ * testsuite/ld-arm/bfs-0.s: New test.
+ * testsuite/ld-arm/bfs-1.s: New test.
+ * testsuite/ld-arm/branch-futures.d: New test.
+
2019-05-21 Tamar Christina <tamar.christina@arm.com>
PR ld/24373
diff --git a/ld/testsuite/ld-arm/arm-elf.exp b/ld/testsuite/ld-arm/arm-elf.exp
index 5471895..7d3217f 100644
--- a/ld/testsuite/ld-arm/arm-elf.exp
+++ b/ld/testsuite/ld-arm/arm-elf.exp
@@ -42,6 +42,11 @@ if {[istarget "arm-*-vxworks"]} {
"" {vxworks2.s}
{{readelf --segments vxworks2-static.sd}}
"vxworks2"}
+ {"Branch future relocations for armv8.1-m.main target"
+ "-static -T arm.ld"
+ "" "" {bfs-0.s bfs-1.s}
+ {{objdump -dw branch-futures.d}}
+ "branch-futures"}
}
run_ld_link_tests $armvxworkstests
run_dump_test "vxworks1-static"
@@ -260,6 +265,10 @@ set armelftests_common_3 {
{"ADDS thumb1 relocations for armv7-m target" "-static -T arm.ld" "" "" {thumb1-adds-armv7-m.s}
{{objdump -dw thumb1-adds.d}}
"thumb1-adds"}
+ {"Branch future relocations for armv8.1-m.main target" "-static -T arm.ld"
+ "" "" {bfs-0.s bfs-1.s}
+ {{objdump -dw branch-futures.d}}
+ "branch-futures"}
}
run_ld_link_tests $armelftests_common_1
diff --git a/ld/testsuite/ld-arm/bfs-0.s b/ld/testsuite/ld-arm/bfs-0.s
new file mode 100644
index 0000000..844417a
--- /dev/null
+++ b/ld/testsuite/ld-arm/bfs-0.s
@@ -0,0 +1,12 @@
+.arch armv8.1-m.main
+.text
+.syntax unified
+.thumb
+future:
+ bf branch, target
+ bfcsel branch, target, else, eq
+ bfl branch, target
+ add r0, r0, r1
+branch:
+ b target
+else:
diff --git a/ld/testsuite/ld-arm/bfs-1.s b/ld/testsuite/ld-arm/bfs-1.s
new file mode 100644
index 0000000..2b72819
--- /dev/null
+++ b/ld/testsuite/ld-arm/bfs-1.s
@@ -0,0 +1,9 @@
+.arch armv8.1-m.main
+.text
+.syntax unified
+.thumb
+.global _start
+.global target
+_start:
+target:
+ add r0, r0, r1
diff --git a/ld/testsuite/ld-arm/branch-futures.d b/ld/testsuite/ld-arm/branch-futures.d
new file mode 100644
index 0000000..427ecce
--- /dev/null
+++ b/ld/testsuite/ld-arm/branch-futures.d
@@ -0,0 +1,17 @@
+
+.*: file format elf32-.*
+
+
+Disassembly of section .text:
+
+0[0-9a-f]+ <future>:
+ [0-9a-f]+: f2c0 e807 bf a, 8012 <_start>
+ [0-9a-f]+: f182 e805 bfcsel 6, 8012 <_start>, a, eq
+ [0-9a-f]+: f080 c803 bfl 2, 8012 <_start>
+ [0-9a-f]+: 4408 add r0, r1
+
+0[0-9a-f]+ <branch>:
+ [0-9a-f]+: f000 b800 b.w 8012 <_start>
+
+0[0-9a-f]+ <_start>:
+ [0-9a-f]+: 4408 add r0, r1
generated by cgit v1.1 at 2024-11-25 11:44:53 +0000