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-rw-r--r--gas/ChangeLog13
-rw-r--r--gas/config/tc-i386.c12
-rw-r--r--gas/testsuite/gas/i386/invlpgb.d4
-rw-r--r--gas/testsuite/gas/i386/invlpgb.s22
-rw-r--r--gas/testsuite/gas/i386/invlpgb64.d5
-rw-r--r--gas/testsuite/gas/i386/snp.d7
-rw-r--r--gas/testsuite/gas/i386/snp.s44
-rw-r--r--gas/testsuite/gas/i386/snp64.d18
-rw-r--r--opcodes/ChangeLog7
-rw-r--r--opcodes/i386-opc.tbl10
-rw-r--r--opcodes/i386-tbl.h53
11 files changed, 163 insertions, 32 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index e36eca9..0c99e51 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,18 @@
2021-03-25 Jan Beulich <jbeulich@suse.com>
+ * config/tc-i386.c (md_assemble): Widen set of insns to avoid
+ swapping operands for.
+ * testsuite/gas/i386/invlpgb.s: Fix, re-arrange, and add Intel
+ syntax tests.
+ * testsuite/gas/i386/snp.s: Re-arrange and add multi-operand as
+ well as Intel syntax tests.
+ * testsuite/gas/i386/invlpgb.d, testsuite/gas/i386/snp.d: Adjust
+ expectations.
+ * testsuite/gas/i386/invlpgb64.d, testsuite/gas/i386/snp64.d:
+ Likewise. Drop passing --def-sym to as.
+
+2021-03-25 Jan Beulich <jbeulich@suse.com>
+
PR/gas 27419
* config/tc-i386.c (process_suffix): Restrict (%rip) -> (%eip)
conversion to x32 mode.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index c2c5b69..785d0c4 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -4679,16 +4679,18 @@ md_assemble (char *line)
operands at hand. */
/* All Intel opcodes have reversed operands except for "bound", "enter",
- "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse
- intersegment "jmp" and "call" instructions with 2 immediate operands so
- that the immediate segment precedes the offset, as it does when in AT&T
- mode. */
+ "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate",
+ "rmpadjust", and "rmpupdate". We also don't reverse intersegment "jmp"
+ and "call" instructions with 2 immediate operands so that the immediate
+ segment precedes the offset consistently in Intel and AT&T modes. */
if (intel_syntax
&& i.operands > 1
&& (strcmp (mnemonic, "bound") != 0)
- && (strcmp (mnemonic, "invlpga") != 0)
+ && (strncmp (mnemonic, "invlpg", 6) != 0)
&& (strncmp (mnemonic, "monitor", 7) != 0)
&& (strncmp (mnemonic, "mwait", 5) != 0)
+ && (strcmp (mnemonic, "pvalidate") != 0)
+ && (strncmp (mnemonic, "rmp", 3) != 0)
&& (strcmp (mnemonic, "tpause") != 0)
&& (strcmp (mnemonic, "umwait") != 0)
&& !(operand_type_check (i.types[0], imm)
diff --git a/gas/testsuite/gas/i386/invlpgb.d b/gas/testsuite/gas/i386/invlpgb.d
index 34e62d1..e645364 100644
--- a/gas/testsuite/gas/i386/invlpgb.d
+++ b/gas/testsuite/gas/i386/invlpgb.d
@@ -11,4 +11,8 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]+0f 01 fe[ ]+invlpgb[ ]*
[0-9a-f]+ <att16>:
[ ]*[a-f0-9]+:[ ]+67 0f 01 fe[ ]+addr16 invlpgb[ ]*
+[0-9a-f]+ <intel32>:
+[ ]*[a-f0-9]+:[ ]+0f 01 fe[ ]+invlpgb[ ]*
+[0-9a-f]+ <intel16>:
+[ ]*[a-f0-9]+:[ ]+67 0f 01 fe[ ]+addr16 invlpgb[ ]*
#pass
diff --git a/gas/testsuite/gas/i386/invlpgb.s b/gas/testsuite/gas/i386/invlpgb.s
index 52b75b7..cc85e73 100644
--- a/gas/testsuite/gas/i386/invlpgb.s
+++ b/gas/testsuite/gas/i386/invlpgb.s
@@ -3,13 +3,25 @@
.text
_start:
invlpgb
-.ifdef __amd64__
+.ifdef x86_64
att64:
- invlpgb %rax, %edx
+ invlpgb %rax, %ecx, %edx
.endif
att32:
- invlpgb %eax, %edx
-.ifndef __amd64__
+ invlpgb %eax, %ecx, %edx
+.ifndef x86_64
att16:
- invlpgb %ax, %edx
+ invlpgb %ax, %ecx, %edx
+.endif
+
+ .intel_syntax noprefix
+.ifdef x86_64
+intel64:
+ invlpgb rax, ecx, edx
+.endif
+intel32:
+ invlpgb eax, ecx, edx
+.ifndef x86_64
+intel16:
+ invlpgb ax, ecx, edx
.endif
diff --git a/gas/testsuite/gas/i386/invlpgb64.d b/gas/testsuite/gas/i386/invlpgb64.d
index 025bdff..2582481 100644
--- a/gas/testsuite/gas/i386/invlpgb64.d
+++ b/gas/testsuite/gas/i386/invlpgb64.d
@@ -1,4 +1,3 @@
-#as: --defsym __amd64__=1
#objdump: -dw
#name: 64-bit INVLPGB insn
#source: invlpgb.s
@@ -13,4 +12,8 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]+0f 01 fe[ ]+invlpgb[ ]*
[0-9a-f]+ <att32>:
[ ]*[a-f0-9]+:[ ]+67 0f 01 fe[ ]+addr32 invlpgb[ ]*
+[0-9a-f]+ <intel64>:
+[ ]*[a-f0-9]+:[ ]+0f 01 fe[ ]+invlpgb[ ]*
+[0-9a-f]+ <intel32>:
+[ ]*[a-f0-9]+:[ ]+67 0f 01 fe[ ]+addr32 invlpgb[ ]*
#pass
diff --git a/gas/testsuite/gas/i386/snp.d b/gas/testsuite/gas/i386/snp.d
index 0bf0d02..81d386c 100644
--- a/gas/testsuite/gas/i386/snp.d
+++ b/gas/testsuite/gas/i386/snp.d
@@ -6,7 +6,12 @@
Disassembly of section \.text:
-00000000 <att32>:
+0+ <att>:
+[ ]*[a-f0-9]+:[ ]+f2 0f 01 ff[ ]+pvalidate[ ]*
+[ ]*[a-f0-9]+:[ ]+f2 0f 01 ff[ ]+pvalidate[ ]*
+[ ]*[a-f0-9]+:[ ]+67 f2 0f 01 ff[ ]+addr16 pvalidate[ ]*
+
+[0-9a-f]+ <intel>:
[ ]*[a-f0-9]+:[ ]+f2 0f 01 ff[ ]+pvalidate[ ]*
[ ]*[a-f0-9]+:[ ]+f2 0f 01 ff[ ]+pvalidate[ ]*
[ ]*[a-f0-9]+:[ ]+67 f2 0f 01 ff[ ]+addr16 pvalidate[ ]*
diff --git a/gas/testsuite/gas/i386/snp.s b/gas/testsuite/gas/i386/snp.s
index 197d053..0ac0dfc 100644
--- a/gas/testsuite/gas/i386/snp.s
+++ b/gas/testsuite/gas/i386/snp.s
@@ -1,23 +1,39 @@
# Check SNP instructions
.text
-.ifdef __amd64__
-att64:
- psmash %rax
+att:
+ pvalidate
+ pvalidate %eax, %ecx, %edx
+.ifdef x86_64
+ pvalidate %rax, %ecx, %edx
psmash
- psmash %eax
- pvalidate %rax
- pvalidate %eax
- rmpupdate %rax
+ psmash %rax
+ psmash %eax
rmpupdate
- rmpupdate %eax
- rmpadjust %rax
+ rmpupdate %rax, %rcx
+ rmpupdate %eax, %rcx
rmpadjust
- rmpadjust %eax
+ rmpadjust %rax, %rcx, %rdx
+ rmpadjust %eax, %rcx, %rdx
+.else
+ pvalidate %ax, %ecx, %edx
.endif
-.ifndef __amd64__
-att32:
+
+ .intel_syntax noprefix
+intel:
pvalidate
- pvalidate %eax
- pvalidate %ax
+ pvalidate eax, ecx, edx
+.ifdef x86_64
+ pvalidate rax, ecx, edx
+ psmash
+ psmash rax
+ psmash eax
+ rmpupdate
+ rmpupdate rax, rcx
+ rmpupdate eax, rcx
+ rmpadjust
+ rmpadjust rax, rcx, rdx
+ rmpadjust eax, rcx, rdx
+.else
+ pvalidate ax, ecx, edx
.endif
diff --git a/gas/testsuite/gas/i386/snp64.d b/gas/testsuite/gas/i386/snp64.d
index 1f78367..2b3e9ee 100644
--- a/gas/testsuite/gas/i386/snp64.d
+++ b/gas/testsuite/gas/i386/snp64.d
@@ -1,4 +1,3 @@
-#as: --defsym __amd64__=1
#objdump: -dw
#name: 64-bit SNP insn
#source: snp.s
@@ -8,12 +7,27 @@
Disassembly of section \.text:
-0+000 <att64>:
+0+ <att>:
+[ ]*[a-f0-9]+:[ ]+f2 0f 01 ff[ ]+pvalidate[ ]*
+[ ]*[a-f0-9]+:[ ]+67 f2 0f 01 ff[ ]+addr32 pvalidate[ ]*
+[ ]*[a-f0-9]+:[ ]+f2 0f 01 ff[ ]+pvalidate[ ]*
[ ]*[a-f0-9]+:[ ]+f3 0f 01 ff[ ]+psmash[ ]*
[ ]*[a-f0-9]+:[ ]+f3 0f 01 ff[ ]+psmash[ ]*
[ ]*[a-f0-9]+:[ ]+67 f3 0f 01 ff[ ]+addr32 psmash[ ]*
+[ ]*[a-f0-9]+:[ ]+f2 0f 01 fe[ ]+rmpupdate[ ]*
+[ ]*[a-f0-9]+:[ ]+f2 0f 01 fe[ ]+rmpupdate[ ]*
+[ ]*[a-f0-9]+:[ ]+67 f2 0f 01 fe[ ]+addr32 rmpupdate[ ]*
+[ ]*[a-f0-9]+:[ ]+f3 0f 01 fe[ ]+rmpadjust[ ]*
+[ ]*[a-f0-9]+:[ ]+f3 0f 01 fe[ ]+rmpadjust[ ]*
+[ ]*[a-f0-9]+:[ ]+67 f3 0f 01 fe[ ]+addr32 rmpadjust[ ]*
+
+[0-9a-f]+ <intel>:
[ ]*[a-f0-9]+:[ ]+f2 0f 01 ff[ ]+pvalidate[ ]*
[ ]*[a-f0-9]+:[ ]+67 f2 0f 01 ff[ ]+addr32 pvalidate[ ]*
+[ ]*[a-f0-9]+:[ ]+f2 0f 01 ff[ ]+pvalidate[ ]*
+[ ]*[a-f0-9]+:[ ]+f3 0f 01 ff[ ]+psmash[ ]*
+[ ]*[a-f0-9]+:[ ]+f3 0f 01 ff[ ]+psmash[ ]*
+[ ]*[a-f0-9]+:[ ]+67 f3 0f 01 ff[ ]+addr32 psmash[ ]*
[ ]*[a-f0-9]+:[ ]+f2 0f 01 fe[ ]+rmpupdate[ ]*
[ ]*[a-f0-9]+:[ ]+f2 0f 01 fe[ ]+rmpupdate[ ]*
[ ]*[a-f0-9]+:[ ]+67 f2 0f 01 fe[ ]+addr32 rmpupdate[ ]*
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 0748beb..bd02d2b 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2021-03-25 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (invlpgb): Fix multi-operand form.
+ (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
+ single-operand forms as deprecated.
+ * i386-tbl.h: Re-generate.
+
2021-03-25 Alan Modra <amodra@gmail.com>
PR 27647
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 3f40f10..721e94e 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3979,7 +3979,7 @@ vpclmulhqhqdq, 0x6644, 0x11, CpuVPCLMULQDQ|CpuAVX512F, Modrm|Space0F3A|VexWIG|Ve
// INVLPGB instructions
invlpgb, 0xf01fe, None, CpuINVLPGB, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
-invlpgb, 0xf01fe, None, CpuINVLPGB, AddrPrefixOpReg, { Acc|Word|Dword|Qword, RegD|Dword }
+invlpgb, 0xf01fe, None, CpuINVLPGB, AddrPrefixOpReg, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword }
// INVLPGB instructions end
@@ -4126,10 +4126,14 @@ mcommit, 0x0f01fa, None, CpuMCOMMIT, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf
psmash, 0xf01ff, None, CpuSNP|Cpu64, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
psmash, 0xf01ff, None, CpuSNP|Cpu64, AddrPrefixOpReg|Prefix_0XF3, { Acc|Dword|Qword }
pvalidate, 0xf01ff, None, CpuSNP, Prefix_0XF2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
-pvalidate, 0xf01ff, None, CpuSNP, AddrPrefixOpReg|Prefix_0XF2, { Acc|Word|Dword|Qword }
+pvalidate, 0xf01ff, None, CpuSNP, AddrPrefixOpReg|Prefix_0XF2, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword }
rmpupdate, 0xf01fe, None, CpuSNP|Cpu64, Prefix_0XF2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
-rmpupdate, 0xf01fe, None, CpuSNP|Cpu64, AddrPrefixOpReg|Prefix_0XF2, { Acc|Dword|Qword }
+rmpupdate, 0xf01fe, None, CpuSNP|Cpu64, AddrPrefixOpReg|Prefix_0XF2, { Acc|Dword|Qword, RegC|Qword }
rmpadjust, 0xf01fe, None, CpuSNP|Cpu64, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
+rmpadjust, 0xf01fe, None, CpuSNP|Cpu64, AddrPrefixOpReg|Prefix_0XF3, { Acc|Dword|Qword, RegC|Qword, RegD|Qword }
+// The single-operand forms exist only for compatibility with older gas.
+pvalidate, 0xf01ff, None, CpuSNP, AddrPrefixOpReg|Prefix_0XF2, { Acc|Word|Dword|Qword }
+rmpupdate, 0xf01fe, None, CpuSNP|Cpu64, AddrPrefixOpReg|Prefix_0XF2, { Acc|Dword|Qword }
rmpadjust, 0xf01fe, None, CpuSNP|Cpu64, AddrPrefixOpReg|Prefix_0XF3, { Acc|Dword|Qword }
// SNP instructions end
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 8228cef..337bf18 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -62769,7 +62769,7 @@ const insn_template i386_optab[] =
1, 0, 0, 0, 0, 0 } },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0 } } } },
- { "invlpgb", 0x0f01fe, None, 2,
+ { "invlpgb", 0x0f01fe, None, 3,
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
@@ -62782,6 +62782,8 @@ const insn_template i386_optab[] =
1, 0, 0, 0, 0, 0 } },
{ { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1,
0, 0, 0, 0, 0, 0, 0 } },
+ { { 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
0, 0, 0, 0, 0, 0, 0 } } } },
{ "tlbsync", 0x0f01ff, None, 0,
@@ -63548,6 +63550,23 @@ const insn_template i386_optab[] =
0, 0, 1, 0, 0, 0 } },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0 } } } },
+ { "pvalidate", 0x0f01ff, None, 3,
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 1, 0, 0, 0 } },
+ { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1,
+ 0, 0, 0, 0, 0, 0, 0 } },
+ { { 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0 } },
+ { { 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0 } } } },
{ "pvalidate", 0x0f01ff, None, 1,
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0,
@@ -63574,6 +63593,21 @@ const insn_template i386_optab[] =
0, 0, 1, 1, 0, 0 } },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0 } } } },
+ { "rmpupdate", 0x0f01fe, None, 2,
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 1, 1, 0, 0 } },
+ { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
+ 0, 0, 0, 0, 0, 0, 0 } },
+ { { 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
+ 0, 0, 0, 0, 0, 0, 0 } } } },
{ "rmpupdate", 0x0f01fe, None, 1,
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0,
@@ -63600,6 +63634,23 @@ const insn_template i386_optab[] =
0, 0, 1, 1, 0, 0 } },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0 } } } },
+ { "rmpadjust", 0x0f01fe, None, 3,
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 1, 1, 0, 0 } },
+ { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
+ 0, 0, 0, 0, 0, 0, 0 } },
+ { { 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
+ 0, 0, 0, 0, 0, 0, 0 } },
+ { { 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
+ 0, 0, 0, 0, 0, 0, 0 } } } },
{ "rmpadjust", 0x0f01fe, None, 1,
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0,
generated by cgit v1.1 at 2025-02-01 20:06:13 +0000