diff options
| -rw-r--r-- | include/elf/ChangeLog | 4 | ||||
| -rw-r--r-- | include/elf/sparc.h | 2 | ||||
| -rw-r--r-- | include/opcode/ChangeLog | 4 | ||||
| -rw-r--r-- | include/opcode/sparc.h | 2 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 1 | ||||
| -rw-r--r-- | opcodes/sparc-opc.c | 24 |
6 files changed, 23 insertions, 14 deletions
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog index 17978ba..001a940 100644 --- a/include/elf/ChangeLog +++ b/include/elf/ChangeLog @@ -1,3 +1,7 @@ +2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com> + + * sparc.h (ELF_SPARC_HWCAP2_VIS3B): Documentation improved. + 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com> * sparc.h (Tag_GNU_Sparc_HWCAPS2): New object attribute. diff --git a/include/elf/sparc.h b/include/elf/sparc.h index d41ba35..fd17a24f 100644 --- a/include/elf/sparc.h +++ b/include/elf/sparc.h @@ -237,7 +237,7 @@ enum #define ELF_SPARC_HWCAP_CRC32C 0x20000000 /* CRC32C insn */ #define ELF_SPARC_HWCAP2_FJATHPLUS 0x00000001 /* Fujitsu Athena+ */ -#define ELF_SPARC_HWCAP2_VIS3B 0x00000002 /* VIS3 present on multiple chips */ +#define ELF_SPARC_HWCAP2_VIS3B 0x00000002 /* Subset of VIS3 present on sparc64 X+ */ #define ELF_SPARC_HWCAP2_ADP 0x00000004 /* Application Data Protection */ #define ELF_SPARC_HWCAP2_SPARC5 0x00000008 /* The 29 new fp and sub instructions */ #define ELF_SPARC_HWCAP2_MWAIT 0x00000010 /* mwait instruction and load/monitor ASIs */ diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index d378910..a8b6229 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,7 @@ +2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com> + + * sparc.h (HWCAP2_VIS3B): Documentation improved. + 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com> * sparc.h (sparc_opcode): new field `hwcaps2'. diff --git a/include/opcode/sparc.h b/include/opcode/sparc.h index cf4ff1c..463b9c1 100644 --- a/include/opcode/sparc.h +++ b/include/opcode/sparc.h @@ -151,7 +151,7 @@ typedef struct sparc_opcode #define HWCAP_CRC32C 0x20000000 /* CRC32C insn */ #define HWCAP2_FJATHPLUS 0x00000001 /* Fujitsu Athena+ */ -#define HWCAP2_VIS3B 0x00000002 /* VIS3 present on multiple chips */ +#define HWCAP2_VIS3B 0x00000002 /* Subset of VIS3 present on sparc64 X+. */ #define HWCAP2_ADP 0x00000004 /* Application Data Protection */ #define HWCAP2_SPARC5 0x00000008 /* The 29 new fp and sub instructions */ #define HWCAP2_MWAIT 0x00000010 /* mwait instruction and load/monitor ASIs */ diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index dcebadd..93d474a 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -2,6 +2,7 @@ * sparc-opc.c (sparc-opcodes): Fix several misplaced hwcap entries. + Annotate several instructions with the HWCAP2_VIS3B hwcap. 2014-10-15 Tristan Gingold <gingold@adacore.com> diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c index 2a0580b..7568974 100644 --- a/opcodes/sparc-opc.c +++ b/opcodes/sparc-opc.c @@ -314,12 +314,12 @@ const struct sparc_opcode sparc_opcodes[] = { { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1), "[i],F", 0, 0, 0, v9 }, { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, 0, 0, v9 }, /* ld [rs1+0],d */ -{ "ldx", F3(3, 0x21, 0)|RD(3), F3(~3, ~0x21, ~0)|RD(~3), "[1+2],(", 0, 0, 0, v9b }, -{ "ldx", F3(3, 0x21, 0)|RD(3), F3(~3, ~0x21, ~0)|RS2_G0|RD(~3),"[1],(", 0, 0, 0, v9b }, -{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RD(~3), "[1+i],(", 0, 0, 0, v9b }, -{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RD(~3), "[i+1],(", 0, 0, 0, v9b }, -{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RS1_G0|RD(~3),"[i],(", 0, 0, 0, v9b }, -{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~3),"[1],(", 0, 0, 0, v9b }, +{ "ldx", F3(3, 0x21, 0)|RD(3), F3(~3, ~0x21, ~0)|RD(~3), "[1+2],(", 0, 0, HWCAP2_VIS3B, v9b }, +{ "ldx", F3(3, 0x21, 0)|RD(3), F3(~3, ~0x21, ~0)|RS2_G0|RD(~3),"[1],(", 0, 0, HWCAP2_VIS3B, v9b }, +{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RD(~3), "[1+i],(", 0, 0, HWCAP2_VIS3B, v9b }, +{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RD(~3), "[i+1],(", 0, 0, HWCAP2_VIS3B, v9b }, +{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RS1_G0|RD(~3),"[i],(", 0, 0, HWCAP2_VIS3B, v9b }, +{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~3),"[1],(", 0, 0, HWCAP2_VIS3B, v9b }, { "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", 0, 0, 0, v6 }, { "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v6 }, /* lda [rs1+%g0],d */ @@ -1986,9 +1986,9 @@ SLCBCC("cbnefr", 15), { "fsra32", F3F(2, 0x36, 0x02f), F3F(~2, ~0x36, ~0x02f), "v,B,H", 0, HWCAP_VIS3, 0, v9b }, { "pdistn", F3F(2, 0x36, 0x03f), F3F(~2, ~0x36, ~0x03f), "v,B,d", 0, HWCAP_VIS3, 0, v9b }, { "fmean16", F3F(2, 0x36, 0x040), F3F(~2, ~0x36, ~0x040), "v,B,H", 0, HWCAP_VIS3, 0, v9b }, -{ "fpadd64", F3F(2, 0x36, 0x042), F3F(~2, ~0x36, ~0x042), "v,B,H", 0, HWCAP_VIS3, 0, v9b }, +{ "fpadd64", F3F(2, 0x36, 0x042), F3F(~2, ~0x36, ~0x042), "v,B,H", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9b }, { "fchksm16", F3F(2, 0x36, 0x044), F3F(~2, ~0x36, ~0x044), "v,B,H", 0, HWCAP_VIS3, 0, v9b }, -{ "fpsub64", F3F(2, 0x36, 0x046), F3F(~2, ~0x36, ~0x046), "v,B,H", 0, HWCAP_VIS3, 0, v9b }, +{ "fpsub64", F3F(2, 0x36, 0x046), F3F(~2, ~0x36, ~0x046), "v,B,H", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9b }, { "fpadds16", F3F(2, 0x36, 0x058), F3F(~2, ~0x36, ~0x058), "v,B,H", 0, HWCAP_VIS3, 0, v9b }, { "fpadds16s", F3F(2, 0x36, 0x059), F3F(~2, ~0x36, ~0x059), "e,f,g", 0, HWCAP_VIS3, 0, v9b }, { "fpadds32", F3F(2, 0x36, 0x05a), F3F(~2, ~0x36, ~0x05a), "v,B,H", 0, HWCAP_VIS3, 0, v9b }, @@ -2004,14 +2004,14 @@ SLCBCC("cbnefr", 15), { "movwtos", F3F(2, 0x36, 0x119), F3F(~2, ~0x36, ~0x119), "2,g", F_FLOAT, HWCAP_VIS3, 0, v9b }, { "xmulx", F3F(2, 0x36, 0x115), F3F(~2, ~0x36, ~0x115), "1,2,d", 0, HWCAP_VIS3, 0, v9b }, { "xmulxhi", F3F(2, 0x36, 0x116), F3F(~2, ~0x36, ~0x116), "1,2,d", 0, HWCAP_VIS3, 0, v9b }, -{ "fpcmpule8", F3F(2, 0x36, 0x120), F3F(~2, ~0x36, ~0x120), "v,B,d", 0, HWCAP_VIS3, 0, v9b }, +{ "fpcmpule8", F3F(2, 0x36, 0x120), F3F(~2, ~0x36, ~0x120), "v,B,d", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9b }, { "fucmple8", F3F(2, 0x36, 0x120), F3F(~2, ~0x36, ~0x120), "v,B,d", F_ALIAS, HWCAP_VIS3, 0, v9b }, -{ "fpcmpune8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", 0, HWCAP_VIS3, 0, v9b }, +{ "fpcmpune8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9b }, { "fpcmpne8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", F_PREF_ALIAS, HWCAP_VIS3, 0, v9b }, { "fucmpne8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", F_ALIAS, HWCAP_VIS3, 0, v9b }, -{ "fpcmpugt8", F3F(2, 0x36, 0x128), F3F(~2, ~0x36, ~0x128), "v,B,d", 0, HWCAP_VIS3, 0, v9b }, +{ "fpcmpugt8", F3F(2, 0x36, 0x128), F3F(~2, ~0x36, ~0x128), "v,B,d", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9b }, { "fucmpgt8", F3F(2, 0x36, 0x128), F3F(~2, ~0x36, ~0x128), "v,B,d", F_ALIAS, HWCAP_VIS3, 0, v9b }, -{ "fpcmpueq8", F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", 0, HWCAP_VIS3, 0, v9b }, +{ "fpcmpueq8", F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9b }, { "fpcmpeq8", F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", F_PREF_ALIAS, HWCAP_VIS3, 0, v9b }, { "fucmpeq8", F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", F_ALIAS, HWCAP_VIS3, 0, v9b }, {"aes_kexpand0",F3F(2, 0x36, 0x130), F3F(~2, ~0x36, ~0x130), "v,B,H", F_FLOAT, HWCAP_AES, 0, v9b }, |