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authorRichard Sandiford <richard.sandiford@arm.com>2016-09-21 16:51:43 +0100
committerRichard Sandiford <richard.sandiford@arm.com>2016-09-21 16:51:43 +0100
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[AArch64][SVE 19/32] Refactor address-printing code
SVE adds addresses in which the base or offset are vector registers. The addresses otherwise have the same kind of form as normal AArch64 addresses, including things like SXTW with or without a shift, UXTW with or without a shift, and LSL. This patch therefore refactors the address-printing code so that it can cope with both scalar and vector registers. opcodes/ * aarch64-opc.c (get_offset_int_reg_name): New function. (print_immediate_offset_address): Likewise. (print_register_offset_address): Take the base and offset registers as parameters. (aarch64_print_operand): Update caller accordingly. Use print_immediate_offset_address.
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