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| author | Jozef Lawrynowicz <jozef.l@mittosystems.com> | 2020-01-22 21:44:54 +0000 |
|---|---|---|
| committer | Jozef Lawrynowicz <jozef.l@mittosystems.com> | 2020-01-22 21:52:29 +0000 |
| commit | b7dcc42dfde12c3a1ccb7149b3cf8ef2f0992ea3 (patch) | |
| tree | c2a177ad023f97f05bedfaa9271e035e371d6a09 /ylwrap | |
| parent | be4c5e58bdc839898739e0332aee84abf6e5299a (diff) | |
| download | gdb-b7dcc42dfde12c3a1ccb7149b3cf8ef2f0992ea3.zip gdb-b7dcc42dfde12c3a1ccb7149b3cf8ef2f0992ea3.tar.gz gdb-b7dcc42dfde12c3a1ccb7149b3cf8ef2f0992ea3.tar.bz2 | |
MSP430: Fix simulator execution of RRUX instruction
The MSP430X RRUX instruction (unsigned right shift) is synthesized as
the RRC (rotate right through carry) instruction, but with the ZC
(zero carry) bit of the opcode extention word set.
Ensure the carry flag is ignored when the ZC bit is set.
sim/msp430/ChangeLog:
2020-01-22 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* msp430-sim.c (msp430_step_once): Ignore the carry flag when executing
an RRC instruction, if the ZC bit of the extension word is set.
sim/testsuite/sim/msp430/ChangeLog:
2020-01-22 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* rrux.s: New test.
Diffstat (limited to 'ylwrap')
0 files changed, 0 insertions, 0 deletions