import gdb-1999-09-13 snapshot

12 files changed, 405 insertions, 40 deletions

diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog
index 410aedf..0695db2 100644
--- a/sim/d10v/ChangeLog
+++ b/sim/d10v/ChangeLog
@@ -1,3 +1,25 @@
+Wed Sep  8 19:34:55 MDT 1999	Diego Novillo <dnovillo@cygnus.com>
+
+	* simops.c (op_types): Added new memory indirect type OP_MEMREF3.
+	(trace_input_func): Added support for OP_MEMREF3.
+	(OP_32010000): New instruction ld.
+	(OP_33010000): New instruction ld2w.
+	(OP_5209): New instruction sac.
+	(OP_4209): New instruction sachi.
+	(OP_3220): New instruction slae.
+	(OP_36010000): New instruction st.
+	(OP_37010000): New instruction st2w.
+
+1999-09-09  Stan Shebs  <shebs@andros.cygnus.com>
+
+	* interp.c (old_segment_mapping): New global.
+	(xfer_mem): Change the default segment mapping to be the way
+	that Mitsubishi prefers, but use the previous mapping if
+	old_segment_mapping is true.
+	(sim_open): Add an option -oldseg to get the old mapping.
+	(sim_create_inferior): Init mapping registers based on the
+	value of old_segment_mapping.
+
 1999-09-07  Nick Clifton  <nickc@cygnus.com>
 
 	* simops.c (OP_6601): Do not write back decremented address if
diff --git a/sim/d10v/interp.c b/sim/d10v/interp.c
index 4602ed2..bd16391 100644
--- a/sim/d10v/interp.c
+++ b/sim/d10v/interp.c
@@ -16,6 +16,11 @@ enum _leftright { LEFT_FIRST, RIGHT_FIRST };
 static char *myname;
 static SIM_OPEN_KIND sim_kind;
 int d10v_debug;
+
+/* Set this to true to get the previous segment layout. */
+
+int old_segment_mapping;
+
 host_callback *d10v_callback;
 unsigned long ins_type_counters[ (int)INS_MAX ];
 
@@ -375,17 +380,53 @@ xfer_mem (SIM_ADDR addr,
     }
 #endif
 
-  /* to access data, we use the following mapping 
-      0x00xxxxxx: Logical data address segment        (DMAP translated memory)
-      0x01xxxxxx: Logical instruction address segment (IMAP translated memory)
-      0x10xxxxxx: Physical data memory segment        (On-chip data memory)
-      0x11xxxxxx: Physical instruction memory segment (On-chip insn memory)
-      0x12xxxxxx: Phisical unified memory segment     (Unified memory)
+  /* To access data, we use the following mappings:
+
+     0x00xxxxxx: Physical unified memory segment     (Unified memory)
+     0x01xxxxxx: Physical instruction memory segment (On-chip insn memory)
+     0x02xxxxxx: Physical data memory segment        (On-chip data memory)
+     0x10xxxxxx: Logical data address segment        (DMAP translated memory)
+     0x11xxxxxx: Logical instruction address segment (IMAP translated memory)
+
+     Alternatively, the "old segment mapping" is still available by setting
+     old_segment_mapping to 1.  It looks like this:
+
+     0x00xxxxxx: Logical data address segment        (DMAP translated memory)
+     0x01xxxxxx: Logical instruction address segment (IMAP translated memory)
+     0x10xxxxxx: Physical data memory segment        (On-chip data memory)
+     0x11xxxxxx: Physical instruction memory segment (On-chip insn memory)
+     0x12xxxxxx: Physical unified memory segment     (Unified memory)
+
    */
 
+  /* However, if we've asked to use the previous generation of segment
+     mapping, rearrange the segments as follows. */
+
+  if (old_segment_mapping)
+    {
+      switch (segment)
+	{
+	case 0x00: /* DMAP translated memory */
+	  segment = 0x10;
+	  break;
+	case 0x01: /* IMAP translated memory */
+	  segment = 0x11;
+	  break;
+	case 0x10: /* On-chip data memory */
+	  segment = 0x02;
+	  break;
+	case 0x11: /* On-chip insn memory */
+	  segment = 0x01;
+	  break;
+	case 0x12: /* Unified memory */
+	  segment = 0x00;
+	  break;
+	}
+    }
+
   switch (segment)
     {
-    case 0x00: /* DMAP translated memory */
+    case 0x10: /* DMAP translated memory */
       {
 	int byte;
 	for (byte = 0; byte < size; byte++)
@@ -401,7 +442,7 @@ xfer_mem (SIM_ADDR addr,
 	return byte;
       }
 
-    case 0x01: /* IMAP translated memory */
+    case 0x11: /* IMAP translated memory */
       {
 	int byte;
 	for (byte = 0; byte < size; byte++)
@@ -417,7 +458,7 @@ xfer_mem (SIM_ADDR addr,
 	return byte;
       }
 
-    case 0x10: /* On-chip data memory */
+    case 0x02: /* On-chip data memory */
       {
 	addr &= ((1 << DMEM_SIZE) - 1);
 	if ((addr + size) > (1 << DMEM_SIZE))
@@ -430,7 +471,7 @@ xfer_mem (SIM_ADDR addr,
 	break;
       }
 
-    case 0x11: /* On-chip insn memory */
+    case 0x01: /* On-chip insn memory */
       {
 	addr &= ((1 << IMEM_SIZE) - 1);
 	if ((addr + size) > (1 << IMEM_SIZE))
@@ -443,7 +484,7 @@ xfer_mem (SIM_ADDR addr,
 	break;
       }
 
-    case 0x12: /* Unified memory */
+    case 0x00: /* Unified memory */
       {
 	int startsegment, startoffset;	/* Segment and offset within segment where xfer starts */
 	int endsegment, endoffset;	/* Segment and offset within segment where xfer ends */
@@ -484,12 +525,23 @@ xfer_mem (SIM_ADDR addr,
     default:
       {
 	(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: address 0x%lx is not in valid range\n", (long) addr);
- 	(*d10v_callback->printf_filtered) (d10v_callback, "0x00xxxxxx:  Logical data address segment		(DMAP translated memory)\n");
- 	(*d10v_callback->printf_filtered) (d10v_callback, "0x01xxxxxx:  Logical instruction address segment	(IMAP translated memory)\n");
- 	(*d10v_callback->printf_filtered) (d10v_callback, "0x10xxxxxx:  Physical data memory segment		(On-chip data memory)\n");
- 	(*d10v_callback->printf_filtered) (d10v_callback, "0x11xxxxxx:  Physical instruction memory segment	(On-chip insn memory)\n");
- 	(*d10v_callback->printf_filtered) (d10v_callback, "0x12xxxxxx:  Phisical unified memory segment		(Unified memory)\n");
-	return (0);
+	if (old_segment_mapping)
+	  {
+	    (*d10v_callback->printf_filtered) (d10v_callback, "0x00xxxxxx:  Logical data address segment            (DMAP translated memory)\n");
+	    (*d10v_callback->printf_filtered) (d10v_callback, "0x01xxxxxx:  Logical instruction address segment     (IMAP translated memory)\n");
+	    (*d10v_callback->printf_filtered) (d10v_callback, "0x10xxxxxx:  Physical data memory segment            (On-chip data memory)\n");
+	    (*d10v_callback->printf_filtered) (d10v_callback, "0x11xxxxxx:  Physical instruction memory segment     (On-chip insn memory)\n");
+	    (*d10v_callback->printf_filtered) (d10v_callback, "0x12xxxxxx:  Phisical unified memory segment         (Unified memory)\n");
+	  }
+	else
+	  {
+	    (*d10v_callback->printf_filtered) (d10v_callback, "0x00xxxxxx:  Physical unified memory segment		(Unified memory)\n");
+	    (*d10v_callback->printf_filtered) (d10v_callback, "0x01xxxxxx:  Physical instruction memory segment	(On-chip insn memory)\n");
+	    (*d10v_callback->printf_filtered) (d10v_callback, "0x02xxxxxx:  Physical data memory segment		(On-chip data memory)\n");
+	    (*d10v_callback->printf_filtered) (d10v_callback, "0x10xxxxxx:  Logical data address segment		(DMAP translated memory)\n");
+	    (*d10v_callback->printf_filtered) (d10v_callback, "0x11xxxxxx:  Logical instruction address segment	(IMAP translated memory)\n");
+	  }
+ 	return (0);
       }
     }
 
@@ -544,14 +596,17 @@ sim_open (kind, callback, abfd, argv)
   sim_kind = kind;
   d10v_callback = callback;
   myname = argv[0];
+  old_segment_mapping = 0;
 
   for (p = argv + 1; *p; ++p)
     {
+      if (strcmp (*p, "-oldseg") == 0)
+	old_segment_mapping = 1;
 #ifdef DEBUG
-      if (strcmp (*p, "-t") == 0)
+      else if (strcmp (*p, "-t") == 0)
 	d10v_debug = DEBUG;
-      else
 #endif
+      else
 	(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: unsupported option(s): %s\n",*p);
     }
   
@@ -969,7 +1024,7 @@ sim_create_inferior (sd, abfd, argv, env)
 
   /* cpu resets imap0 to 0 and imap1 to 0x7f, but D10V-EVA board */
   /* resets imap0 and imap1 to 0x1000. */
-  if (1)
+  if (old_segment_mapping)
     {
       SET_IMAP0 (0x0000);
       SET_IMAP1 (0x007f);
diff --git a/sim/d10v/simops.c b/sim/d10v/simops.c
index 54cc6fe..22bdd91 100644
--- a/sim/d10v/simops.c
+++ b/sim/d10v/simops.c
@@ -34,6 +34,7 @@ enum op_types {
   OP_CONSTANT4,
   OP_MEMREF,
   OP_MEMREF2,
+  OP_MEMREF3,
   OP_POSTDEC,
   OP_POSTINC,
   OP_PREDEC,
@@ -307,6 +308,12 @@ trace_input_func (name, in1, in2, in3)
 	  comma = ",";
 	  break;
 
+	case OP_MEMREF3:
+	  sprintf (p, "%s@%d", comma, OP[i]);
+	  p += strlen (p);
+	  comma = ",";
+	  break;
+
 	case OP_POSTINC:
 	  sprintf (p, "%s@r%d+", comma, OP[i]);
 	  p += strlen (p);
@@ -380,6 +387,10 @@ trace_input_func (name, in1, in2, in3)
 						 (uint16) GPR (OP[i]));
 	      break;
 
+	    case OP_MEMREF3:
+	      (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", (uint16) OP[i]);
+	      break;
+
 	    case OP_DREG:
 	      tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
 	      (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
@@ -1312,6 +1323,18 @@ OP_6000 ()
   trace_output_16 (tmp);
 }
 
+/* ld */
+void
+OP_32010000 ()
+{
+  uint16 tmp;
+  
+  trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
+  tmp = RW (OP[1]);
+  SET_GPR (OP[0], tmp);
+  trace_output_16 (tmp);
+}
+
 /* ld2w */
 void
 OP_31000000 ()
@@ -1364,6 +1387,18 @@ OP_6200 ()
   trace_output_32 (tmp);
 }
 
+/* ld2w */
+void
+OP_33010000 ()
+{
+  int32 tmp;
+  
+  trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
+  tmp = RLW (OP[1]);
+  SET_GPR32 (OP[0], tmp);
+  trace_output_32 (tmp);
+}
+
 /* ldb */
 void
 OP_38000000 ()
@@ -2207,6 +2242,74 @@ OP_5F40 ()
   trace_output_void ();
 }
 
+
+/* sac */
+void OP_5209 ()
+{
+  int64 tmp;
+
+  trace_input ("sac", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
+
+  tmp = SEXT40(ACC (OP[1]));
+
+  SET_PSW_F1 (PSW_F0);
+
+  if (tmp > SEXT40(MAX32))
+    {
+      tmp = (MAX32);
+      SET_PSW_F0 (1);
+    }
+  else if (tmp < SEXT40(MIN32))
+    {
+      tmp = 0x80000000;
+      SET_PSW_F0 (1);
+    }
+  else
+    {
+      tmp = (tmp & MASK32);
+      SET_PSW_F0 (0);
+    }
+
+  SET_GPR32 (OP[0], tmp);
+
+  trace_output_40 (tmp);
+}
+
+
+/* sachi */
+void
+OP_4209 ()
+{
+  int64 tmp;
+
+  trace_input ("sachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
+
+  tmp = SEXT40(ACC (OP[1]));
+
+  SET_PSW_F1 (PSW_F0);
+
+  if (tmp > SEXT40(MAX32))
+    {
+      tmp = 0x7fff;
+      SET_PSW_F0 (1);
+    }
+  else if (tmp < SEXT40(MIN32))
+    {
+      tmp = 0x8000;
+      SET_PSW_F0 (1);
+    }
+  else
+    {
+      tmp >>= 16;
+      SET_PSW_F0 (0);
+    }
+
+  SET_GPR (OP[0], tmp);
+
+  trace_output_16 (OP[0]);
+}
+
+
 /* sadd */
 void
 OP_1223 ()
@@ -2252,6 +2355,59 @@ OP_4613 ()
   trace_output_16 (tmp);
 }
 
+/* slae */
+void
+OP_3220 ()
+{
+  int64 tmp;
+  int16 reg;
+
+  trace_input ("slae", OP_ACCUM, OP_REG, OP_VOID);
+
+  reg = SEXT16( GPR (OP[1]));
+
+  if (reg >= 17 || reg <= -17)
+    {
+      (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", reg);
+      State.exception = SIGILL;
+      return;
+    }
+
+  tmp = SEXT40 (ACC (OP[0]));
+
+  if (PSW_ST && (tmp < SEXT40 (MIN32) || tmp > SEXT40 (MAX32)))
+    {
+      (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: value to shift 0x%x out of range.\n", tmp);
+      State.exception = SIGILL;
+      return;
+    }
+
+  if (reg >= 0 && reg <= 16)
+    {
+      tmp = SEXT56 ((SEXT56 (tmp)) << (GPR (OP[1])));
+      if (PSW_ST)
+	{
+	  if (tmp > SEXT40(MAX32))
+	    tmp = (MAX32);
+	  else if (tmp < SEXT40(MIN32))
+	    tmp = (MIN32);
+	  else
+	    tmp = (tmp & MASK40);
+	}
+      else
+	tmp = (tmp & MASK40);
+    }
+  else
+    {
+      tmp = (SEXT40 (ACC (OP[0]))) >> (-GPR (OP[1]));
+    }
+
+  SET_ACC(OP[0], tmp);
+
+  trace_output_40(tmp);
+}
+
+
 /* sleep */
 void
 OP_5FC0 ()
@@ -2535,6 +2691,15 @@ OP_6C01 ()
   trace_output_void ();
 }
 
+/* st */
+void
+OP_36010000 ()
+{
+  trace_input ("st", OP_REG, OP_MEMREF3, OP_VOID);
+  SW (OP[1], GPR (OP[0]));
+  trace_output_void ();
+}
+
 /* st2w */
 void
 OP_35000000 ()
@@ -2601,6 +2766,16 @@ OP_6E01 ()
   trace_output_void ();
 }
 
+/* st2w */
+void
+OP_37010000 ()
+{
+  trace_input ("st2w", OP_DREG, OP_MEMREF3, OP_VOID);
+  SW (OP [1] + 0, GPR (OP[0] + 0));
+  SW (OP [1] + 2, GPR (OP[0] + 1));
+  trace_output_void ();
+}
+
 /* stb */
 void
 OP_3C000000 ()
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 52a2d86..c12ec65 100644
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,7 @@
+Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
+
+	* mips.igen (MULT): Correct previous mis-applied patch.
+
 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
 
 	* mips.igen (delayslot32): Handle sequence like
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index 17748fe..6d92d4a 100644
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -1749,7 +1749,7 @@
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr4100:
 {
-  do_multu (SD_, RS, RT, RD);
+  do_multu (SD_, RS, RT, 0);
 }
 
 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
@@ -1758,7 +1758,7 @@
 *vr5000:
 *r3900:
 {
-  do_multu (SD_, RS, RT, 0);
+  do_multu (SD_, RS, RT, RD);
 }
 
 
diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog
index ca3bde2..e876e1f 100644
--- a/sim/testsuite/ChangeLog
+++ b/sim/testsuite/ChangeLog
@@ -1,32 +1,14 @@
-1999-09-06  Doug Evans  <devans@casey.cygnus.com>
-
-	* sim/arm/testutils.inc: Testsuite utilities.
-	* sim/arm/adc.cgs: New testcase.
-
 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 
 	* configure: Regenerated to track ../common/aclocal.m4 changes.
 
 1999-08-30  Doug Evans  <devans@casey.cygnus.com>
 
-	* sim/arm/thumb/allthumb.exp: New driver for thumb testcases.
-	* sim/arm/allinsn.exp: New driver for arm testcases.
-
 	* lib/sim-defs.exp (run_sim_test): Rename all_machs arg to
 	requested_machs, now is list of machs to run tests for.
 	Delete locals AS,ASFLAGS,LD,LDFLAGS.  Use target_assemble
 	and target_link instead.
 
-1999-07-16  Ben Elliston  <bje@cygnus.com>
-
-	* sim/arm/misaligned1.ms: New test case.
-	* sim/arm/misaligned2.ms: Likewise.
-	* sim/arm/misaligned3.ms: Likewise.
-
-1999-07-16  Ben Elliston  <bje@cygnus.com>
-
-	* sim/arm/misc.exp: Enable basic tests.
-
 1999-04-21  Doug Evans  <devans@casey.cygnus.com>
 
 	* sim/m32r/nop.cgs: Add missing nop insn.
diff --git a/sim/testsuite/d10v-elf/ChangeLog b/sim/testsuite/d10v-elf/ChangeLog
index b3b7f8c..723f88a 100644
--- a/sim/testsuite/d10v-elf/ChangeLog
+++ b/sim/testsuite/d10v-elf/ChangeLog
@@ -1,3 +1,10 @@
+Wed Sep  8 19:34:55 MDT 1999	Diego Novillo <dnovillo@cygnus.com>
+
+	* t-ld-st.s: New file.
+	* t-sac.s: New file.
+	* t-sachi.s: New file.
+	* t-slae.s: New file.
+
 1999-01-13  Jason Molenda  (jsm@bugshack.cygnus.com)
 
 	* t-sadd.s: New file.
diff --git a/sim/testsuite/d10v-elf/Makefile.in b/sim/testsuite/d10v-elf/Makefile.in
index 09d59ac..b170f37 100644
--- a/sim/testsuite/d10v-elf/Makefile.in
+++ b/sim/testsuite/d10v-elf/Makefile.in
@@ -41,6 +41,7 @@ TESTS = \
 	exit47.ko \
 	hello.hi \
 	t-dbt.ok \
+	t-ld-st.ok \
 	t-mac.ok \
 	t-mvtac.ok \
 	t-mvtc.ok \
@@ -51,7 +52,10 @@ TESTS = \
 	t-rdt.ok \
 	t-rep.ok \
 	t-rte.ok \
+	t-sac.ok \
+	t-sachi.ok \
 	t-sadd.ok \
+	t-slae.ok \
 	t-sp.ok \
 	t-sub2w.ok \
 	t-sub.ok \
diff --git a/sim/testsuite/d10v-elf/t-ld-st.s b/sim/testsuite/d10v-elf/t-ld-st.s
new file mode 100644
index 0000000..ec9f202
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-ld-st.s
@@ -0,0 +1,32 @@
+.include "t-macros.i"
+
+	start
+
+	; Test ld and st
+	ld r4, @foo
+	check 1 r4 0xdead
+
+	ldi r4, #0x2152
+	st r4, @foo
+	ld r4, @foo
+	check 2 r4 0x2152
+
+	; Test ld2w and st2w
+	ldi r4, #0xdead
+	st r4, @foo
+	ld2w r4, @foo
+	check2w2 3 r4 0xdead 0xf000
+
+	ldi r4, #0x2112
+	ldi r5, #0x1984
+	st2w r4, @foo
+	ld2w r4, @foo
+	check2w2 4 r4 0x2112 0x1984
+
+	.data
+	.align 2
+foo:	.short 0xdead
+bar:	.short 0xf000
+	.text
+
+	exit0
diff --git a/sim/testsuite/d10v-elf/t-sac.s b/sim/testsuite/d10v-elf/t-sac.s
new file mode 100644
index 0000000..7042be0
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-sac.s
@@ -0,0 +1,23 @@
+.include "t-macros.i"
+
+	start
+
+test_sac_1:
+	loadacc2 a0 0x00 0xAFFF 0x0000
+	sac r4, a0
+	check 1 r4 0x7FFF
+	check 2 r5 0xFFFF
+
+test_sac_2:
+	loadacc2 a0 0xFF 0x7000 0x0000
+	sac r4, a0
+	check 3 r4 0x8000
+	check 4 r5 0x0000
+
+test_sac_3:
+	loadacc2 a0 0x00 0x1000 0xA000
+	sac r4, a0
+	check 5 r4 0x1000
+	check 6 r5 0xA000
+
+	exit0
diff --git a/sim/testsuite/d10v-elf/t-sachi.s b/sim/testsuite/d10v-elf/t-sachi.s
new file mode 100644
index 0000000..7774ee0
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-sachi.s
@@ -0,0 +1,22 @@
+.include "t-macros.i"
+
+	start
+
+test_sachi_1:
+	loadacc2 a0 0x00 0xAFFF 0x0000
+	sachi r4, a0
+	check 1 r4 0x7FFF
+
+
+test_sachi_2:
+	loadacc2 a0 0xFF 0x8000 0x1000
+	sachi r4, a0
+	check 2 r4 0x8000
+
+
+test_sachi_3:
+	loadacc2 a0 0x00 0x1000 0xA000
+	sachi r4, a0
+	check 3 r4 0x1000
+
+	exit0
diff --git a/sim/testsuite/d10v-elf/t-slae.s b/sim/testsuite/d10v-elf/t-slae.s
new file mode 100644
index 0000000..6d8422d
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-slae.s
@@ -0,0 +1,39 @@
+.include "t-macros.i"
+
+	start
+
+test_slae_1:
+	loadpsw2 PSW_ST|PSW_FX
+	loadacc2 a0 0x00 0x0AFF 0xF000
+	ldi r0, 4
+	slae a0, r0
+	checkacc2 1 a0 0x00 0x7FFF 0xFFFF
+
+test_slae_2:
+	loadpsw2 PSW_ST|PSW_FX
+	loadacc2 a0 0xFF 0xF700 0x1000
+	ldi r0, 4
+	slae a0, r0
+	checkacc2 2 a0 0xFF 0x8000 0x0000
+
+test_slae_3:
+	loadpsw2 PSW_ST|PSW_FX
+	loadacc2 a0 0x00 0x0010 0xA000
+	ldi r0, 4
+	slae a0, r0
+	checkacc2 3 a0 0x00 0x010A 0x0000
+
+test_slae_4:
+	loadpsw2 0
+	loadacc2 a0 0x00 0x0010 0xA000
+	ldi r0, 4
+	slae a0, r0
+	checkacc2 4 a0 0x00 0x010A 0x0000
+
+test_slae_5:
+	loadacc2 a0 0x00 0x0010 0xA000
+	ldi r0, -4
+	slae a0, r0
+	checkacc2 4 a0 0x00 0x0001 0x0A00
+
+	exit0