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| author | Yoshinori Sato <ysato@users.sourceforge.jp> | 2021-05-21 22:40:04 +0900 |
|---|---|---|
| committer | Yoshinori Sato <ysato@users.sourceforge.jp> | 2021-05-28 21:14:24 +0900 |
| commit | 0ef4c3f83b044a9ed4b49f4ebc9d8480ca9aa4fe (patch) | |
| tree | 661d91ebb556bb7ab3f8a36c3e97bec72dbb9ffd /sim | |
| parent | 3633d4fb4469f5bc4e6e1593b65c7fc93d3805bb (diff) | |
| download | gdb-0ef4c3f83b044a9ed4b49f4ebc9d8480ca9aa4fe.zip gdb-0ef4c3f83b044a9ed4b49f4ebc9d8480ca9aa4fe.tar.gz gdb-0ef4c3f83b044a9ed4b49f4ebc9d8480ca9aa4fe.tar.bz2 | |
sim: h8300 Fixed different behavior in preinc/predec.
* sim-main.h (h8_typecodes): Add operand type OP_REG_DEC, OP_REG_INC.
* compile.c (decode): Rewrite oprand type for specific case.
(fetch_1): Add handling OP_REG_DEC and OP_REG_INC.
(step_once): Fix operand fetch order.
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/h8300/ChangeLog | 7 | ||||
| -rw-r--r-- | sim/h8300/compile.c | 52 | ||||
| -rw-r--r-- | sim/h8300/sim-main.h | 4 |
3 files changed, 60 insertions, 3 deletions
diff --git a/sim/h8300/ChangeLog b/sim/h8300/ChangeLog index b6d91c8..c07a5929 100644 --- a/sim/h8300/ChangeLog +++ b/sim/h8300/ChangeLog @@ -1,3 +1,10 @@ +2021-05-28 Yoshinori Sato <ysato@users.sourceforge.jp> + + * sim-main.h (h8_typecodes): Add operand type OP_REG_DEC, OP_REG_INC. + * compile.c (decode): Rewrite oprand type for specific case. + (fetch_1): Add handling OP_REG_DEC and OP_REG_INC. + (step_once): Fix operand fetch order. + 2021-05-17 Mike Frysinger <vapier@gentoo.org> * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Delete. diff --git a/sim/h8300/compile.c b/sim/h8300/compile.c index a45a676..01e9766 100644 --- a/sim/h8300/compile.c +++ b/sim/h8300/compile.c @@ -1100,6 +1100,35 @@ decode (SIM_DESC sd, int addr, unsigned char *data, decoded_inst *dst) /* End of Processing for system calls. */ } + /* Use same register is specified for source + and destination. + The value of source will be the value after + address calculation. */ + if (OP_KIND (dst->opcode) != O_CMP && + OP_KIND (dst->src.type) == OP_REG && + (dst->src.reg & 7) == dst->dst.reg) { + switch (OP_KIND (dst->dst.type)) + { + case OP_POSTDEC: + dst->src.type = X (OP_REG_DEC, + OP_SIZE (dst->dst.type)); + break; + case OP_POSTINC: + dst->src.type = X (OP_REG_INC, + OP_SIZE (dst->dst.type)); + break; + case OP_PREINC: + if (OP_KIND (dst->opcode) == O_MOV) + dst->src.type = X (OP_REG_INC, + OP_SIZE (dst->dst.type)); + break; + case OP_PREDEC: + if (OP_KIND (dst->opcode) == O_MOV) + dst->src.type = X (OP_REG_DEC, + OP_SIZE (dst->dst.type)); + break; + } + } dst->next_pc = addr + len / 2; return; } @@ -1370,6 +1399,25 @@ fetch_1 (SIM_DESC sd, ea_type *arg, int *val, int twice) *val = abs; break; + case X (OP_REG_DEC, SB): /* Register direct, affected decrement byte. */ + *val = GET_B_REG (rn) - 1; + break; + case X (OP_REG_DEC, SW): /* Register direct, affected decrement word. */ + *val = GET_W_REG (rn) - 2; + break; + case X (OP_REG_DEC, SL): /* Register direct, affected decrement long. */ + *val = GET_L_REG (rn) - 4; + break; + case X (OP_REG_INC, SB): /* Register direct, affected increment byte. */ + *val = GET_B_REG (rn) + 1; + break; + case X (OP_REG_INC, SW): /* Register direct, affected increment word. */ + *val = GET_W_REG (rn) + 2; + break; + case X (OP_REG_INC, SL): /* Register direct, affected increment long. */ + *val = GET_L_REG (rn) + 4; + break; + case X (OP_MEM, SB): /* Why isn't this implemented? */ default: sim_engine_halt (sd, cpu, NULL, NULL_CIA, sim_stopped, SIM_SIGSEGV); @@ -1981,7 +2029,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) case O (O_AND, SB): /* and.b */ /* Fetch rd and ea. */ - if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd)) + if (fetch2 (sd, &code->dst, &rd) || fetch (sd, &code->src, &ea)) goto end; res = rd & ea; goto log8; @@ -2002,7 +2050,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) case O (O_OR, SB): /* or.b */ /* Fetch rd and ea. */ - if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd)) + if (fetch2 (sd, &code->dst, &rd) || fetch (sd, &code->src, &ea)) goto end; res = rd | ea; goto log8; diff --git a/sim/h8300/sim-main.h b/sim/h8300/sim-main.h index a0aa9ef..f27ba68 100644 --- a/sim/h8300/sim-main.h +++ b/sim/h8300/sim-main.h @@ -82,7 +82,9 @@ enum h8_typecodes { /* FIXME: memory indirect? */ OP_INDEXB, /* Byte index mode */ OP_INDEXW, /* Word index mode */ - OP_INDEXL /* Long index mode */ + OP_INDEXL, /* Long index mode */ + OP_REG_DEC, /* Register direct. affect address decrement. */ + OP_REG_INC, /* Register direct. affect address increment. */ }; #include "sim-basics.h" |