aboutsummaryrefslogtreecommitdiff
path: root/sim
diff options
context:
space:
mode:
authorStephane Carrez <stcarrez@nerim.fr>2002-08-13 08:38:09 +0000
committerStephane Carrez <stcarrez@nerim.fr>2002-08-13 08:38:09 +0000
commit7230d80931209c515783b9b5bebaf7dde2c6362e (patch)
tree57097a6dc3ebb52fca8aef7dd727b98356f17d31 /sim
parentdcceded28ac77cfef16492bf4b3fb3c0e19c0524 (diff)
downloadgdb-7230d80931209c515783b9b5bebaf7dde2c6362e.zip
gdb-7230d80931209c515783b9b5bebaf7dde2c6362e.tar.gz
gdb-7230d80931209c515783b9b5bebaf7dde2c6362e.tar.bz2
* dv-m68hc11.c (m68hc11cpu_io_read_buffer): Translate memory
bank window to some virtual address to read from extended memory. (m68hc11cpu_io_write_buffer): Likewise for writing. (attach_m68hc11_regs): When use_bank property is defined, attached to the 68HC12 16K memory bank window. * interp.c (sim_hw_configure): Create memory region for banked memory.
Diffstat (limited to 'sim')
-rw-r--r--sim/m68hc11/ChangeLog13
-rw-r--r--sim/m68hc11/dv-m68hc11.c23
-rw-r--r--sim/m68hc11/interp.c5
3 files changed, 40 insertions, 1 deletions
diff --git a/sim/m68hc11/ChangeLog b/sim/m68hc11/ChangeLog
index 03f491f..a48fa5e 100644
--- a/sim/m68hc11/ChangeLog
+++ b/sim/m68hc11/ChangeLog
@@ -1,3 +1,16 @@
+2002-08-13 Stephane Carrez <stcarrez@nerim.fr>
+
+ * dv-m68hc11.c (m68hc11cpu_io_read_buffer): Translate memory
+ bank window to some virtual address to read from extended memory.
+ (m68hc11cpu_io_write_buffer): Likewise for writing.
+ (attach_m68hc11_regs): When use_bank property is defined, attached
+ to the 68HC12 16K memory bank window.
+
+2002-08-13 Stephane Carrez <Stephane.Carrez@nerim.fr>
+
+ * interp.c (sim_hw_configure): Create memory region for banked
+ memory.
+
2002-08-13 Stephane Carrez <Stephane.Carrez@nerim.fr>
* interp.c (sim_hw_configure): Connect port-X to cpu-write-port.
diff --git a/sim/m68hc11/dv-m68hc11.c b/sim/m68hc11/dv-m68hc11.c
index 49c33e3..669a045 100644
--- a/sim/m68hc11/dv-m68hc11.c
+++ b/sim/m68hc11/dv-m68hc11.c
@@ -321,6 +321,13 @@ attach_m68hc11_regs (struct hw *me,
cpu->cpu_frequency = 8*1000*1000;
}
+ if (hw_find_property (me, "use_bank") != NULL)
+ hw_attach_address (hw_parent (me), 0,
+ exec_map,
+ 0x08000,
+ 0x04000,
+ me);
+
cpu_mode = "expanded";
if (hw_find_property (me, "mode") != NULL)
cpu_mode = hw_find_string_property (me, "mode");
@@ -836,6 +843,14 @@ m68hc11cpu_io_read_buffer (struct hw *me,
sd = hw_system (me);
cpu = STATE_CPU (sd, 0);
+ if (base >= 0x8000 && base < 0xc000)
+ {
+ address_word virt_addr = phys_to_virt (cpu, base);
+ if (virt_addr != base)
+ return sim_core_read_buffer (sd, cpu, space, dest,
+ virt_addr, nr_bytes);
+ }
+
/* Handle reads for the sub-devices. */
base -= controller->attach_address;
result = sim_core_read_buffer (sd, cpu,
@@ -1075,6 +1090,14 @@ m68hc11cpu_io_write_buffer (struct hw *me,
sd = hw_system (me);
cpu = STATE_CPU (sd, 0);
+
+ if (base >= 0x8000 && base < 0xc000)
+ {
+ address_word virt_addr = phys_to_virt (cpu, base);
+ if (virt_addr != base)
+ return sim_core_write_buffer (sd, cpu, space, source,
+ virt_addr, nr_bytes);
+ }
base -= controller->attach_address;
result = sim_core_write_buffer (sd, cpu,
io_map, source, base, nr_bytes);
diff --git a/sim/m68hc11/interp.c b/sim/m68hc11/interp.c
index eee7429..1f3b86f 100644
--- a/sim/m68hc11/interp.c
+++ b/sim/m68hc11/interp.c
@@ -242,11 +242,14 @@ sim_hw_configure (SIM_DESC sd)
{
/* Allocate core external memory. */
sim_do_commandf (sd, "memory region 0x%lx@%d,0x%lx",
- 0x8000, M6811_RAM_LEVEL, 0x8000);
+ 0xC000, M6811_RAM_LEVEL, 0x4000);
sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
M6811_RAM_LEVEL);
+ sim_do_commandf (sd, "memory region 0x01000000@%d,0x100000",
+ M6811_RAM_LEVEL);
sim_hw_parse (sd, "/m68hc12/reg 0x0 0x3FF");
+ sim_hw_parse (sd, "/m68hc12/use_bank 1");
}
if (!hw_tree_find_property (device_tree, "/m68hc12/m68hc12sio@1/reg"))