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authorAlexandre Oliva <aoliva@redhat.com>2000-07-04 06:39:39 +0000
committerAlexandre Oliva <aoliva@redhat.com>2000-07-04 06:39:39 +0000
commit13b6dd6f68d9eb79f9d3dbe730ec1b6aa9bef737 (patch)
tree5e845d5d392e1b36c4793793cb1d094c06a05823 /sim
parent892c6b9d8fca691330232aaea9c0aaaff880feb1 (diff)
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* armemu.c (LoadSMult): Use WriteR15() to discard the least
significant bits of PC.
Diffstat (limited to 'sim')
-rw-r--r--sim/arm/ChangeLog3
-rw-r--r--sim/arm/armemu.c4
2 files changed, 5 insertions, 2 deletions
diff --git a/sim/arm/ChangeLog b/sim/arm/ChangeLog
index 526b49d..06345b2 100644
--- a/sim/arm/ChangeLog
+++ b/sim/arm/ChangeLog
@@ -1,5 +1,8 @@
2000-07-04 Alexandre Oliva <aoliva@redhat.com>
+ * armemu.c (LoadSMult): Use WriteR15() to discard the least
+ significant bits of PC.
+
* armemu.h (WRITEDESTB): New macro.
* armemu.c (ARMul_Emulate26, bl): Use WriteR15Branch() to
modify PC. Moved the existing logic...
diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c
index 2fc0eda..43cd6dc 100644
--- a/sim/arm/armemu.c
+++ b/sim/arm/armemu.c
@@ -3544,7 +3544,7 @@ LoadSMult (ARMul_State * state, ARMword instr,
state->Cpsr = GETSPSR (state->Bank);
ARMul_CPSRAltered (state);
}
- state->Reg[15] = PC;
+ WriteR15 (state, PC);
#else
if (state->Mode == USER26MODE || state->Mode == USER32MODE)
{ /* protect bits in user mode */
@@ -3555,8 +3555,8 @@ LoadSMult (ARMul_State * state, ARMword instr,
}
else
ARMul_R15Altered (state);
-#endif
FLUSHPIPE;
+#endif
}
if (!BIT (15) && state->Mode != USER26MODE && state->Mode != USER32MODE)