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authorAnthony Green <green@redhat.com>2009-05-10 13:25:57 +0000
committerAnthony Green <green@redhat.com>2009-05-10 13:25:57 +0000
commit77176dfc67dc5b8d8984af31ae195b95bac8f8e5 (patch)
treee94387620020420b1bf66c01a0ca2323bc10dd97 /sim
parentbd518e6be47d7fb7a38acbeb401356f9eb858210 (diff)
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Add missing break statemenets.
Diffstat (limited to 'sim')
-rw-r--r--sim/moxie/ChangeLog4
-rw-r--r--sim/moxie/interp.c2
2 files changed, 6 insertions, 0 deletions
diff --git a/sim/moxie/ChangeLog b/sim/moxie/ChangeLog
index fdad6c5..c528de3 100644
--- a/sim/moxie/ChangeLog
+++ b/sim/moxie/ChangeLog
@@ -1,3 +1,7 @@
+2009-05-09 Anthony Green <green@moxielogic.com>
+
+ * interp.c (sim_resume): Add missing breaks in switch.
+
2008-10-03 Anthony Green <green@moxielogic.com>
* interp.c (sim_resume): Add support for ldo.b, sto.b, ldo.s, sto.s.
diff --git a/sim/moxie/interp.c b/sim/moxie/interp.c
index 2be561c..dd87648 100644
--- a/sim/moxie/interp.c
+++ b/sim/moxie/interp.c
@@ -460,6 +460,7 @@ sim_resume (sd, step, siggnal)
TRACE("gsr");
cpu.asregs.regs[a] = cpu.asregs.sregs[v];
}
+ break;
case 0x03: /* ssr */
{
int a = (inst >> 8) & 0xf;
@@ -467,6 +468,7 @@ sim_resume (sd, step, siggnal)
TRACE("ssr");
cpu.asregs.sregs[v] = cpu.asregs.regs[a];
}
+ break;
default:
TRACE("SIGILL2");
cpu.asregs.exception = SIGILL;