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author | Joel Brobecker <brobecker@gnat.com> | 2008-05-09 15:03:09 +0000 |
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committer | Joel Brobecker <brobecker@gnat.com> | 2008-05-09 15:03:09 +0000 |
commit | 7010a0c9019a68999ca6e43b4eec8b28d0907cbc (patch) | |
tree | c9dde5c32eda8f0e2f3d2cb8738c42b765694ab4 /sim | |
parent | 55ba0940d96a0da92a3ab3234a5fb7ae0b445b5f (diff) | |
download | gdb-7010a0c9019a68999ca6e43b4eec8b28d0907cbc.zip gdb-7010a0c9019a68999ca6e43b4eec8b28d0907cbc.tar.gz gdb-7010a0c9019a68999ca6e43b4eec8b28d0907cbc.tar.bz2 |
* ppc/altivec.igen (vperm): Latch inputs into temporaries.
Diffstat (limited to 'sim')
-rw-r--r-- | sim/ChangeLog | 4 | ||||
-rw-r--r-- | sim/ppc/altivec.igen | 9 |
2 files changed, 11 insertions, 2 deletions
diff --git a/sim/ChangeLog b/sim/ChangeLog index ea3b306..521ccfb 100644 --- a/sim/ChangeLog +++ b/sim/ChangeLog @@ -1,3 +1,7 @@ +2008-05-09 Olivier Hainque <hainque@adacore.com> + + * ppc/altivec.igen (vperm): Latch inputs into temporaries. + 2008-03-25 M R Swami Reddy <MR.Swami.Reddy@nsc.com> * MAINTAINERS: Add myself as maintainer of cr16 port. diff --git a/sim/ppc/altivec.igen b/sim/ppc/altivec.igen index d933f56..3a224cc 100644 --- a/sim/ppc/altivec.igen +++ b/sim/ppc/altivec.igen @@ -1634,12 +1634,17 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat 0.4,6.VS,11.VA,16.VB,21.VC,26.43:VX:av:vperm %VD, %VA, %VB, %VC:Vector Permute int i, who; + /* The permutation vector might have us read into the source vectors + back at positions before the iteration index, so we must latch the + sources to prevent early-clobbering in case the destination vector + is the same as one of them. */ + vreg myvA = (*vA), myvB = (*vB); for (i = 0; i < 16; i++) { who = (*vC).b[AV_BINDEX(i)] & 0x1f; if (who & 0x10) - (*vS).b[AV_BINDEX(i)] = (*vB).b[AV_BINDEX(who & 0xf)]; + (*vS).b[AV_BINDEX(i)] = myvB.b[AV_BINDEX(who & 0xf)]; else - (*vS).b[AV_BINDEX(i)] = (*vA).b[AV_BINDEX(who & 0xf)]; + (*vS).b[AV_BINDEX(i)] = myvA.b[AV_BINDEX(who & 0xf)]; } PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK); |