2001-11-14 Dave Brolley <brolley@redhat.com>

* arch.c: Regenerate. * arch.h: Regenerate. * cpu.c: Regenerate. * cpu.h: Regenerate. * cpuall.h: Regenerate. * cpux.c: Regenerate. * cpux.h: Regenerate. * decode.c: Regenerate. * decode.h: Regenerate. * decodex.c: Regenerate. * decodex.h: Regenerate. * model.c: Regenerate. * modelx.c: Regenerate. * sem-switch.c: Regenerate. * sem.c: Regenerate. * semx-switch.c: Regenerate.
author: Dave Brolley <brolley@redhat.com> 2001-11-14 19:51:40 +0000
committer: Dave Brolley <brolley@redhat.com> 2001-11-14 19:51:40 +0000
commit: 378af1d671c4ac1e6501c740ba97bbfe1964bf44 (patch)
tree: 4d2c2d7b5dfc169f919fe24e1871ca1e959a43cc /sim
parent: 3e43c635d5ceca27f56f51ca22ed7bce1e64ade0 (diff)
download: gdb-378af1d671c4ac1e6501c740ba97bbfe1964bf44.zip
gdb-378af1d671c4ac1e6501c740ba97bbfe1964bf44.tar.gz
gdb-378af1d671c4ac1e6501c740ba97bbfe1964bf44.tar.bz2
17 files changed, 739 insertions, 226 deletions
diff --git a/sim/m32r/ChangeLog b/sim/m32r/ChangeLog
index 3fe36f5..7762c7b 100644
--- a/sim/m32r/ChangeLog
+++ b/sim/m32r/ChangeLog
@@ -1,3 +1,22 @@
+2001-11-14  Dave Brolley  <brolley@redhat.com>
+
+	* arch.c: Regenerate.
+	* arch.h: Regenerate.
+	* cpu.c: Regenerate.
+	* cpu.h: Regenerate.
+	* cpuall.h: Regenerate.
+	* cpux.c: Regenerate.
+	* cpux.h: Regenerate.
+	* decode.c: Regenerate.
+	* decode.h: Regenerate.
+	* decodex.c: Regenerate.
+	* decodex.h: Regenerate.
+	* model.c: Regenerate.
+	* modelx.c: Regenerate.
+	* sem-switch.c: Regenerate.
+	* sem.c: Regenerate.
+	* semx-switch.c: Regenerate.
+
 2001-07-05  Ben Elliston  <bje@redhat.com>
 
 	* Makefile.in (stamp-arch): Use $(CGEN_CPU_DIR).
@@ -6,22 +25,22 @@
 
 2001-03-05  Dave Brolley  <brolley@redhat.com>
 
-	arch.c: Regenerate.
-	arch.h: Regenerate.
-	cpu.c: Regenerate.
-	cpu.h: Regenerate.
-	cpuall.h: Regenerate.
-	cpux.c: Regenerate.
-	cpux.h: Regenerate.
-	decode.c: Regenerate.
-	decode.h: Regenerate.
-	decodex.c: Regenerate.
-	decodex.h: Regenerate.
-	model.c: Regenerate.
-	modelx.c: Regenerate.
-	sem-switch.c: Regenerate.
-	sem.c: Regenerate.
-	semx-switch.c: Regenerate.
+	* arch.c: Regenerate.
+	* arch.h: Regenerate.
+	* cpu.c: Regenerate.
+	* cpu.h: Regenerate.
+	* cpuall.h: Regenerate.
+	* cpux.c: Regenerate.
+	* cpux.h: Regenerate.
+	* decode.c: Regenerate.
+	* decode.h: Regenerate.
+	* decodex.c: Regenerate.
+	* decodex.h: Regenerate.
+	* model.c: Regenerate.
+	* modelx.c: Regenerate.
+	* sem-switch.c: Regenerate.
+	* sem.c: Regenerate.
+	* semx-switch.c: Regenerate.
 
 2001-01-12  Frank Ch. Eigler  <fche@redhat.com>
 
diff --git a/sim/m32r/arch.c b/sim/m32r/arch.c
index 4bc51b0..d6860c1 100644
--- a/sim/m32r/arch.c
+++ b/sim/m32r/arch.c
@@ -2,9 +2,9 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
 
-This file is part of the GNU Simulators.
+This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
diff --git a/sim/m32r/arch.h b/sim/m32r/arch.h
index 11b386e..9521f44 100644
--- a/sim/m32r/arch.h
+++ b/sim/m32r/arch.h
@@ -2,9 +2,9 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
 
-This file is part of the GNU Simulators.
+This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
diff --git a/sim/m32r/cpu.c b/sim/m32r/cpu.c
index f862899..d93943d 100644
--- a/sim/m32r/cpu.c
+++ b/sim/m32r/cpu.c
@@ -2,9 +2,9 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
 
-This file is part of the GNU Simulators.
+This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
diff --git a/sim/m32r/cpu.h b/sim/m32r/cpu.h
index 3b06978..6f9a3ff 100644
--- a/sim/m32r/cpu.h
+++ b/sim/m32r/cpu.h
@@ -2,9 +2,9 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
 
-This file is part of the GNU Simulators.
+This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
@@ -128,11 +128,11 @@ union sem_fields {
   } sfmt_trap;
   struct { /*  */
     IADDR i_disp24;
-    unsigned char out_h_gr_14;
+    unsigned char out_h_gr_SI_14;
   } sfmt_bl24;
   struct { /*  */
     IADDR i_disp8;
-    unsigned char out_h_gr_14;
+    unsigned char out_h_gr_SI_14;
   } sfmt_bl8;
   struct { /*  */
     SI* i_dr;
@@ -150,7 +150,7 @@ union sem_fields {
     SI* i_sr;
     UINT f_r2;
     unsigned char in_sr;
-    unsigned char out_h_gr_14;
+    unsigned char out_h_gr_SI_14;
   } sfmt_jl;
   struct { /*  */
     SI* i_dr;
diff --git a/sim/m32r/cpuall.h b/sim/m32r/cpuall.h
index a180022..0c16b21 100644
--- a/sim/m32r/cpuall.h
+++ b/sim/m32r/cpuall.h
@@ -2,9 +2,9 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
 
-This file is part of the GNU Simulators.
+This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
diff --git a/sim/m32r/cpux.c b/sim/m32r/cpux.c
index 95eb3a9..054828b 100644
--- a/sim/m32r/cpux.c
+++ b/sim/m32r/cpux.c
@@ -2,9 +2,9 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
 
-This file is part of the GNU Simulators.
+This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
diff --git a/sim/m32r/cpux.h b/sim/m32r/cpux.h
index 6385444..2d5cab4 100644
--- a/sim/m32r/cpux.h
+++ b/sim/m32r/cpux.h
@@ -2,9 +2,9 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
 
-This file is part of the GNU Simulators.
+This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
@@ -133,11 +133,11 @@ union sem_fields {
   } sfmt_trap;
   struct { /*  */
     IADDR i_disp24;
-    unsigned char out_h_gr_14;
+    unsigned char out_h_gr_SI_14;
   } sfmt_bl24;
   struct { /*  */
     IADDR i_disp8;
-    unsigned char out_h_gr_14;
+    unsigned char out_h_gr_SI_14;
   } sfmt_bl8;
   struct { /*  */
     SI f_imm1;
@@ -172,7 +172,7 @@ union sem_fields {
     SI* i_sr;
     UINT f_r2;
     unsigned char in_sr;
-    unsigned char out_h_gr_14;
+    unsigned char out_h_gr_SI_14;
   } sfmt_jl;
   struct { /*  */
     SI* i_dr;
@@ -772,19 +772,19 @@ struct parexec {
       USI pc;
     } sfmt_beqz;
     struct { /* e.g. bl.s $disp8 */
-      SI h_gr_14;
+      SI h_gr_SI_14;
       USI pc;
     } sfmt_bl8;
     struct { /* e.g. bl.l $disp24 */
-      SI h_gr_14;
+      SI h_gr_SI_14;
       USI pc;
     } sfmt_bl24;
     struct { /* e.g. bcl.s $disp8 */
-      SI h_gr_14;
+      SI h_gr_SI_14;
       USI pc;
     } sfmt_bcl8;
     struct { /* e.g. bcl.l $disp24 */
-      SI h_gr_14;
+      SI h_gr_SI_14;
       USI pc;
     } sfmt_bcl24;
     struct { /* e.g. bra.s $disp8 */
@@ -809,7 +809,7 @@ struct parexec {
       USI pc;
     } sfmt_jc;
     struct { /* e.g. jl $sr */
-      SI h_gr_14;
+      SI h_gr_SI_14;
       USI pc;
     } sfmt_jl;
     struct { /* e.g. jmp $sr */
@@ -821,6 +821,18 @@ struct parexec {
     struct { /* e.g. ld $dr,@($slo16,$sr) */
       SI dr;
     } sfmt_ld_d;
+    struct { /* e.g. ldb $dr,@$sr */
+      SI dr;
+    } sfmt_ldb;
+    struct { /* e.g. ldb $dr,@($slo16,$sr) */
+      SI dr;
+    } sfmt_ldb_d;
+    struct { /* e.g. ldh $dr,@$sr */
+      SI dr;
+    } sfmt_ldh;
+    struct { /* e.g. ldh $dr,@($slo16,$sr) */
+      SI dr;
+    } sfmt_ldh_d;
     struct { /* e.g. ld $dr,@$sr+ */
       SI dr;
       SI sr;
@@ -836,7 +848,7 @@ struct parexec {
     } sfmt_ldi16;
     struct { /* e.g. lock $dr,@$sr */
       SI dr;
-      BI h_lock;
+      BI h_lock_BI;
     } sfmt_lock;
     struct { /* e.g. machi $src1,$src2,$acc */
       DI acc;
@@ -866,9 +878,9 @@ struct parexec {
       DI accd;
     } sfmt_rac_dsi;
     struct { /* e.g. rte */
-      UQI h_bpsw;
-      USI h_cr_6;
-      UQI h_psw;
+      UQI h_bpsw_UQI;
+      USI h_cr_USI_6;
+      UQI h_psw_UQI;
       USI pc;
     } sfmt_rte;
     struct { /* e.g. seth $dr,$hash$hi16 */
@@ -881,46 +893,46 @@ struct parexec {
       SI dr;
     } sfmt_slli;
     struct { /* e.g. st $src1,@$src2 */
-      SI h_memory_src2;
-      USI h_memory_src2_idx;
+      SI h_memory_SI_src2;
+      USI h_memory_SI_src2_idx;
     } sfmt_st;
     struct { /* e.g. st $src1,@($slo16,$src2) */
-      SI h_memory_add__DFLT_src2_slo16;
-      USI h_memory_add__DFLT_src2_slo16_idx;
+      SI h_memory_SI_add__DFLT_src2_slo16;
+      USI h_memory_SI_add__DFLT_src2_slo16_idx;
     } sfmt_st_d;
     struct { /* e.g. stb $src1,@$src2 */
-      QI h_memory_src2;
-      USI h_memory_src2_idx;
+      QI h_memory_QI_src2;
+      USI h_memory_QI_src2_idx;
     } sfmt_stb;
     struct { /* e.g. stb $src1,@($slo16,$src2) */
-      QI h_memory_add__DFLT_src2_slo16;
-      USI h_memory_add__DFLT_src2_slo16_idx;
+      QI h_memory_QI_add__DFLT_src2_slo16;
+      USI h_memory_QI_add__DFLT_src2_slo16_idx;
     } sfmt_stb_d;
     struct { /* e.g. sth $src1,@$src2 */
-      HI h_memory_src2;
-      USI h_memory_src2_idx;
+      HI h_memory_HI_src2;
+      USI h_memory_HI_src2_idx;
     } sfmt_sth;
     struct { /* e.g. sth $src1,@($slo16,$src2) */
-      HI h_memory_add__DFLT_src2_slo16;
-      USI h_memory_add__DFLT_src2_slo16_idx;
+      HI h_memory_HI_add__DFLT_src2_slo16;
+      USI h_memory_HI_add__DFLT_src2_slo16_idx;
     } sfmt_sth_d;
     struct { /* e.g. st $src1,@+$src2 */
-      SI h_memory_new_src2;
-      USI h_memory_new_src2_idx;
+      SI h_memory_SI_new_src2;
+      USI h_memory_SI_new_src2_idx;
       SI src2;
     } sfmt_st_plus;
     struct { /* e.g. trap $uimm4 */
-      UQI h_bbpsw;
-      UQI h_bpsw;
-      USI h_cr_14;
-      USI h_cr_6;
-      UQI h_psw;
+      UQI h_bbpsw_UQI;
+      UQI h_bpsw_UQI;
+      USI h_cr_USI_14;
+      USI h_cr_USI_6;
+      UQI h_psw_UQI;
       SI pc;
     } sfmt_trap;
     struct { /* e.g. unlock $src1,@$src2 */
-      BI h_lock;
-      SI h_memory_src2;
-      USI h_memory_src2_idx;
+      BI h_lock_BI;
+      SI h_memory_SI_src2;
+      USI h_memory_SI_src2_idx;
     } sfmt_unlock;
     struct { /* e.g. satb $dr,$sr */
       SI dr;
@@ -929,16 +941,16 @@ struct parexec {
       SI dr;
     } sfmt_sat;
     struct { /* e.g. sadd */
-      DI h_accums_0;
+      DI h_accums_DI_0;
     } sfmt_sadd;
     struct { /* e.g. macwu1 $src1,$src2 */
-      DI h_accums_1;
+      DI h_accums_DI_1;
     } sfmt_macwu1;
     struct { /* e.g. msblo $src1,$src2 */
       DI accum;
     } sfmt_msblo;
     struct { /* e.g. mulwu1 $src1,$src2 */
-      DI h_accums_1;
+      DI h_accums_DI_1;
     } sfmt_mulwu1;
     struct { /* e.g. sc */
       int empty;
diff --git a/sim/m32r/decode.c b/sim/m32r/decode.c
index 52daa8b..83c3a38 100644
--- a/sim/m32r/decode.c
+++ b/sim/m32r/decode.c
@@ -2,9 +2,9 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
 
-This file is part of the GNU Simulators.
+This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
@@ -33,7 +33,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
    teensy bit of cpu in the decoder.  Moving it to malloc space is trivial
    but won't be done until necessary (we don't currently support the runtime
    addition of instructions nor an SMP machine with different cpus).  */
-static IDESC m32rbf_insn_data[M32RBF_INSN_MAX];
+static IDESC m32rbf_insn_data[M32RBF_INSN_UNLOCK + 1];
 
 /* Commas between elements are contained in the macros.
    Some of these are conditionally compiled out.  */
@@ -86,14 +86,14 @@ static const struct insn_sem m32rbf_insn_sem[] =
   { M32R_INSN_JMP, M32RBF_INSN_JMP, M32RBF_SFMT_JMP },
   { M32R_INSN_LD, M32RBF_INSN_LD, M32RBF_SFMT_LD },
   { M32R_INSN_LD_D, M32RBF_INSN_LD_D, M32RBF_SFMT_LD_D },
-  { M32R_INSN_LDB, M32RBF_INSN_LDB, M32RBF_SFMT_LD },
-  { M32R_INSN_LDB_D, M32RBF_INSN_LDB_D, M32RBF_SFMT_LD_D },
-  { M32R_INSN_LDH, M32RBF_INSN_LDH, M32RBF_SFMT_LD },
-  { M32R_INSN_LDH_D, M32RBF_INSN_LDH_D, M32RBF_SFMT_LD_D },
-  { M32R_INSN_LDUB, M32RBF_INSN_LDUB, M32RBF_SFMT_LD },
-  { M32R_INSN_LDUB_D, M32RBF_INSN_LDUB_D, M32RBF_SFMT_LD_D },
-  { M32R_INSN_LDUH, M32RBF_INSN_LDUH, M32RBF_SFMT_LD },
-  { M32R_INSN_LDUH_D, M32RBF_INSN_LDUH_D, M32RBF_SFMT_LD_D },
+  { M32R_INSN_LDB, M32RBF_INSN_LDB, M32RBF_SFMT_LDB },
+  { M32R_INSN_LDB_D, M32RBF_INSN_LDB_D, M32RBF_SFMT_LDB_D },
+  { M32R_INSN_LDH, M32RBF_INSN_LDH, M32RBF_SFMT_LDH },
+  { M32R_INSN_LDH_D, M32RBF_INSN_LDH_D, M32RBF_SFMT_LDH_D },
+  { M32R_INSN_LDUB, M32RBF_INSN_LDUB, M32RBF_SFMT_LDB },
+  { M32R_INSN_LDUB_D, M32RBF_INSN_LDUB_D, M32RBF_SFMT_LDB_D },
+  { M32R_INSN_LDUH, M32RBF_INSN_LDUH, M32RBF_SFMT_LDH },
+  { M32R_INSN_LDUH_D, M32RBF_INSN_LDUH_D, M32RBF_SFMT_LDH_D },
   { M32R_INSN_LD_PLUS, M32RBF_INSN_LD_PLUS, M32RBF_SFMT_LD_PLUS },
   { M32R_INSN_LD24, M32RBF_INSN_LD24, M32RBF_SFMT_LD24 },
   { M32R_INSN_LDI8, M32RBF_INSN_LDI8, M32RBF_SFMT_LDI8 },
@@ -186,7 +186,7 @@ m32rbf_init_idesc_table (SIM_CPU *cpu)
 {
   IDESC *id,*tabend;
   const struct insn_sem *t,*tend;
-  int tabsize = M32RBF_INSN_MAX;
+  int tabsize = sizeof (m32rbf_insn_data) / sizeof (IDESC);
   IDESC *table = m32rbf_insn_data;
 
   memset (table, 0, tabsize * sizeof (IDESC));
@@ -224,15 +224,60 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
       unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
       switch (val)
       {
-      case 0 : itype = M32RBF_INSN_SUBV; goto extract_sfmt_addv;      case 1 : itype = M32RBF_INSN_SUBX; goto extract_sfmt_addx;      case 2 : itype = M32RBF_INSN_SUB; goto extract_sfmt_add;      case 3 : itype = M32RBF_INSN_NEG; goto extract_sfmt_mv;      case 4 : itype = M32RBF_INSN_CMP; goto extract_sfmt_cmp;      case 5 : itype = M32RBF_INSN_CMPU; goto extract_sfmt_cmp;      case 8 : itype = M32RBF_INSN_ADDV; goto extract_sfmt_addv;      case 9 : itype = M32RBF_INSN_ADDX; goto extract_sfmt_addx;      case 10 : itype = M32RBF_INSN_ADD; goto extract_sfmt_add;      case 11 : itype = M32RBF_INSN_NOT; goto extract_sfmt_mv;      case 12 : itype = M32RBF_INSN_AND; goto extract_sfmt_add;      case 13 : itype = M32RBF_INSN_XOR; goto extract_sfmt_add;      case 14 : itype = M32RBF_INSN_OR; goto extract_sfmt_add;      case 16 : itype = M32RBF_INSN_SRL; goto extract_sfmt_add;      case 18 : itype = M32RBF_INSN_SRA; goto extract_sfmt_add;      case 20 : itype = M32RBF_INSN_SLL; goto extract_sfmt_add;      case 22 : itype = M32RBF_INSN_MUL; goto extract_sfmt_add;      case 24 : itype = M32RBF_INSN_MV; goto extract_sfmt_mv;      case 25 : itype = M32RBF_INSN_MVFC; goto extract_sfmt_mvfc;      case 26 : itype = M32RBF_INSN_MVTC; goto extract_sfmt_mvtc;      case 28 :
+      case 0 : itype = M32RBF_INSN_SUBV;goto extract_sfmt_addv;
+      case 1 : itype = M32RBF_INSN_SUBX;goto extract_sfmt_addx;
+      case 2 : itype = M32RBF_INSN_SUB;goto extract_sfmt_add;
+      case 3 : itype = M32RBF_INSN_NEG;goto extract_sfmt_mv;
+      case 4 : itype = M32RBF_INSN_CMP;goto extract_sfmt_cmp;
+      case 5 : itype = M32RBF_INSN_CMPU;goto extract_sfmt_cmp;
+      case 8 : itype = M32RBF_INSN_ADDV;goto extract_sfmt_addv;
+      case 9 : itype = M32RBF_INSN_ADDX;goto extract_sfmt_addx;
+      case 10 : itype = M32RBF_INSN_ADD;goto extract_sfmt_add;
+      case 11 : itype = M32RBF_INSN_NOT;goto extract_sfmt_mv;
+      case 12 : itype = M32RBF_INSN_AND;goto extract_sfmt_add;
+      case 13 : itype = M32RBF_INSN_XOR;goto extract_sfmt_add;
+      case 14 : itype = M32RBF_INSN_OR;goto extract_sfmt_add;
+      case 16 : itype = M32RBF_INSN_SRL;goto extract_sfmt_add;
+      case 18 : itype = M32RBF_INSN_SRA;goto extract_sfmt_add;
+      case 20 : itype = M32RBF_INSN_SLL;goto extract_sfmt_add;
+      case 22 : itype = M32RBF_INSN_MUL;goto extract_sfmt_add;
+      case 24 : itype = M32RBF_INSN_MV;goto extract_sfmt_mv;
+      case 25 : itype = M32RBF_INSN_MVFC;goto extract_sfmt_mvfc;
+      case 26 : itype = M32RBF_INSN_MVTC;goto extract_sfmt_mvtc;
+      case 28 :
         {
           unsigned int val = (((insn >> 8) & (1 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RBF_INSN_JL; goto extract_sfmt_jl;          case 1 : itype = M32RBF_INSN_JMP; goto extract_sfmt_jmp;          default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 0 : itype = M32RBF_INSN_JL;goto extract_sfmt_jl;
+          case 1 : itype = M32RBF_INSN_JMP;goto extract_sfmt_jmp;
+          default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 29 : itype = M32RBF_INSN_RTE; goto extract_sfmt_rte;      case 31 : itype = M32RBF_INSN_TRAP; goto extract_sfmt_trap;      case 32 : itype = M32RBF_INSN_STB; goto extract_sfmt_stb;      case 34 : itype = M32RBF_INSN_STH; goto extract_sfmt_sth;      case 36 : itype = M32RBF_INSN_ST; goto extract_sfmt_st;      case 37 : itype = M32RBF_INSN_UNLOCK; goto extract_sfmt_unlock;      case 38 : itype = M32RBF_INSN_ST_PLUS; goto extract_sfmt_st_plus;      case 39 : itype = M32RBF_INSN_ST_MINUS; goto extract_sfmt_st_plus;      case 40 : itype = M32RBF_INSN_LDB; goto extract_sfmt_ld;      case 41 : itype = M32RBF_INSN_LDUB; goto extract_sfmt_ld;      case 42 : itype = M32RBF_INSN_LDH; goto extract_sfmt_ld;      case 43 : itype = M32RBF_INSN_LDUH; goto extract_sfmt_ld;      case 44 : itype = M32RBF_INSN_LD; goto extract_sfmt_ld;      case 45 : itype = M32RBF_INSN_LOCK; goto extract_sfmt_lock;      case 46 : itype = M32RBF_INSN_LD_PLUS; goto extract_sfmt_ld_plus;      case 48 : itype = M32RBF_INSN_MULHI; goto extract_sfmt_mulhi;      case 49 : itype = M32RBF_INSN_MULLO; goto extract_sfmt_mulhi;      case 50 : itype = M32RBF_INSN_MULWHI; goto extract_sfmt_mulhi;      case 51 : itype = M32RBF_INSN_MULWLO; goto extract_sfmt_mulhi;      case 52 : itype = M32RBF_INSN_MACHI; goto extract_sfmt_machi;      case 53 : itype = M32RBF_INSN_MACLO; goto extract_sfmt_machi;      case 54 : itype = M32RBF_INSN_MACWHI; goto extract_sfmt_machi;      case 55 : itype = M32RBF_INSN_MACWLO; goto extract_sfmt_machi;      case 64 : /* fall through */
+      case 29 : itype = M32RBF_INSN_RTE;goto extract_sfmt_rte;
+      case 31 : itype = M32RBF_INSN_TRAP;goto extract_sfmt_trap;
+      case 32 : itype = M32RBF_INSN_STB;goto extract_sfmt_stb;
+      case 34 : itype = M32RBF_INSN_STH;goto extract_sfmt_sth;
+      case 36 : itype = M32RBF_INSN_ST;goto extract_sfmt_st;
+      case 37 : itype = M32RBF_INSN_UNLOCK;goto extract_sfmt_unlock;
+      case 38 : itype = M32RBF_INSN_ST_PLUS;goto extract_sfmt_st_plus;
+      case 39 : itype = M32RBF_INSN_ST_MINUS;goto extract_sfmt_st_plus;
+      case 40 : itype = M32RBF_INSN_LDB;goto extract_sfmt_ldb;
+      case 41 : itype = M32RBF_INSN_LDUB;goto extract_sfmt_ldb;
+      case 42 : itype = M32RBF_INSN_LDH;goto extract_sfmt_ldh;
+      case 43 : itype = M32RBF_INSN_LDUH;goto extract_sfmt_ldh;
+      case 44 : itype = M32RBF_INSN_LD;goto extract_sfmt_ld;
+      case 45 : itype = M32RBF_INSN_LOCK;goto extract_sfmt_lock;
+      case 46 : itype = M32RBF_INSN_LD_PLUS;goto extract_sfmt_ld_plus;
+      case 48 : itype = M32RBF_INSN_MULHI;goto extract_sfmt_mulhi;
+      case 49 : itype = M32RBF_INSN_MULLO;goto extract_sfmt_mulhi;
+      case 50 : itype = M32RBF_INSN_MULWHI;goto extract_sfmt_mulhi;
+      case 51 : itype = M32RBF_INSN_MULWLO;goto extract_sfmt_mulhi;
+      case 52 : itype = M32RBF_INSN_MACHI;goto extract_sfmt_machi;
+      case 53 : itype = M32RBF_INSN_MACLO;goto extract_sfmt_machi;
+      case 54 : itype = M32RBF_INSN_MACWHI;goto extract_sfmt_machi;
+      case 55 : itype = M32RBF_INSN_MACWLO;goto extract_sfmt_machi;
+      case 64 : /* fall through */
       case 65 : /* fall through */
       case 66 : /* fall through */
       case 67 : /* fall through */
@@ -247,23 +292,34 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 76 : /* fall through */
       case 77 : /* fall through */
       case 78 : /* fall through */
-      case 79 : itype = M32RBF_INSN_ADDI; goto extract_sfmt_addi;      case 80 : /* fall through */
-      case 81 : itype = M32RBF_INSN_SRLI; goto extract_sfmt_slli;      case 82 : /* fall through */
-      case 83 : itype = M32RBF_INSN_SRAI; goto extract_sfmt_slli;      case 84 : /* fall through */
-      case 85 : itype = M32RBF_INSN_SLLI; goto extract_sfmt_slli;      case 87 :
+      case 79 : itype = M32RBF_INSN_ADDI;goto extract_sfmt_addi;
+      case 80 : /* fall through */
+      case 81 : itype = M32RBF_INSN_SRLI;goto extract_sfmt_slli;
+      case 82 : /* fall through */
+      case 83 : itype = M32RBF_INSN_SRAI;goto extract_sfmt_slli;
+      case 84 : /* fall through */
+      case 85 : itype = M32RBF_INSN_SLLI;goto extract_sfmt_slli;
+      case 87 :
         {
           unsigned int val = (((insn >> 0) & (1 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RBF_INSN_MVTACHI; goto extract_sfmt_mvtachi;          case 1 : itype = M32RBF_INSN_MVTACLO; goto extract_sfmt_mvtachi;          default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 0 : itype = M32RBF_INSN_MVTACHI;goto extract_sfmt_mvtachi;
+          case 1 : itype = M32RBF_INSN_MVTACLO;goto extract_sfmt_mvtachi;
+          default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 88 : itype = M32RBF_INSN_RACH; goto extract_sfmt_rac;      case 89 : itype = M32RBF_INSN_RAC; goto extract_sfmt_rac;      case 95 :
+      case 88 : itype = M32RBF_INSN_RACH;goto extract_sfmt_rac;
+      case 89 : itype = M32RBF_INSN_RAC;goto extract_sfmt_rac;
+      case 95 :
         {
           unsigned int val = (((insn >> 0) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RBF_INSN_MVFACHI; goto extract_sfmt_mvfachi;          case 1 : itype = M32RBF_INSN_MVFACLO; goto extract_sfmt_mvfachi;          case 2 : itype = M32RBF_INSN_MVFACMI; goto extract_sfmt_mvfachi;          default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 0 : itype = M32RBF_INSN_MVFACHI;goto extract_sfmt_mvfachi;
+          case 1 : itype = M32RBF_INSN_MVFACLO;goto extract_sfmt_mvfachi;
+          case 2 : itype = M32RBF_INSN_MVFACMI;goto extract_sfmt_mvfachi;
+          default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
       case 96 : /* fall through */
@@ -281,12 +337,18 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 108 : /* fall through */
       case 109 : /* fall through */
       case 110 : /* fall through */
-      case 111 : itype = M32RBF_INSN_LDI8; goto extract_sfmt_ldi8;      case 112 :
+      case 111 : itype = M32RBF_INSN_LDI8;goto extract_sfmt_ldi8;
+      case 112 :
         {
           unsigned int val = (((insn >> 8) & (15 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RBF_INSN_NOP; goto extract_sfmt_nop;          case 12 : itype = M32RBF_INSN_BC8; goto extract_sfmt_bc8;          case 13 : itype = M32RBF_INSN_BNC8; goto extract_sfmt_bc8;          case 14 : itype = M32RBF_INSN_BL8; goto extract_sfmt_bl8;          case 15 : itype = M32RBF_INSN_BRA8; goto extract_sfmt_bra8;          default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 0 : itype = M32RBF_INSN_NOP;goto extract_sfmt_nop;
+          case 12 : itype = M32RBF_INSN_BC8;goto extract_sfmt_bc8;
+          case 13 : itype = M32RBF_INSN_BNC8;goto extract_sfmt_bc8;
+          case 14 : itype = M32RBF_INSN_BL8;goto extract_sfmt_bl8;
+          case 15 : itype = M32RBF_INSN_BRA8;goto extract_sfmt_bra8;
+          default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
       case 113 : /* fall through */
@@ -308,10 +370,46 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 8) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RBF_INSN_BC8; goto extract_sfmt_bc8;          case 1 : itype = M32RBF_INSN_BNC8; goto extract_sfmt_bc8;          case 2 : itype = M32RBF_INSN_BL8; goto extract_sfmt_bl8;          case 3 : itype = M32RBF_INSN_BRA8; goto extract_sfmt_bra8;          default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 0 : itype = M32RBF_INSN_BC8;goto extract_sfmt_bc8;
+          case 1 : itype = M32RBF_INSN_BNC8;goto extract_sfmt_bc8;
+          case 2 : itype = M32RBF_INSN_BL8;goto extract_sfmt_bl8;
+          case 3 : itype = M32RBF_INSN_BRA8;goto extract_sfmt_bra8;
+          default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 132 : itype = M32RBF_INSN_CMPI; goto extract_sfmt_cmpi;      case 133 : itype = M32RBF_INSN_CMPUI; goto extract_sfmt_cmpi;      case 136 : itype = M32RBF_INSN_ADDV3; goto extract_sfmt_addv3;      case 138 : itype = M32RBF_INSN_ADD3; goto extract_sfmt_add3;      case 140 : itype = M32RBF_INSN_AND3; goto extract_sfmt_and3;      case 141 : itype = M32RBF_INSN_XOR3; goto extract_sfmt_and3;      case 142 : itype = M32RBF_INSN_OR3; goto extract_sfmt_or3;      case 144 : itype = M32RBF_INSN_DIV; goto extract_sfmt_div;      case 145 : itype = M32RBF_INSN_DIVU; goto extract_sfmt_div;      case 146 : itype = M32RBF_INSN_REM; goto extract_sfmt_div;      case 147 : itype = M32RBF_INSN_REMU; goto extract_sfmt_div;      case 152 : itype = M32RBF_INSN_SRL3; goto extract_sfmt_sll3;      case 154 : itype = M32RBF_INSN_SRA3; goto extract_sfmt_sll3;      case 156 : itype = M32RBF_INSN_SLL3; goto extract_sfmt_sll3;      case 159 : itype = M32RBF_INSN_LDI16; goto extract_sfmt_ldi16;      case 160 : itype = M32RBF_INSN_STB_D; goto extract_sfmt_stb_d;      case 162 : itype = M32RBF_INSN_STH_D; goto extract_sfmt_sth_d;      case 164 : itype = M32RBF_INSN_ST_D; goto extract_sfmt_st_d;      case 168 : itype = M32RBF_INSN_LDB_D; goto extract_sfmt_ld_d;      case 169 : itype = M32RBF_INSN_LDUB_D; goto extract_sfmt_ld_d;      case 170 : itype = M32RBF_INSN_LDH_D; goto extract_sfmt_ld_d;      case 171 : itype = M32RBF_INSN_LDUH_D; goto extract_sfmt_ld_d;      case 172 : itype = M32RBF_INSN_LD_D; goto extract_sfmt_ld_d;      case 176 : itype = M32RBF_INSN_BEQ; goto extract_sfmt_beq;      case 177 : itype = M32RBF_INSN_BNE; goto extract_sfmt_beq;      case 184 : itype = M32RBF_INSN_BEQZ; goto extract_sfmt_beqz;      case 185 : itype = M32RBF_INSN_BNEZ; goto extract_sfmt_beqz;      case 186 : itype = M32RBF_INSN_BLTZ; goto extract_sfmt_beqz;      case 187 : itype = M32RBF_INSN_BGEZ; goto extract_sfmt_beqz;      case 188 : itype = M32RBF_INSN_BLEZ; goto extract_sfmt_beqz;      case 189 : itype = M32RBF_INSN_BGTZ; goto extract_sfmt_beqz;      case 220 : itype = M32RBF_INSN_SETH; goto extract_sfmt_seth;      case 224 : /* fall through */
+      case 132 : itype = M32RBF_INSN_CMPI;goto extract_sfmt_cmpi;
+      case 133 : itype = M32RBF_INSN_CMPUI;goto extract_sfmt_cmpi;
+      case 136 : itype = M32RBF_INSN_ADDV3;goto extract_sfmt_addv3;
+      case 138 : itype = M32RBF_INSN_ADD3;goto extract_sfmt_add3;
+      case 140 : itype = M32RBF_INSN_AND3;goto extract_sfmt_and3;
+      case 141 : itype = M32RBF_INSN_XOR3;goto extract_sfmt_and3;
+      case 142 : itype = M32RBF_INSN_OR3;goto extract_sfmt_or3;
+      case 144 : itype = M32RBF_INSN_DIV;goto extract_sfmt_div;
+      case 145 : itype = M32RBF_INSN_DIVU;goto extract_sfmt_div;
+      case 146 : itype = M32RBF_INSN_REM;goto extract_sfmt_div;
+      case 147 : itype = M32RBF_INSN_REMU;goto extract_sfmt_div;
+      case 152 : itype = M32RBF_INSN_SRL3;goto extract_sfmt_sll3;
+      case 154 : itype = M32RBF_INSN_SRA3;goto extract_sfmt_sll3;
+      case 156 : itype = M32RBF_INSN_SLL3;goto extract_sfmt_sll3;
+      case 159 : itype = M32RBF_INSN_LDI16;goto extract_sfmt_ldi16;
+      case 160 : itype = M32RBF_INSN_STB_D;goto extract_sfmt_stb_d;
+      case 162 : itype = M32RBF_INSN_STH_D;goto extract_sfmt_sth_d;
+      case 164 : itype = M32RBF_INSN_ST_D;goto extract_sfmt_st_d;
+      case 168 : itype = M32RBF_INSN_LDB_D;goto extract_sfmt_ldb_d;
+      case 169 : itype = M32RBF_INSN_LDUB_D;goto extract_sfmt_ldb_d;
+      case 170 : itype = M32RBF_INSN_LDH_D;goto extract_sfmt_ldh_d;
+      case 171 : itype = M32RBF_INSN_LDUH_D;goto extract_sfmt_ldh_d;
+      case 172 : itype = M32RBF_INSN_LD_D;goto extract_sfmt_ld_d;
+      case 176 : itype = M32RBF_INSN_BEQ;goto extract_sfmt_beq;
+      case 177 : itype = M32RBF_INSN_BNE;goto extract_sfmt_beq;
+      case 184 : itype = M32RBF_INSN_BEQZ;goto extract_sfmt_beqz;
+      case 185 : itype = M32RBF_INSN_BNEZ;goto extract_sfmt_beqz;
+      case 186 : itype = M32RBF_INSN_BLTZ;goto extract_sfmt_beqz;
+      case 187 : itype = M32RBF_INSN_BGEZ;goto extract_sfmt_beqz;
+      case 188 : itype = M32RBF_INSN_BLEZ;goto extract_sfmt_beqz;
+      case 189 : itype = M32RBF_INSN_BGTZ;goto extract_sfmt_beqz;
+      case 220 : itype = M32RBF_INSN_SETH;goto extract_sfmt_seth;
+      case 224 : /* fall through */
       case 225 : /* fall through */
       case 226 : /* fall through */
       case 227 : /* fall through */
@@ -326,7 +424,8 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 236 : /* fall through */
       case 237 : /* fall through */
       case 238 : /* fall through */
-      case 239 : itype = M32RBF_INSN_LD24; goto extract_sfmt_ld24;      case 240 : /* fall through */
+      case 239 : itype = M32RBF_INSN_LD24;goto extract_sfmt_ld24;
+      case 240 : /* fall through */
       case 241 : /* fall through */
       case 242 : /* fall through */
       case 243 : /* fall through */
@@ -346,7 +445,11 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 8) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RBF_INSN_BC24; goto extract_sfmt_bc24;          case 1 : itype = M32RBF_INSN_BNC24; goto extract_sfmt_bc24;          case 2 : itype = M32RBF_INSN_BL24; goto extract_sfmt_bl24;          case 3 : itype = M32RBF_INSN_BRA24; goto extract_sfmt_bra24;          default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 0 : itype = M32RBF_INSN_BC24;goto extract_sfmt_bc24;
+          case 1 : itype = M32RBF_INSN_BNC24;goto extract_sfmt_bc24;
+          case 2 : itype = M32RBF_INSN_BL24;goto extract_sfmt_bl24;
+          case 3 : itype = M32RBF_INSN_BRA24;goto extract_sfmt_bra24;
+          default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
       default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
@@ -747,7 +850,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (out_h_gr_14) = 14;
+      FLD (out_h_gr_SI_14) = 14;
     }
 #endif
 #undef FLD
@@ -771,7 +874,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (out_h_gr_14) = 14;
+      FLD (out_h_gr_SI_14) = 14;
     }
 #endif
 #undef FLD
@@ -932,7 +1035,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
   if (PROFILE_MODEL_P (current_cpu))
     {
       FLD (in_sr) = f_r2;
-      FLD (out_h_gr_14) = 14;
+      FLD (out_h_gr_SI_14) = 14;
     }
 #endif
 #undef FLD
@@ -1027,6 +1130,132 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
+ extract_sfmt_ldb:
+  {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+    UINT f_r1;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = f_r2;
+  FLD (f_r1) = f_r1;
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldb_d:
+  {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add3.f
+    UINT f_r1;
+    UINT f_r2;
+    INT f_simm16;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_simm16) = f_simm16;
+  FLD (f_r2) = f_r2;
+  FLD (f_r1) = f_r1;
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldh:
+  {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+    UINT f_r1;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = f_r2;
+  FLD (f_r1) = f_r1;
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldh_d:
+  {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add3.f
+    UINT f_r1;
+    UINT f_r2;
+    INT f_simm16;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_simm16) = f_simm16;
+  FLD (f_r2) = f_r2;
+  FLD (f_r1) = f_r1;
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
  extract_sfmt_ld_plus:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
diff --git a/sim/m32r/decode.h b/sim/m32r/decode.h
index 2289438..1450667 100644
--- a/sim/m32r/decode.h
+++ b/sim/m32r/decode.h
@@ -2,9 +2,9 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
 
-This file is part of the GNU Simulators.
+This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
@@ -71,6 +71,7 @@ typedef enum m32rbf_sfmt_type {
  , M32RBF_SFMT_BEQZ, M32RBF_SFMT_BL8, M32RBF_SFMT_BL24, M32RBF_SFMT_BRA8
  , M32RBF_SFMT_BRA24, M32RBF_SFMT_CMP, M32RBF_SFMT_CMPI, M32RBF_SFMT_DIV
  , M32RBF_SFMT_JL, M32RBF_SFMT_JMP, M32RBF_SFMT_LD, M32RBF_SFMT_LD_D
+ , M32RBF_SFMT_LDB, M32RBF_SFMT_LDB_D, M32RBF_SFMT_LDH, M32RBF_SFMT_LDH_D
  , M32RBF_SFMT_LD_PLUS, M32RBF_SFMT_LD24, M32RBF_SFMT_LDI8, M32RBF_SFMT_LDI16
  , M32RBF_SFMT_LOCK, M32RBF_SFMT_MACHI, M32RBF_SFMT_MULHI, M32RBF_SFMT_MV
  , M32RBF_SFMT_MVFACHI, M32RBF_SFMT_MVFC, M32RBF_SFMT_MVTACHI, M32RBF_SFMT_MVTC
diff --git a/sim/m32r/decodex.c b/sim/m32r/decodex.c
index 46e3f0f..336ba3a 100644
--- a/sim/m32r/decodex.c
+++ b/sim/m32r/decodex.c
@@ -2,9 +2,9 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
 
-This file is part of the GNU Simulators.
+This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
@@ -37,7 +37,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
    teensy bit of cpu in the decoder.  Moving it to malloc space is trivial
    but won't be done until necessary (we don't currently support the runtime
    addition of instructions nor an SMP machine with different cpus).  */
-static IDESC m32rxf_insn_data[M32RXF_INSN_MAX];
+static IDESC m32rxf_insn_data[M32RXF_INSN_SNC + 1];
 
 /* Commas between elements are contained in the macros.
    Some of these are conditionally compiled out.  */
@@ -99,14 +99,14 @@ static const struct insn_sem m32rxf_insn_sem[] =
   { M32R_INSN_JMP, M32RXF_INSN_JMP, M32RXF_SFMT_JMP, M32RXF_INSN_PAR_JMP, M32RXF_INSN_WRITE_JMP },
   { M32R_INSN_LD, M32RXF_INSN_LD, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LD, M32RXF_INSN_WRITE_LD },
   { M32R_INSN_LD_D, M32RXF_INSN_LD_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR  },
-  { M32R_INSN_LDB, M32RXF_INSN_LDB, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LDB, M32RXF_INSN_WRITE_LDB },
-  { M32R_INSN_LDB_D, M32RXF_INSN_LDB_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR  },
-  { M32R_INSN_LDH, M32RXF_INSN_LDH, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LDH, M32RXF_INSN_WRITE_LDH },
-  { M32R_INSN_LDH_D, M32RXF_INSN_LDH_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR  },
-  { M32R_INSN_LDUB, M32RXF_INSN_LDUB, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LDUB, M32RXF_INSN_WRITE_LDUB },
-  { M32R_INSN_LDUB_D, M32RXF_INSN_LDUB_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR  },
-  { M32R_INSN_LDUH, M32RXF_INSN_LDUH, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LDUH, M32RXF_INSN_WRITE_LDUH },
-  { M32R_INSN_LDUH_D, M32RXF_INSN_LDUH_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR  },
+  { M32R_INSN_LDB, M32RXF_INSN_LDB, M32RXF_SFMT_LDB, M32RXF_INSN_PAR_LDB, M32RXF_INSN_WRITE_LDB },
+  { M32R_INSN_LDB_D, M32RXF_INSN_LDB_D, M32RXF_SFMT_LDB_D, NOPAR, NOPAR  },
+  { M32R_INSN_LDH, M32RXF_INSN_LDH, M32RXF_SFMT_LDH, M32RXF_INSN_PAR_LDH, M32RXF_INSN_WRITE_LDH },
+  { M32R_INSN_LDH_D, M32RXF_INSN_LDH_D, M32RXF_SFMT_LDH_D, NOPAR, NOPAR  },
+  { M32R_INSN_LDUB, M32RXF_INSN_LDUB, M32RXF_SFMT_LDB, M32RXF_INSN_PAR_LDUB, M32RXF_INSN_WRITE_LDUB },
+  { M32R_INSN_LDUB_D, M32RXF_INSN_LDUB_D, M32RXF_SFMT_LDB_D, NOPAR, NOPAR  },
+  { M32R_INSN_LDUH, M32RXF_INSN_LDUH, M32RXF_SFMT_LDH, M32RXF_INSN_PAR_LDUH, M32RXF_INSN_WRITE_LDUH },
+  { M32R_INSN_LDUH_D, M32RXF_INSN_LDUH_D, M32RXF_SFMT_LDH_D, NOPAR, NOPAR  },
   { M32R_INSN_LD_PLUS, M32RXF_INSN_LD_PLUS, M32RXF_SFMT_LD_PLUS, M32RXF_INSN_PAR_LD_PLUS, M32RXF_INSN_WRITE_LD_PLUS },
   { M32R_INSN_LD24, M32RXF_INSN_LD24, M32RXF_SFMT_LD24, NOPAR, NOPAR  },
   { M32R_INSN_LDI8, M32RXF_INSN_LDI8, M32RXF_SFMT_LDI8, M32RXF_INSN_PAR_LDI8, M32RXF_INSN_WRITE_LDI8 },
@@ -210,7 +210,7 @@ m32rxf_init_idesc_table (SIM_CPU *cpu)
 {
   IDESC *id,*tabend;
   const struct insn_sem *t,*tend;
-  int tabsize = M32RXF_INSN_MAX;
+  int tabsize = sizeof (m32rxf_insn_data) / sizeof (IDESC);
   IDESC *table = m32rxf_insn_data;
 
   memset (table, 0, tabsize * sizeof (IDESC));
@@ -258,31 +258,81 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
       unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
       switch (val)
       {
-      case 0 : itype = M32RXF_INSN_SUBV; goto extract_sfmt_addv;      case 1 : itype = M32RXF_INSN_SUBX; goto extract_sfmt_addx;      case 2 : itype = M32RXF_INSN_SUB; goto extract_sfmt_add;      case 3 : itype = M32RXF_INSN_NEG; goto extract_sfmt_mv;      case 4 : itype = M32RXF_INSN_CMP; goto extract_sfmt_cmp;      case 5 : itype = M32RXF_INSN_CMPU; goto extract_sfmt_cmp;      case 6 : itype = M32RXF_INSN_CMPEQ; goto extract_sfmt_cmp;      case 7 :
+      case 0 : itype = M32RXF_INSN_SUBV;goto extract_sfmt_addv;
+      case 1 : itype = M32RXF_INSN_SUBX;goto extract_sfmt_addx;
+      case 2 : itype = M32RXF_INSN_SUB;goto extract_sfmt_add;
+      case 3 : itype = M32RXF_INSN_NEG;goto extract_sfmt_mv;
+      case 4 : itype = M32RXF_INSN_CMP;goto extract_sfmt_cmp;
+      case 5 : itype = M32RXF_INSN_CMPU;goto extract_sfmt_cmp;
+      case 6 : itype = M32RXF_INSN_CMPEQ;goto extract_sfmt_cmp;
+      case 7 :
         {
           unsigned int val = (((insn >> 8) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RXF_INSN_CMPZ; goto extract_sfmt_cmpz;          case 3 : itype = M32RXF_INSN_PCMPBZ; goto extract_sfmt_cmpz;          default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 0 : itype = M32RXF_INSN_CMPZ;goto extract_sfmt_cmpz;
+          case 3 : itype = M32RXF_INSN_PCMPBZ;goto extract_sfmt_cmpz;
+          default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 8 : itype = M32RXF_INSN_ADDV; goto extract_sfmt_addv;      case 9 : itype = M32RXF_INSN_ADDX; goto extract_sfmt_addx;      case 10 : itype = M32RXF_INSN_ADD; goto extract_sfmt_add;      case 11 : itype = M32RXF_INSN_NOT; goto extract_sfmt_mv;      case 12 : itype = M32RXF_INSN_AND; goto extract_sfmt_add;      case 13 : itype = M32RXF_INSN_XOR; goto extract_sfmt_add;      case 14 : itype = M32RXF_INSN_OR; goto extract_sfmt_add;      case 16 : itype = M32RXF_INSN_SRL; goto extract_sfmt_add;      case 18 : itype = M32RXF_INSN_SRA; goto extract_sfmt_add;      case 20 : itype = M32RXF_INSN_SLL; goto extract_sfmt_add;      case 22 : itype = M32RXF_INSN_MUL; goto extract_sfmt_add;      case 24 : itype = M32RXF_INSN_MV; goto extract_sfmt_mv;      case 25 : itype = M32RXF_INSN_MVFC; goto extract_sfmt_mvfc;      case 26 : itype = M32RXF_INSN_MVTC; goto extract_sfmt_mvtc;      case 28 :
+      case 8 : itype = M32RXF_INSN_ADDV;goto extract_sfmt_addv;
+      case 9 : itype = M32RXF_INSN_ADDX;goto extract_sfmt_addx;
+      case 10 : itype = M32RXF_INSN_ADD;goto extract_sfmt_add;
+      case 11 : itype = M32RXF_INSN_NOT;goto extract_sfmt_mv;
+      case 12 : itype = M32RXF_INSN_AND;goto extract_sfmt_add;
+      case 13 : itype = M32RXF_INSN_XOR;goto extract_sfmt_add;
+      case 14 : itype = M32RXF_INSN_OR;goto extract_sfmt_add;
+      case 16 : itype = M32RXF_INSN_SRL;goto extract_sfmt_add;
+      case 18 : itype = M32RXF_INSN_SRA;goto extract_sfmt_add;
+      case 20 : itype = M32RXF_INSN_SLL;goto extract_sfmt_add;
+      case 22 : itype = M32RXF_INSN_MUL;goto extract_sfmt_add;
+      case 24 : itype = M32RXF_INSN_MV;goto extract_sfmt_mv;
+      case 25 : itype = M32RXF_INSN_MVFC;goto extract_sfmt_mvfc;
+      case 26 : itype = M32RXF_INSN_MVTC;goto extract_sfmt_mvtc;
+      case 28 :
         {
           unsigned int val = (((insn >> 8) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RXF_INSN_JC; goto extract_sfmt_jc;          case 1 : itype = M32RXF_INSN_JNC; goto extract_sfmt_jc;          case 2 : itype = M32RXF_INSN_JL; goto extract_sfmt_jl;          case 3 : itype = M32RXF_INSN_JMP; goto extract_sfmt_jmp;          default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 0 : itype = M32RXF_INSN_JC;goto extract_sfmt_jc;
+          case 1 : itype = M32RXF_INSN_JNC;goto extract_sfmt_jc;
+          case 2 : itype = M32RXF_INSN_JL;goto extract_sfmt_jl;
+          case 3 : itype = M32RXF_INSN_JMP;goto extract_sfmt_jmp;
+          default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 29 : itype = M32RXF_INSN_RTE; goto extract_sfmt_rte;      case 31 : itype = M32RXF_INSN_TRAP; goto extract_sfmt_trap;      case 32 : itype = M32RXF_INSN_STB; goto extract_sfmt_stb;      case 34 : itype = M32RXF_INSN_STH; goto extract_sfmt_sth;      case 36 : itype = M32RXF_INSN_ST; goto extract_sfmt_st;      case 37 : itype = M32RXF_INSN_UNLOCK; goto extract_sfmt_unlock;      case 38 : itype = M32RXF_INSN_ST_PLUS; goto extract_sfmt_st_plus;      case 39 : itype = M32RXF_INSN_ST_MINUS; goto extract_sfmt_st_plus;      case 40 : itype = M32RXF_INSN_LDB; goto extract_sfmt_ld;      case 41 : itype = M32RXF_INSN_LDUB; goto extract_sfmt_ld;      case 42 : itype = M32RXF_INSN_LDH; goto extract_sfmt_ld;      case 43 : itype = M32RXF_INSN_LDUH; goto extract_sfmt_ld;      case 44 : itype = M32RXF_INSN_LD; goto extract_sfmt_ld;      case 45 : itype = M32RXF_INSN_LOCK; goto extract_sfmt_lock;      case 46 : itype = M32RXF_INSN_LD_PLUS; goto extract_sfmt_ld_plus;      case 48 : /* fall through */
-      case 56 : itype = M32RXF_INSN_MULHI_A; goto extract_sfmt_mulhi_a;      case 49 : /* fall through */
-      case 57 : itype = M32RXF_INSN_MULLO_A; goto extract_sfmt_mulhi_a;      case 50 : /* fall through */
-      case 58 : itype = M32RXF_INSN_MULWHI_A; goto extract_sfmt_mulhi_a;      case 51 : /* fall through */
-      case 59 : itype = M32RXF_INSN_MULWLO_A; goto extract_sfmt_mulhi_a;      case 52 : /* fall through */
-      case 60 : itype = M32RXF_INSN_MACHI_A; goto extract_sfmt_machi_a;      case 53 : /* fall through */
-      case 61 : itype = M32RXF_INSN_MACLO_A; goto extract_sfmt_machi_a;      case 54 : /* fall through */
-      case 62 : itype = M32RXF_INSN_MACWHI_A; goto extract_sfmt_machi_a;      case 55 : /* fall through */
-      case 63 : itype = M32RXF_INSN_MACWLO_A; goto extract_sfmt_machi_a;      case 64 : /* fall through */
+      case 29 : itype = M32RXF_INSN_RTE;goto extract_sfmt_rte;
+      case 31 : itype = M32RXF_INSN_TRAP;goto extract_sfmt_trap;
+      case 32 : itype = M32RXF_INSN_STB;goto extract_sfmt_stb;
+      case 34 : itype = M32RXF_INSN_STH;goto extract_sfmt_sth;
+      case 36 : itype = M32RXF_INSN_ST;goto extract_sfmt_st;
+      case 37 : itype = M32RXF_INSN_UNLOCK;goto extract_sfmt_unlock;
+      case 38 : itype = M32RXF_INSN_ST_PLUS;goto extract_sfmt_st_plus;
+      case 39 : itype = M32RXF_INSN_ST_MINUS;goto extract_sfmt_st_plus;
+      case 40 : itype = M32RXF_INSN_LDB;goto extract_sfmt_ldb;
+      case 41 : itype = M32RXF_INSN_LDUB;goto extract_sfmt_ldb;
+      case 42 : itype = M32RXF_INSN_LDH;goto extract_sfmt_ldh;
+      case 43 : itype = M32RXF_INSN_LDUH;goto extract_sfmt_ldh;
+      case 44 : itype = M32RXF_INSN_LD;goto extract_sfmt_ld;
+      case 45 : itype = M32RXF_INSN_LOCK;goto extract_sfmt_lock;
+      case 46 : itype = M32RXF_INSN_LD_PLUS;goto extract_sfmt_ld_plus;
+      case 48 : /* fall through */
+      case 56 : itype = M32RXF_INSN_MULHI_A;goto extract_sfmt_mulhi_a;
+      case 49 : /* fall through */
+      case 57 : itype = M32RXF_INSN_MULLO_A;goto extract_sfmt_mulhi_a;
+      case 50 : /* fall through */
+      case 58 : itype = M32RXF_INSN_MULWHI_A;goto extract_sfmt_mulhi_a;
+      case 51 : /* fall through */
+      case 59 : itype = M32RXF_INSN_MULWLO_A;goto extract_sfmt_mulhi_a;
+      case 52 : /* fall through */
+      case 60 : itype = M32RXF_INSN_MACHI_A;goto extract_sfmt_machi_a;
+      case 53 : /* fall through */
+      case 61 : itype = M32RXF_INSN_MACLO_A;goto extract_sfmt_machi_a;
+      case 54 : /* fall through */
+      case 62 : itype = M32RXF_INSN_MACWHI_A;goto extract_sfmt_machi_a;
+      case 55 : /* fall through */
+      case 63 : itype = M32RXF_INSN_MACWLO_A;goto extract_sfmt_machi_a;
+      case 64 : /* fall through */
       case 65 : /* fall through */
       case 66 : /* fall through */
       case 67 : /* fall through */
@@ -297,23 +347,39 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 76 : /* fall through */
       case 77 : /* fall through */
       case 78 : /* fall through */
-      case 79 : itype = M32RXF_INSN_ADDI; goto extract_sfmt_addi;      case 80 : /* fall through */
-      case 81 : itype = M32RXF_INSN_SRLI; goto extract_sfmt_slli;      case 82 : /* fall through */
-      case 83 : itype = M32RXF_INSN_SRAI; goto extract_sfmt_slli;      case 84 : /* fall through */
-      case 85 : itype = M32RXF_INSN_SLLI; goto extract_sfmt_slli;      case 87 :
+      case 79 : itype = M32RXF_INSN_ADDI;goto extract_sfmt_addi;
+      case 80 : /* fall through */
+      case 81 : itype = M32RXF_INSN_SRLI;goto extract_sfmt_slli;
+      case 82 : /* fall through */
+      case 83 : itype = M32RXF_INSN_SRAI;goto extract_sfmt_slli;
+      case 84 : /* fall through */
+      case 85 : itype = M32RXF_INSN_SLLI;goto extract_sfmt_slli;
+      case 87 :
         {
           unsigned int val = (((insn >> 0) & (1 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RXF_INSN_MVTACHI_A; goto extract_sfmt_mvtachi_a;          case 1 : itype = M32RXF_INSN_MVTACLO_A; goto extract_sfmt_mvtachi_a;          default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 0 : itype = M32RXF_INSN_MVTACHI_A;goto extract_sfmt_mvtachi_a;
+          case 1 : itype = M32RXF_INSN_MVTACLO_A;goto extract_sfmt_mvtachi_a;
+          default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 88 : itype = M32RXF_INSN_RACH_DSI; goto extract_sfmt_rac_dsi;      case 89 : itype = M32RXF_INSN_RAC_DSI; goto extract_sfmt_rac_dsi;      case 90 : itype = M32RXF_INSN_MULWU1; goto extract_sfmt_mulwu1;      case 91 : itype = M32RXF_INSN_MACWU1; goto extract_sfmt_macwu1;      case 92 : itype = M32RXF_INSN_MACLH1; goto extract_sfmt_macwu1;      case 93 : itype = M32RXF_INSN_MSBLO; goto extract_sfmt_msblo;      case 94 : itype = M32RXF_INSN_SADD; goto extract_sfmt_sadd;      case 95 :
+      case 88 : itype = M32RXF_INSN_RACH_DSI;goto extract_sfmt_rac_dsi;
+      case 89 : itype = M32RXF_INSN_RAC_DSI;goto extract_sfmt_rac_dsi;
+      case 90 : itype = M32RXF_INSN_MULWU1;goto extract_sfmt_mulwu1;
+      case 91 : itype = M32RXF_INSN_MACWU1;goto extract_sfmt_macwu1;
+      case 92 : itype = M32RXF_INSN_MACLH1;goto extract_sfmt_macwu1;
+      case 93 : itype = M32RXF_INSN_MSBLO;goto extract_sfmt_msblo;
+      case 94 : itype = M32RXF_INSN_SADD;goto extract_sfmt_sadd;
+      case 95 :
         {
           unsigned int val = (((insn >> 0) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RXF_INSN_MVFACHI_A; goto extract_sfmt_mvfachi_a;          case 1 : itype = M32RXF_INSN_MVFACLO_A; goto extract_sfmt_mvfachi_a;          case 2 : itype = M32RXF_INSN_MVFACMI_A; goto extract_sfmt_mvfachi_a;          default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 0 : itype = M32RXF_INSN_MVFACHI_A;goto extract_sfmt_mvfachi_a;
+          case 1 : itype = M32RXF_INSN_MVFACLO_A;goto extract_sfmt_mvfachi_a;
+          case 2 : itype = M32RXF_INSN_MVFACMI_A;goto extract_sfmt_mvfachi_a;
+          default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
       case 96 : /* fall through */
@@ -331,12 +397,22 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 108 : /* fall through */
       case 109 : /* fall through */
       case 110 : /* fall through */
-      case 111 : itype = M32RXF_INSN_LDI8; goto extract_sfmt_ldi8;      case 112 :
+      case 111 : itype = M32RXF_INSN_LDI8;goto extract_sfmt_ldi8;
+      case 112 :
         {
           unsigned int val = (((insn >> 8) & (15 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RXF_INSN_NOP; goto extract_sfmt_nop;          case 4 : itype = M32RXF_INSN_SC; goto extract_sfmt_sc;          case 5 : itype = M32RXF_INSN_SNC; goto extract_sfmt_sc;          case 8 : itype = M32RXF_INSN_BCL8; goto extract_sfmt_bcl8;          case 9 : itype = M32RXF_INSN_BNCL8; goto extract_sfmt_bcl8;          case 12 : itype = M32RXF_INSN_BC8; goto extract_sfmt_bc8;          case 13 : itype = M32RXF_INSN_BNC8; goto extract_sfmt_bc8;          case 14 : itype = M32RXF_INSN_BL8; goto extract_sfmt_bl8;          case 15 : itype = M32RXF_INSN_BRA8; goto extract_sfmt_bra8;          default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 0 : itype = M32RXF_INSN_NOP;goto extract_sfmt_nop;
+          case 4 : itype = M32RXF_INSN_SC;goto extract_sfmt_sc;
+          case 5 : itype = M32RXF_INSN_SNC;goto extract_sfmt_sc;
+          case 8 : itype = M32RXF_INSN_BCL8;goto extract_sfmt_bcl8;
+          case 9 : itype = M32RXF_INSN_BNCL8;goto extract_sfmt_bcl8;
+          case 12 : itype = M32RXF_INSN_BC8;goto extract_sfmt_bc8;
+          case 13 : itype = M32RXF_INSN_BNC8;goto extract_sfmt_bc8;
+          case 14 : itype = M32RXF_INSN_BL8;goto extract_sfmt_bl8;
+          case 15 : itype = M32RXF_INSN_BRA8;goto extract_sfmt_bra8;
+          default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
       case 113 : /* fall through */
@@ -358,26 +434,68 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 8) & (7 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RXF_INSN_BCL8; goto extract_sfmt_bcl8;          case 1 : itype = M32RXF_INSN_BNCL8; goto extract_sfmt_bcl8;          case 4 : itype = M32RXF_INSN_BC8; goto extract_sfmt_bc8;          case 5 : itype = M32RXF_INSN_BNC8; goto extract_sfmt_bc8;          case 6 : itype = M32RXF_INSN_BL8; goto extract_sfmt_bl8;          case 7 : itype = M32RXF_INSN_BRA8; goto extract_sfmt_bra8;          default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 0 : itype = M32RXF_INSN_BCL8;goto extract_sfmt_bcl8;
+          case 1 : itype = M32RXF_INSN_BNCL8;goto extract_sfmt_bcl8;
+          case 4 : itype = M32RXF_INSN_BC8;goto extract_sfmt_bc8;
+          case 5 : itype = M32RXF_INSN_BNC8;goto extract_sfmt_bc8;
+          case 6 : itype = M32RXF_INSN_BL8;goto extract_sfmt_bl8;
+          case 7 : itype = M32RXF_INSN_BRA8;goto extract_sfmt_bra8;
+          default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 132 : itype = M32RXF_INSN_CMPI; goto extract_sfmt_cmpi;      case 133 : itype = M32RXF_INSN_CMPUI; goto extract_sfmt_cmpi;      case 134 :
+      case 132 : itype = M32RXF_INSN_CMPI;goto extract_sfmt_cmpi;
+      case 133 : itype = M32RXF_INSN_CMPUI;goto extract_sfmt_cmpi;
+      case 134 :
         {
           unsigned int val = (((insn >> -8) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RXF_INSN_SAT; goto extract_sfmt_sat;          case 2 : itype = M32RXF_INSN_SATH; goto extract_sfmt_satb;          case 3 : itype = M32RXF_INSN_SATB; goto extract_sfmt_satb;          default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 0 : itype = M32RXF_INSN_SAT;goto extract_sfmt_sat;
+          case 2 : itype = M32RXF_INSN_SATH;goto extract_sfmt_satb;
+          case 3 : itype = M32RXF_INSN_SATB;goto extract_sfmt_satb;
+          default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 136 : itype = M32RXF_INSN_ADDV3; goto extract_sfmt_addv3;      case 138 : itype = M32RXF_INSN_ADD3; goto extract_sfmt_add3;      case 140 : itype = M32RXF_INSN_AND3; goto extract_sfmt_and3;      case 141 : itype = M32RXF_INSN_XOR3; goto extract_sfmt_and3;      case 142 : itype = M32RXF_INSN_OR3; goto extract_sfmt_or3;      case 144 :
+      case 136 : itype = M32RXF_INSN_ADDV3;goto extract_sfmt_addv3;
+      case 138 : itype = M32RXF_INSN_ADD3;goto extract_sfmt_add3;
+      case 140 : itype = M32RXF_INSN_AND3;goto extract_sfmt_and3;
+      case 141 : itype = M32RXF_INSN_XOR3;goto extract_sfmt_and3;
+      case 142 : itype = M32RXF_INSN_OR3;goto extract_sfmt_or3;
+      case 144 :
         {
           unsigned int val = (((insn >> -12) & (1 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RXF_INSN_DIV; goto extract_sfmt_div;          case 1 : itype = M32RXF_INSN_DIVH; goto extract_sfmt_div;          default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 0 : itype = M32RXF_INSN_DIV;goto extract_sfmt_div;
+          case 1 : itype = M32RXF_INSN_DIVH;goto extract_sfmt_div;
+          default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 145 : itype = M32RXF_INSN_DIVU; goto extract_sfmt_div;      case 146 : itype = M32RXF_INSN_REM; goto extract_sfmt_div;      case 147 : itype = M32RXF_INSN_REMU; goto extract_sfmt_div;      case 152 : itype = M32RXF_INSN_SRL3; goto extract_sfmt_sll3;      case 154 : itype = M32RXF_INSN_SRA3; goto extract_sfmt_sll3;      case 156 : itype = M32RXF_INSN_SLL3; goto extract_sfmt_sll3;      case 159 : itype = M32RXF_INSN_LDI16; goto extract_sfmt_ldi16;      case 160 : itype = M32RXF_INSN_STB_D; goto extract_sfmt_stb_d;      case 162 : itype = M32RXF_INSN_STH_D; goto extract_sfmt_sth_d;      case 164 : itype = M32RXF_INSN_ST_D; goto extract_sfmt_st_d;      case 168 : itype = M32RXF_INSN_LDB_D; goto extract_sfmt_ld_d;      case 169 : itype = M32RXF_INSN_LDUB_D; goto extract_sfmt_ld_d;      case 170 : itype = M32RXF_INSN_LDH_D; goto extract_sfmt_ld_d;      case 171 : itype = M32RXF_INSN_LDUH_D; goto extract_sfmt_ld_d;      case 172 : itype = M32RXF_INSN_LD_D; goto extract_sfmt_ld_d;      case 176 : itype = M32RXF_INSN_BEQ; goto extract_sfmt_beq;      case 177 : itype = M32RXF_INSN_BNE; goto extract_sfmt_beq;      case 184 : itype = M32RXF_INSN_BEQZ; goto extract_sfmt_beqz;      case 185 : itype = M32RXF_INSN_BNEZ; goto extract_sfmt_beqz;      case 186 : itype = M32RXF_INSN_BLTZ; goto extract_sfmt_beqz;      case 187 : itype = M32RXF_INSN_BGEZ; goto extract_sfmt_beqz;      case 188 : itype = M32RXF_INSN_BLEZ; goto extract_sfmt_beqz;      case 189 : itype = M32RXF_INSN_BGTZ; goto extract_sfmt_beqz;      case 220 : itype = M32RXF_INSN_SETH; goto extract_sfmt_seth;      case 224 : /* fall through */
+      case 145 : itype = M32RXF_INSN_DIVU;goto extract_sfmt_div;
+      case 146 : itype = M32RXF_INSN_REM;goto extract_sfmt_div;
+      case 147 : itype = M32RXF_INSN_REMU;goto extract_sfmt_div;
+      case 152 : itype = M32RXF_INSN_SRL3;goto extract_sfmt_sll3;
+      case 154 : itype = M32RXF_INSN_SRA3;goto extract_sfmt_sll3;
+      case 156 : itype = M32RXF_INSN_SLL3;goto extract_sfmt_sll3;
+      case 159 : itype = M32RXF_INSN_LDI16;goto extract_sfmt_ldi16;
+      case 160 : itype = M32RXF_INSN_STB_D;goto extract_sfmt_stb_d;
+      case 162 : itype = M32RXF_INSN_STH_D;goto extract_sfmt_sth_d;
+      case 164 : itype = M32RXF_INSN_ST_D;goto extract_sfmt_st_d;
+      case 168 : itype = M32RXF_INSN_LDB_D;goto extract_sfmt_ldb_d;
+      case 169 : itype = M32RXF_INSN_LDUB_D;goto extract_sfmt_ldb_d;
+      case 170 : itype = M32RXF_INSN_LDH_D;goto extract_sfmt_ldh_d;
+      case 171 : itype = M32RXF_INSN_LDUH_D;goto extract_sfmt_ldh_d;
+      case 172 : itype = M32RXF_INSN_LD_D;goto extract_sfmt_ld_d;
+      case 176 : itype = M32RXF_INSN_BEQ;goto extract_sfmt_beq;
+      case 177 : itype = M32RXF_INSN_BNE;goto extract_sfmt_beq;
+      case 184 : itype = M32RXF_INSN_BEQZ;goto extract_sfmt_beqz;
+      case 185 : itype = M32RXF_INSN_BNEZ;goto extract_sfmt_beqz;
+      case 186 : itype = M32RXF_INSN_BLTZ;goto extract_sfmt_beqz;
+      case 187 : itype = M32RXF_INSN_BGEZ;goto extract_sfmt_beqz;
+      case 188 : itype = M32RXF_INSN_BLEZ;goto extract_sfmt_beqz;
+      case 189 : itype = M32RXF_INSN_BGTZ;goto extract_sfmt_beqz;
+      case 220 : itype = M32RXF_INSN_SETH;goto extract_sfmt_seth;
+      case 224 : /* fall through */
       case 225 : /* fall through */
       case 226 : /* fall through */
       case 227 : /* fall through */
@@ -392,7 +510,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 236 : /* fall through */
       case 237 : /* fall through */
       case 238 : /* fall through */
-      case 239 : itype = M32RXF_INSN_LD24; goto extract_sfmt_ld24;      case 240 : /* fall through */
+      case 239 : itype = M32RXF_INSN_LD24;goto extract_sfmt_ld24;
+      case 240 : /* fall through */
       case 241 : /* fall through */
       case 242 : /* fall through */
       case 243 : /* fall through */
@@ -412,7 +531,13 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 8) & (7 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RXF_INSN_BCL24; goto extract_sfmt_bcl24;          case 1 : itype = M32RXF_INSN_BNCL24; goto extract_sfmt_bcl24;          case 4 : itype = M32RXF_INSN_BC24; goto extract_sfmt_bc24;          case 5 : itype = M32RXF_INSN_BNC24; goto extract_sfmt_bc24;          case 6 : itype = M32RXF_INSN_BL24; goto extract_sfmt_bl24;          case 7 : itype = M32RXF_INSN_BRA24; goto extract_sfmt_bra24;          default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 0 : itype = M32RXF_INSN_BCL24;goto extract_sfmt_bcl24;
+          case 1 : itype = M32RXF_INSN_BNCL24;goto extract_sfmt_bcl24;
+          case 4 : itype = M32RXF_INSN_BC24;goto extract_sfmt_bc24;
+          case 5 : itype = M32RXF_INSN_BNC24;goto extract_sfmt_bc24;
+          case 6 : itype = M32RXF_INSN_BL24;goto extract_sfmt_bl24;
+          case 7 : itype = M32RXF_INSN_BRA24;goto extract_sfmt_bra24;
+          default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
       default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
@@ -813,7 +938,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (out_h_gr_14) = 14;
+      FLD (out_h_gr_SI_14) = 14;
     }
 #endif
 #undef FLD
@@ -837,7 +962,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (out_h_gr_14) = 14;
+      FLD (out_h_gr_SI_14) = 14;
     }
 #endif
 #undef FLD
@@ -861,7 +986,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (out_h_gr_14) = 14;
+      FLD (out_h_gr_SI_14) = 14;
     }
 #endif
 #undef FLD
@@ -885,7 +1010,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (out_h_gr_14) = 14;
+      FLD (out_h_gr_SI_14) = 14;
     }
 #endif
 #undef FLD
@@ -1096,7 +1221,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   if (PROFILE_MODEL_P (current_cpu))
     {
       FLD (in_sr) = f_r2;
-      FLD (out_h_gr_14) = 14;
+      FLD (out_h_gr_SI_14) = 14;
     }
 #endif
 #undef FLD
@@ -1191,6 +1316,132 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
+ extract_sfmt_ldb:
+  {
+    const IDESC *idesc = &m32rxf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+    UINT f_r1;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = f_r2;
+  FLD (f_r1) = f_r1;
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldb_d:
+  {
+    const IDESC *idesc = &m32rxf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add3.f
+    UINT f_r1;
+    UINT f_r2;
+    INT f_simm16;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_simm16) = f_simm16;
+  FLD (f_r2) = f_r2;
+  FLD (f_r1) = f_r1;
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldh:
+  {
+    const IDESC *idesc = &m32rxf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+    UINT f_r1;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = f_r2;
+  FLD (f_r1) = f_r1;
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldh_d:
+  {
+    const IDESC *idesc = &m32rxf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add3.f
+    UINT f_r1;
+    UINT f_r2;
+    INT f_simm16;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_simm16) = f_simm16;
+  FLD (f_r2) = f_r2;
+  FLD (f_r1) = f_r1;
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
  extract_sfmt_ld_plus:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
diff --git a/sim/m32r/decodex.h b/sim/m32r/decodex.h
index 5415e77..6394f03 100644
--- a/sim/m32r/decodex.h
+++ b/sim/m32r/decodex.h
@@ -2,9 +2,9 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
 
-This file is part of the GNU Simulators.
+This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
@@ -115,6 +115,7 @@ typedef enum m32rxf_sfmt_type {
  , M32RXF_SFMT_BCL24, M32RXF_SFMT_BRA8, M32RXF_SFMT_BRA24, M32RXF_SFMT_CMP
  , M32RXF_SFMT_CMPI, M32RXF_SFMT_CMPZ, M32RXF_SFMT_DIV, M32RXF_SFMT_JC
  , M32RXF_SFMT_JL, M32RXF_SFMT_JMP, M32RXF_SFMT_LD, M32RXF_SFMT_LD_D
+ , M32RXF_SFMT_LDB, M32RXF_SFMT_LDB_D, M32RXF_SFMT_LDH, M32RXF_SFMT_LDH_D
  , M32RXF_SFMT_LD_PLUS, M32RXF_SFMT_LD24, M32RXF_SFMT_LDI8, M32RXF_SFMT_LDI16
  , M32RXF_SFMT_LOCK, M32RXF_SFMT_MACHI_A, M32RXF_SFMT_MULHI_A, M32RXF_SFMT_MV
  , M32RXF_SFMT_MVFACHI_A, M32RXF_SFMT_MVFC, M32RXF_SFMT_MVTACHI_A, M32RXF_SFMT_MVTC
diff --git a/sim/m32r/model.c b/sim/m32r/model.c
index 87485ba..419e581 100644
--- a/sim/m32r/model.c
+++ b/sim/m32r/model.c
@@ -2,9 +2,9 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
 
-This file is part of the GNU Simulators.
+This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
@@ -4148,7 +4148,7 @@ m32r_init_cpu (SIM_CPU *cpu)
   CPU_PC_FETCH (cpu) = m32rbf_h_pc_get;
   CPU_PC_STORE (cpu) = m32rbf_h_pc_set;
   CPU_GET_IDATA (cpu) = m32rbf_get_idata;
-  CPU_MAX_INSNS (cpu) = M32RBF_INSN_MAX;
+  CPU_MAX_INSNS (cpu) = M32RBF_INSN_UNLOCK + 1;
   CPU_INSN_NAME (cpu) = cgen_insn_name;
   CPU_FULL_ENGINE_FN (cpu) = m32rbf_engine_run_full;
 #if WITH_FAST
diff --git a/sim/m32r/modelx.c b/sim/m32r/modelx.c
index 464ab1f..bdcb93a 100644
--- a/sim/m32r/modelx.c
+++ b/sim/m32r/modelx.c
@@ -2,9 +2,9 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
 
-This file is part of the GNU Simulators.
+This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
@@ -2879,7 +2879,7 @@ m32rx_init_cpu (SIM_CPU *cpu)
   CPU_PC_FETCH (cpu) = m32rxf_h_pc_get;
   CPU_PC_STORE (cpu) = m32rxf_h_pc_set;
   CPU_GET_IDATA (cpu) = m32rxf_get_idata;
-  CPU_MAX_INSNS (cpu) = M32RXF_INSN_MAX;
+  CPU_MAX_INSNS (cpu) = M32RXF_INSN_SNC + 1;
   CPU_INSN_NAME (cpu) = cgen_insn_name;
   CPU_FULL_ENGINE_FN (cpu) = m32rxf_engine_run_full;
 #if WITH_FAST
diff --git a/sim/m32r/sem-switch.c b/sim/m32r/sem-switch.c
index 658d599..2d5489c 100644
--- a/sim/m32r/sem-switch.c
+++ b/sim/m32r/sem-switch.c
@@ -2,9 +2,9 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
 
-This file is part of the GNU Simulators.
+This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
diff --git a/sim/m32r/sem.c b/sim/m32r/sem.c
index 3fa4f59..8a20cc1 100644
--- a/sim/m32r/sem.c
+++ b/sim/m32r/sem.c
@@ -2,9 +2,9 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
 
-This file is part of the GNU Simulators.
+This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
diff --git a/sim/m32r/semx-switch.c b/sim/m32r/semx-switch.c
index dff0aed..3cc95b0 100644
--- a/sim/m32r/semx-switch.c
+++ b/sim/m32r/semx-switch.c
@@ -2,9 +2,9 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
 
-This file is part of the GNU Simulators.
+This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
@@ -3461,7 +3461,7 @@ CASE (sem, INSN_WRITE_BC8) : /* bc.s $disp8 */
 {
   {
     SI opval = ADDSI (ANDSI (pc, -4), 4);
-    OPRND (h_gr_14) = opval;
+    OPRND (h_gr_SI_14) = opval;
     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
   }
   {
@@ -3487,7 +3487,7 @@ CASE (sem, INSN_WRITE_BL8) : /* bl.s $disp8 */
     SEM_BRANCH_INIT
     vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 
-  CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_14);
+  CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14);
   SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
 
   SEM_BRANCH_FINI (vpc);
@@ -3510,7 +3510,7 @@ if (CPU (h_cond)) {
 {
   {
     SI opval = ADDSI (ANDSI (pc, -4), 4);
-    OPRND (h_gr_14) = opval;
+    OPRND (h_gr_SI_14) = opval;
     written |= (1 << 3);
     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
   }
@@ -3542,7 +3542,7 @@ CASE (sem, INSN_WRITE_BCL8) : /* bcl.s $disp8 */
 
   if (written & (1 << 3))
     {
-      CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_14);
+      CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14);
     }
   if (written & (1 << 4))
     {
@@ -3656,7 +3656,7 @@ if (NOTBI (CPU (h_cond))) {
 {
   {
     SI opval = ADDSI (ANDSI (pc, -4), 4);
-    OPRND (h_gr_14) = opval;
+    OPRND (h_gr_SI_14) = opval;
     written |= (1 << 3);
     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
   }
@@ -3688,7 +3688,7 @@ CASE (sem, INSN_WRITE_BNCL8) : /* bncl.s $disp8 */
 
   if (written & (1 << 3))
     {
-      CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_14);
+      CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14);
     }
   if (written & (1 << 4))
     {
@@ -3963,7 +3963,7 @@ CASE (sem, INSN_WRITE_JNC) : /* jnc $sr */
   temp1 = ANDSI (* FLD (i_sr), -4);
   {
     SI opval = temp0;
-    OPRND (h_gr_14) = opval;
+    OPRND (h_gr_SI_14) = opval;
     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
   }
   {
@@ -3989,7 +3989,7 @@ CASE (sem, INSN_WRITE_JL) : /* jl $sr */
     SEM_BRANCH_INIT
     vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 
-  CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_14);
+  CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14);
   SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
 
   SEM_BRANCH_FINI (vpc);
@@ -4081,7 +4081,7 @@ CASE (sem, INSN_WRITE_LD) : /* ld $dr,@$sr */
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ld.f
+#define OPRND(f) par_exec->operands.sfmt_ldb.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -4102,7 +4102,7 @@ CASE (sem, INSN_WRITE_LDB) : /* ldb $dr,@$sr */
     SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
     const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
 #define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ld.f
+#define OPRND(f) par_exec->operands.sfmt_ldb.f
     int UNUSED written = abuf->written;
     IADDR UNUSED pc = abuf->addr;
     vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
@@ -4119,7 +4119,7 @@ CASE (sem, INSN_WRITE_LDB) : /* ldb $dr,@$sr */
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ld.f
+#define OPRND(f) par_exec->operands.sfmt_ldh.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -4140,7 +4140,7 @@ CASE (sem, INSN_WRITE_LDH) : /* ldh $dr,@$sr */
     SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
     const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
 #define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ld.f
+#define OPRND(f) par_exec->operands.sfmt_ldh.f
     int UNUSED written = abuf->written;
     IADDR UNUSED pc = abuf->addr;
     vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
@@ -4157,7 +4157,7 @@ CASE (sem, INSN_WRITE_LDH) : /* ldh $dr,@$sr */
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ld.f
+#define OPRND(f) par_exec->operands.sfmt_ldb.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -4178,7 +4178,7 @@ CASE (sem, INSN_WRITE_LDUB) : /* ldub $dr,@$sr */
     SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
     const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
 #define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ld.f
+#define OPRND(f) par_exec->operands.sfmt_ldb.f
     int UNUSED written = abuf->written;
     IADDR UNUSED pc = abuf->addr;
     vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
@@ -4195,7 +4195,7 @@ CASE (sem, INSN_WRITE_LDUB) : /* ldub $dr,@$sr */
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ld.f
+#define OPRND(f) par_exec->operands.sfmt_ldh.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -4216,7 +4216,7 @@ CASE (sem, INSN_WRITE_LDUH) : /* lduh $dr,@$sr */
     SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
     const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
 #define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ld.f
+#define OPRND(f) par_exec->operands.sfmt_ldh.f
     int UNUSED written = abuf->written;
     IADDR UNUSED pc = abuf->addr;
     vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
@@ -4328,7 +4328,7 @@ CASE (sem, INSN_WRITE_LDI8) : /* ldi8 $dr,$simm8 */
 {
   {
     BI opval = 1;
-    OPRND (h_lock) = opval;
+    OPRND (h_lock_BI) = opval;
     TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
   }
   {
@@ -4354,7 +4354,7 @@ CASE (sem, INSN_WRITE_LOCK) : /* lock $dr,@$sr */
     vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 
   * FLD (i_dr) = OPRND (dr);
-  CPU (h_lock) = OPRND (h_lock);
+  CPU (h_lock) = OPRND (h_lock_BI);
 
 #undef OPRND
 #undef FLD
@@ -5220,17 +5220,17 @@ CASE (sem, INSN_WRITE_RACH_DSI) : /* rach $accd,$accs,$imm1 */
   }
   {
     USI opval = GET_H_CR (((UINT) 14));
-    OPRND (h_cr_6) = opval;
+    OPRND (h_cr_USI_6) = opval;
     TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
   }
   {
     UQI opval = CPU (h_bpsw);
-    OPRND (h_psw) = opval;
+    OPRND (h_psw_UQI) = opval;
     TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
   }
   {
     UQI opval = CPU (h_bbpsw);
-    OPRND (h_bpsw) = opval;
+    OPRND (h_bpsw_UQI) = opval;
     TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
   }
 }
@@ -5251,9 +5251,9 @@ CASE (sem, INSN_WRITE_RTE) : /* rte */
     SEM_BRANCH_INIT
     vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 
-  CPU (h_bpsw) = OPRND (h_bpsw);
-  SET_H_CR (((UINT) 6), OPRND (h_cr_6));
-  SET_H_PSW (OPRND (h_psw));
+  CPU (h_bpsw) = OPRND (h_bpsw_UQI);
+  SET_H_CR (((UINT) 6), OPRND (h_cr_USI_6));
+  SET_H_PSW (OPRND (h_psw_UQI));
   SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
 
   SEM_BRANCH_FINI (vpc);
@@ -5502,8 +5502,8 @@ CASE (sem, INSN_WRITE_SRLI) : /* srli $dr,$uimm5 */
 
   {
     SI opval = * FLD (i_src1);
-    OPRND (h_memory_src2_idx) = * FLD (i_src2);
-    OPRND (h_memory_src2) = opval;
+    OPRND (h_memory_SI_src2_idx) = * FLD (i_src2);
+    OPRND (h_memory_SI_src2) = opval;
     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
   }
 
@@ -5522,7 +5522,7 @@ CASE (sem, INSN_WRITE_ST) : /* st $src1,@$src2 */
     IADDR UNUSED pc = abuf->addr;
     vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 
-  SETMEMSI (current_cpu, pc, OPRND (h_memory_src2_idx), OPRND (h_memory_src2));
+  SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_src2_idx), OPRND (h_memory_SI_src2));
 
 #undef OPRND
 #undef FLD
@@ -5541,8 +5541,8 @@ CASE (sem, INSN_WRITE_ST) : /* st $src1,@$src2 */
 
   {
     QI opval = * FLD (i_src1);
-    OPRND (h_memory_src2_idx) = * FLD (i_src2);
-    OPRND (h_memory_src2) = opval;
+    OPRND (h_memory_QI_src2_idx) = * FLD (i_src2);
+    OPRND (h_memory_QI_src2) = opval;
     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
   }
 
@@ -5561,7 +5561,7 @@ CASE (sem, INSN_WRITE_STB) : /* stb $src1,@$src2 */
     IADDR UNUSED pc = abuf->addr;
     vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 
-  SETMEMQI (current_cpu, pc, OPRND (h_memory_src2_idx), OPRND (h_memory_src2));
+  SETMEMQI (current_cpu, pc, OPRND (h_memory_QI_src2_idx), OPRND (h_memory_QI_src2));
 
 #undef OPRND
 #undef FLD
@@ -5580,8 +5580,8 @@ CASE (sem, INSN_WRITE_STB) : /* stb $src1,@$src2 */
 
   {
     HI opval = * FLD (i_src1);
-    OPRND (h_memory_src2_idx) = * FLD (i_src2);
-    OPRND (h_memory_src2) = opval;
+    OPRND (h_memory_HI_src2_idx) = * FLD (i_src2);
+    OPRND (h_memory_HI_src2) = opval;
     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
   }
 
@@ -5600,7 +5600,7 @@ CASE (sem, INSN_WRITE_STH) : /* sth $src1,@$src2 */
     IADDR UNUSED pc = abuf->addr;
     vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 
-  SETMEMHI (current_cpu, pc, OPRND (h_memory_src2_idx), OPRND (h_memory_src2));
+  SETMEMHI (current_cpu, pc, OPRND (h_memory_HI_src2_idx), OPRND (h_memory_HI_src2));
 
 #undef OPRND
 #undef FLD
@@ -5622,8 +5622,8 @@ CASE (sem, INSN_WRITE_STH) : /* sth $src1,@$src2 */
   tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
   {
     SI opval = * FLD (i_src1);
-    OPRND (h_memory_new_src2_idx) = tmp_new_src2;
-    OPRND (h_memory_new_src2) = opval;
+    OPRND (h_memory_SI_new_src2_idx) = tmp_new_src2;
+    OPRND (h_memory_SI_new_src2) = opval;
     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
   }
   {
@@ -5648,7 +5648,7 @@ CASE (sem, INSN_WRITE_ST_PLUS) : /* st $src1,@+$src2 */
     IADDR UNUSED pc = abuf->addr;
     vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 
-  SETMEMSI (current_cpu, pc, OPRND (h_memory_new_src2_idx), OPRND (h_memory_new_src2));
+  SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_new_src2_idx), OPRND (h_memory_SI_new_src2));
   * FLD (i_src2) = OPRND (src2);
 
 #undef OPRND
@@ -5671,8 +5671,8 @@ CASE (sem, INSN_WRITE_ST_PLUS) : /* st $src1,@+$src2 */
   tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
   {
     SI opval = * FLD (i_src1);
-    OPRND (h_memory_new_src2_idx) = tmp_new_src2;
-    OPRND (h_memory_new_src2) = opval;
+    OPRND (h_memory_SI_new_src2_idx) = tmp_new_src2;
+    OPRND (h_memory_SI_new_src2) = opval;
     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
   }
   {
@@ -5697,7 +5697,7 @@ CASE (sem, INSN_WRITE_ST_MINUS) : /* st $src1,@-$src2 */
     IADDR UNUSED pc = abuf->addr;
     vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 
-  SETMEMSI (current_cpu, pc, OPRND (h_memory_new_src2_idx), OPRND (h_memory_new_src2));
+  SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_new_src2_idx), OPRND (h_memory_SI_new_src2));
   * FLD (i_src2) = OPRND (src2);
 
 #undef OPRND
@@ -5854,27 +5854,27 @@ CASE (sem, INSN_WRITE_SUBX) : /* subx $dr,$sr */
 {
   {
     USI opval = GET_H_CR (((UINT) 6));
-    OPRND (h_cr_14) = opval;
+    OPRND (h_cr_USI_14) = opval;
     TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
   }
   {
     USI opval = ADDSI (pc, 4);
-    OPRND (h_cr_6) = opval;
+    OPRND (h_cr_USI_6) = opval;
     TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
   }
   {
     UQI opval = CPU (h_bpsw);
-    OPRND (h_bbpsw) = opval;
+    OPRND (h_bbpsw_UQI) = opval;
     TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval);
   }
   {
     UQI opval = GET_H_PSW ();
-    OPRND (h_bpsw) = opval;
+    OPRND (h_bpsw_UQI) = opval;
     TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
   }
   {
     UQI opval = ANDQI (GET_H_PSW (), 128);
-    OPRND (h_psw) = opval;
+    OPRND (h_psw_UQI) = opval;
     TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
   }
   {
@@ -5900,11 +5900,11 @@ CASE (sem, INSN_WRITE_TRAP) : /* trap $uimm4 */
     SEM_BRANCH_INIT
     vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 
-  CPU (h_bbpsw) = OPRND (h_bbpsw);
-  CPU (h_bpsw) = OPRND (h_bpsw);
-  SET_H_CR (((UINT) 14), OPRND (h_cr_14));
-  SET_H_CR (((UINT) 6), OPRND (h_cr_6));
-  SET_H_PSW (OPRND (h_psw));
+  CPU (h_bbpsw) = OPRND (h_bbpsw_UQI);
+  CPU (h_bpsw) = OPRND (h_bpsw_UQI);
+  SET_H_CR (((UINT) 14), OPRND (h_cr_USI_14));
+  SET_H_CR (((UINT) 6), OPRND (h_cr_USI_6));
+  SET_H_PSW (OPRND (h_psw_UQI));
   SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
 
   SEM_BRANCH_FINI (vpc);
@@ -5927,15 +5927,15 @@ CASE (sem, INSN_WRITE_TRAP) : /* trap $uimm4 */
 if (CPU (h_lock)) {
   {
     SI opval = * FLD (i_src1);
-    OPRND (h_memory_src2_idx) = * FLD (i_src2);
-    OPRND (h_memory_src2) = opval;
+    OPRND (h_memory_SI_src2_idx) = * FLD (i_src2);
+    OPRND (h_memory_SI_src2) = opval;
     written |= (1 << 4);
     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
   }
 }
   {
     BI opval = 0;
-    OPRND (h_lock) = opval;
+    OPRND (h_lock_BI) = opval;
     TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
   }
 }
@@ -5956,10 +5956,10 @@ CASE (sem, INSN_WRITE_UNLOCK) : /* unlock $src1,@$src2 */
     IADDR UNUSED pc = abuf->addr;
     vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 
-  CPU (h_lock) = OPRND (h_lock);
+  CPU (h_lock) = OPRND (h_lock_BI);
   if (written & (1 << 4))
     {
-      SETMEMSI (current_cpu, pc, OPRND (h_memory_src2_idx), OPRND (h_memory_src2));
+      SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_src2_idx), OPRND (h_memory_SI_src2));
     }
 
 #undef OPRND
@@ -6017,7 +6017,7 @@ CASE (sem, INSN_WRITE_PCMPBZ) : /* pcmpbz $src2 */
 
   {
     DI opval = ADDDI (SRADI (GET_H_ACCUMS (((UINT) 1)), 16), GET_H_ACCUMS (((UINT) 0)));
-    OPRND (h_accums_0) = opval;
+    OPRND (h_accums_DI_0) = opval;
     TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
   }
 
@@ -6036,7 +6036,7 @@ CASE (sem, INSN_WRITE_SADD) : /* sadd */
     IADDR UNUSED pc = abuf->addr;
     vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 
-  SET_H_ACCUMS (((UINT) 0), OPRND (h_accums_0));
+  SET_H_ACCUMS (((UINT) 0), OPRND (h_accums_DI_0));
 
 #undef OPRND
 #undef FLD
@@ -6055,7 +6055,7 @@ CASE (sem, INSN_WRITE_SADD) : /* sadd */
 
   {
     DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535)))), 8), 8);
-    OPRND (h_accums_1) = opval;
+    OPRND (h_accums_DI_1) = opval;
     TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
   }
 
@@ -6074,7 +6074,7 @@ CASE (sem, INSN_WRITE_MACWU1) : /* macwu1 $src1,$src2 */
     IADDR UNUSED pc = abuf->addr;
     vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 
-  SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_1));
+  SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_DI_1));
 
 #undef OPRND
 #undef FLD
@@ -6131,7 +6131,7 @@ CASE (sem, INSN_WRITE_MSBLO) : /* msblo $src1,$src2 */
 
   {
     DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535))), 16), 16);
-    OPRND (h_accums_1) = opval;
+    OPRND (h_accums_DI_1) = opval;
     TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
   }
 
@@ -6150,7 +6150,7 @@ CASE (sem, INSN_WRITE_MULWU1) : /* mulwu1 $src1,$src2 */
     IADDR UNUSED pc = abuf->addr;
     vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 
-  SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_1));
+  SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_DI_1));
 
 #undef OPRND
 #undef FLD
@@ -6169,7 +6169,7 @@ CASE (sem, INSN_WRITE_MULWU1) : /* mulwu1 $src1,$src2 */
 
   {
     DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), SLLDI (EXTSIDI (MULSI (EXTHISI (TRUNCSIHI (* FLD (i_src1))), SRASI (* FLD (i_src2), 16))), 16)), 8), 8);
-    OPRND (h_accums_1) = opval;
+    OPRND (h_accums_DI_1) = opval;
     TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
   }
 
@@ -6188,7 +6188,7 @@ CASE (sem, INSN_WRITE_MACLH1) : /* maclh1 $src1,$src2 */
     IADDR UNUSED pc = abuf->addr;
     vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 
-  SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_1));
+  SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_DI_1));
 
 #undef OPRND
 #undef FLD
author	Dave Brolley <brolley@redhat.com>	2001-11-14 19:51:40 +0000
committer	Dave Brolley <brolley@redhat.com>	2001-11-14 19:51:40 +0000
commit	378af1d671c4ac1e6501c740ba97bbfe1964bf44 (patch)
tree	4d2c2d7b5dfc169f919fe24e1871ca1e959a43cc /sim
parent	3e43c635d5ceca27f56f51ca22ed7bce1e64ade0 (diff)
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