aboutsummaryrefslogtreecommitdiff
path: root/sim
diff options
context:
space:
mode:
authorAndrew Cagney <cagney@redhat.com>2002-06-17 23:37:43 +0000
committerAndrew Cagney <cagney@redhat.com>2002-06-17 23:37:43 +0000
commit57af9c8bc0f5254f4d729109ced8744d10b14c1a (patch)
treea0707a99d5ce2799ba0f092d9d8c2c63c507a5c4 /sim
parentfa88f6772de4b169c1651d73fc956cda828fb1b6 (diff)
downloadgdb-57af9c8bc0f5254f4d729109ced8744d10b14c1a.zip
gdb-57af9c8bc0f5254f4d729109ced8744d10b14c1a.tar.gz
gdb-57af9c8bc0f5254f4d729109ced8744d10b14c1a.tar.bz2
* d10v_sim.h (SET_PSW_BIT): Add cast to avoid inverting an enum.
Diffstat (limited to 'sim')
-rw-r--r--sim/d10v/ChangeLog4
-rw-r--r--sim/d10v/d10v_sim.h2
2 files changed, 5 insertions, 1 deletions
diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog
index f6e5eac..320eb98 100644
--- a/sim/d10v/ChangeLog
+++ b/sim/d10v/ChangeLog
@@ -1,3 +1,7 @@
+2002-06-17 Andrew Cagney <cagney@redhat.com>
+
+ * d10v_sim.h (SET_PSW_BIT): Add cast to avoid inverting an enum.
+
2002-06-16 Andrew Cagney <ac131313@redhat.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
diff --git a/sim/d10v/d10v_sim.h b/sim/d10v/d10v_sim.h
index ca14006..09e0631 100644
--- a/sim/d10v/d10v_sim.h
+++ b/sim/d10v/d10v_sim.h
@@ -318,7 +318,7 @@ enum
#define PSW CREG (PSW_CR)
#define SET_PSW(VAL) SET_CREG (PSW_CR, (VAL))
#define SET_HW_PSW(VAL) SET_HW_CREG (PSW_CR, (VAL))
-#define SET_PSW_BIT(MASK,VAL) move_to_cr (PSW_CR, ~(MASK), (VAL) ? (MASK) : 0, 1)
+#define SET_PSW_BIT(MASK,VAL) move_to_cr (PSW_CR, ~((reg_t) MASK), (VAL) ? (MASK) : 0, 1)
#define PSW_SM ((PSW & PSW_SM_BIT) != 0)
#define SET_PSW_SM(VAL) SET_PSW_BIT (PSW_SM_BIT, (VAL))