2001-11-14 Dave Brolley <brolley@redhat.com>

	* arch.c: Regenerate.
	* arch.h: Regenerate.
	* cpu.c: Regenerate.
	* cpu.h: Regenerate.
	* cpuall.h: Regenerate.
	* decode.c: Regenerate.
	* decode.h: Regenerate.
	* model.c: Regenerate.
	* sem-switch.c: Regenerate.
	* sem.c: Regenerate.

11 files changed, 727 insertions, 215 deletions

diff --git a/sim/fr30/ChangeLog b/sim/fr30/ChangeLog
index ed8f8af..c52ef62 100644
--- a/sim/fr30/ChangeLog
+++ b/sim/fr30/ChangeLog
@@ -1,3 +1,16 @@
+2001-11-14  Dave Brolley  <brolley@redhat.com>
+
+	* arch.c: Regenerate.
+	* arch.h: Regenerate.
+	* cpu.c: Regenerate.
+	* cpu.h: Regenerate.
+	* cpuall.h: Regenerate.
+	* decode.c: Regenerate.
+	* decode.h: Regenerate.
+	* model.c: Regenerate.
+	* sem-switch.c: Regenerate.
+	* sem.c: Regenerate.
+
 2001-07-05  Ben Elliston  <bje@redhat.com>
 
 	* Makefile.in (stamp-arch): Use $(CGEN_CPU_DIR).
diff --git a/sim/fr30/arch.c b/sim/fr30/arch.c
index a8404d8..c0f3c62 100644
--- a/sim/fr30/arch.c
+++ b/sim/fr30/arch.c
@@ -2,9 +2,9 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
 
-This file is part of the GNU Simulators.
+This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
diff --git a/sim/fr30/arch.h b/sim/fr30/arch.h
index dc92099..26de475 100644
--- a/sim/fr30/arch.h
+++ b/sim/fr30/arch.h
@@ -2,9 +2,9 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
 
-This file is part of the GNU Simulators.
+This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
diff --git a/sim/fr30/cpu.c b/sim/fr30/cpu.c
index 374bcc8..938a5b7 100644
--- a/sim/fr30/cpu.c
+++ b/sim/fr30/cpu.c
@@ -2,9 +2,9 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
 
-This file is part of the GNU Simulators.
+This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
diff --git a/sim/fr30/cpu.h b/sim/fr30/cpu.h
index 7a7ee46..3a9e7c6 100644
--- a/sim/fr30/cpu.h
+++ b/sim/fr30/cpu.h
@@ -2,9 +2,9 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
 
-This file is part of the GNU Simulators.
+This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
@@ -206,33 +206,33 @@ union sem_fields {
   } sfmt_call;
   struct { /*  */
     SI f_s10;
-    unsigned char in_h_gr_15;
-    unsigned char out_h_gr_15;
+    unsigned char in_h_gr_SI_15;
+    unsigned char out_h_gr_SI_15;
   } sfmt_addsp;
   struct { /*  */
     USI f_dir10;
-    unsigned char in_h_gr_15;
-    unsigned char out_h_gr_15;
+    unsigned char in_h_gr_SI_15;
+    unsigned char out_h_gr_SI_15;
   } sfmt_dmovr15pi;
   struct { /*  */
     UINT f_dir8;
-    unsigned char in_h_gr_13;
-    unsigned char out_h_gr_13;
+    unsigned char in_h_gr_SI_13;
+    unsigned char out_h_gr_SI_13;
   } sfmt_dmovr13pib;
   struct { /*  */
     USI f_dir9;
-    unsigned char in_h_gr_13;
-    unsigned char out_h_gr_13;
+    unsigned char in_h_gr_SI_13;
+    unsigned char out_h_gr_SI_13;
   } sfmt_dmovr13pih;
   struct { /*  */
     USI f_dir10;
-    unsigned char in_h_gr_13;
-    unsigned char out_h_gr_13;
+    unsigned char in_h_gr_SI_13;
+    unsigned char out_h_gr_SI_13;
   } sfmt_dmovr13pi;
   struct { /*  */
     UINT f_Rs2;
-    unsigned char in_h_gr_15;
-    unsigned char out_h_gr_15;
+    unsigned char in_h_gr_SI_15;
+    unsigned char out_h_gr_SI_15;
   } sfmt_ldr15dr;
   struct { /*  */
     SI* i_Ri;
@@ -266,79 +266,79 @@ union sem_fields {
   } sfmt_ldi8;
   struct { /*  */
     USI f_u10;
-    unsigned char in_h_gr_14;
-    unsigned char in_h_gr_15;
-    unsigned char out_h_gr_14;
-    unsigned char out_h_gr_15;
+    unsigned char in_h_gr_SI_14;
+    unsigned char in_h_gr_SI_15;
+    unsigned char out_h_gr_SI_14;
+    unsigned char out_h_gr_SI_15;
   } sfmt_enter;
   struct { /*  */
     SI* i_Ri;
     UINT f_Ri;
     unsigned char in_Ri;
-    unsigned char in_h_gr_15;
-    unsigned char out_h_gr_15;
+    unsigned char in_h_gr_SI_15;
+    unsigned char out_h_gr_SI_15;
   } sfmt_str15gr;
   struct { /*  */
     SI* i_Ri;
     UINT f_Ri;
     USI f_udisp6;
     unsigned char in_Ri;
-    unsigned char in_h_gr_15;
+    unsigned char in_h_gr_SI_15;
   } sfmt_str15;
   struct { /*  */
     SI* i_Ri;
     INT f_disp8;
     UINT f_Ri;
     unsigned char in_Ri;
-    unsigned char in_h_gr_14;
+    unsigned char in_h_gr_SI_14;
   } sfmt_str14b;
   struct { /*  */
     SI* i_Ri;
     SI f_disp9;
     UINT f_Ri;
     unsigned char in_Ri;
-    unsigned char in_h_gr_14;
+    unsigned char in_h_gr_SI_14;
   } sfmt_str14h;
   struct { /*  */
     SI* i_Ri;
     SI f_disp10;
     UINT f_Ri;
     unsigned char in_Ri;
-    unsigned char in_h_gr_14;
+    unsigned char in_h_gr_SI_14;
   } sfmt_str14;
   struct { /*  */
     SI* i_Ri;
     UINT f_Ri;
-    unsigned char in_h_gr_15;
+    unsigned char in_h_gr_SI_15;
     unsigned char out_Ri;
-    unsigned char out_h_gr_15;
+    unsigned char out_h_gr_SI_15;
   } sfmt_ldr15gr;
   struct { /*  */
     SI* i_Ri;
     UINT f_Ri;
     USI f_udisp6;
-    unsigned char in_h_gr_15;
+    unsigned char in_h_gr_SI_15;
     unsigned char out_Ri;
   } sfmt_ldr15;
   struct { /*  */
     SI* i_Ri;
     INT f_disp8;
     UINT f_Ri;
-    unsigned char in_h_gr_14;
+    unsigned char in_h_gr_SI_14;
     unsigned char out_Ri;
   } sfmt_ldr14ub;
   struct { /*  */
     SI* i_Ri;
     SI f_disp9;
     UINT f_Ri;
-    unsigned char in_h_gr_14;
+    unsigned char in_h_gr_SI_14;
     unsigned char out_Ri;
   } sfmt_ldr14uh;
   struct { /*  */
     SI* i_Ri;
     SI f_disp10;
     UINT f_Ri;
-    unsigned char in_h_gr_14;
+    unsigned char in_h_gr_SI_14;
     unsigned char out_Ri;
   } sfmt_ldr14;
   struct { /*  */
@@ -362,7 +362,7 @@ union sem_fields {
     UINT f_Rj;
     unsigned char in_Ri;
     unsigned char in_Rj;
-    unsigned char in_h_gr_13;
+    unsigned char in_h_gr_SI_13;
   } sfmt_str13;
   struct { /*  */
     SI* i_Ri;
@@ -370,7 +370,7 @@ union sem_fields {
     UINT f_Ri;
     UINT f_Rj;
     unsigned char in_Rj;
-    unsigned char in_h_gr_13;
+    unsigned char in_h_gr_SI_13;
     unsigned char out_Ri;
   } sfmt_ldr13;
   struct { /*  */
@@ -384,53 +384,53 @@ union sem_fields {
   } sfmt_add;
   struct { /*  */
     UINT f_reglist_hi_st;
-    unsigned char in_h_gr_10;
-    unsigned char in_h_gr_11;
-    unsigned char in_h_gr_12;
-    unsigned char in_h_gr_13;
-    unsigned char in_h_gr_14;
-    unsigned char in_h_gr_15;
-    unsigned char in_h_gr_8;
-    unsigned char in_h_gr_9;
-    unsigned char out_h_gr_15;
+    unsigned char in_h_gr_SI_10;
+    unsigned char in_h_gr_SI_11;
+    unsigned char in_h_gr_SI_12;
+    unsigned char in_h_gr_SI_13;
+    unsigned char in_h_gr_SI_14;
+    unsigned char in_h_gr_SI_15;
+    unsigned char in_h_gr_SI_8;
+    unsigned char in_h_gr_SI_9;
+    unsigned char out_h_gr_SI_15;
   } sfmt_stm1;
   struct { /*  */
     UINT f_reglist_hi_ld;
-    unsigned char in_h_gr_15;
-    unsigned char out_h_gr_10;
-    unsigned char out_h_gr_11;
-    unsigned char out_h_gr_12;
-    unsigned char out_h_gr_13;
-    unsigned char out_h_gr_14;
-    unsigned char out_h_gr_15;
-    unsigned char out_h_gr_8;
-    unsigned char out_h_gr_9;
+    unsigned char in_h_gr_SI_15;
+    unsigned char out_h_gr_SI_10;
+    unsigned char out_h_gr_SI_11;
+    unsigned char out_h_gr_SI_12;
+    unsigned char out_h_gr_SI_13;
+    unsigned char out_h_gr_SI_14;
+    unsigned char out_h_gr_SI_15;
+    unsigned char out_h_gr_SI_8;
+    unsigned char out_h_gr_SI_9;
   } sfmt_ldm1;
   struct { /*  */
     UINT f_reglist_low_st;
-    unsigned char in_h_gr_0;
-    unsigned char in_h_gr_1;
-    unsigned char in_h_gr_15;
-    unsigned char in_h_gr_2;
-    unsigned char in_h_gr_3;
-    unsigned char in_h_gr_4;
-    unsigned char in_h_gr_5;
-    unsigned char in_h_gr_6;
-    unsigned char in_h_gr_7;
-    unsigned char out_h_gr_15;
+    unsigned char in_h_gr_SI_0;
+    unsigned char in_h_gr_SI_1;
+    unsigned char in_h_gr_SI_15;
+    unsigned char in_h_gr_SI_2;
+    unsigned char in_h_gr_SI_3;
+    unsigned char in_h_gr_SI_4;
+    unsigned char in_h_gr_SI_5;
+    unsigned char in_h_gr_SI_6;
+    unsigned char in_h_gr_SI_7;
+    unsigned char out_h_gr_SI_15;
   } sfmt_stm0;
   struct { /*  */
     UINT f_reglist_low_ld;
-    unsigned char in_h_gr_15;
-    unsigned char out_h_gr_0;
-    unsigned char out_h_gr_1;
-    unsigned char out_h_gr_15;
-    unsigned char out_h_gr_2;
-    unsigned char out_h_gr_3;
-    unsigned char out_h_gr_4;
-    unsigned char out_h_gr_5;
-    unsigned char out_h_gr_6;
-    unsigned char out_h_gr_7;
+    unsigned char in_h_gr_SI_15;
+    unsigned char out_h_gr_SI_0;
+    unsigned char out_h_gr_SI_1;
+    unsigned char out_h_gr_SI_15;
+    unsigned char out_h_gr_SI_2;
+    unsigned char out_h_gr_SI_3;
+    unsigned char out_h_gr_SI_4;
+    unsigned char out_h_gr_SI_5;
+    unsigned char out_h_gr_SI_6;
+    unsigned char out_h_gr_SI_7;
   } sfmt_ldm0;
 #if WITH_SCACHE_PBB
   /* Writeback handler.  */
@@ -768,7 +768,7 @@ struct scache {
   f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
   f_CRj = (0|(EXTRACT_MSB0_UINT (word_1, 16, 8, 4) << 0)); \
   f_u4c = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-  f_CRi = (0|(EXTRACT_MSB0_UINT (word_1, 16, 12, 16) << 0)); \
+  f_CRi = (0|(EXTRACT_MSB0_UINT (word_1, 16, 12, 4) << 0)); \
 
 #define EXTRACT_IFMT_COPLD_VARS \
   UINT f_op1; \
@@ -790,7 +790,7 @@ struct scache {
   f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
   f_Rjc = (0|(EXTRACT_MSB0_UINT (word_1, 16, 8, 4) << 0)); \
   f_u4c = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-  f_CRi = (0|(EXTRACT_MSB0_UINT (word_1, 16, 12, 16) << 0)); \
+  f_CRi = (0|(EXTRACT_MSB0_UINT (word_1, 16, 12, 4) << 0)); \
 
 #define EXTRACT_IFMT_COPST_VARS \
   UINT f_op1; \
@@ -812,7 +812,7 @@ struct scache {
   f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
   f_CRj = (0|(EXTRACT_MSB0_UINT (word_1, 16, 8, 4) << 0)); \
   f_u4c = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-  f_Ric = (0|(EXTRACT_MSB0_UINT (word_1, 16, 12, 16) << 0)); \
+  f_Ric = (0|(EXTRACT_MSB0_UINT (word_1, 16, 12, 4) << 0)); \
 
 #define EXTRACT_IFMT_ADDSP_VARS \
   UINT f_op1; \
diff --git a/sim/fr30/cpuall.h b/sim/fr30/cpuall.h
index 59646cf..296228d 100644
--- a/sim/fr30/cpuall.h
+++ b/sim/fr30/cpuall.h
@@ -2,9 +2,9 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
 
-This file is part of the GNU Simulators.
+This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
diff --git a/sim/fr30/decode.c b/sim/fr30/decode.c
index ff01ce5..445c3ab 100644
--- a/sim/fr30/decode.c
+++ b/sim/fr30/decode.c
@@ -2,9 +2,9 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
 
-This file is part of the GNU Simulators.
+This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
@@ -33,7 +33,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
    teensy bit of cpu in the decoder.  Moving it to malloc space is trivial
    but won't be done until necessary (we don't currently support the runtime
    addition of instructions nor an SMP machine with different cpus).  */
-static IDESC fr30bf_insn_data[FR30BF_INSN_MAX];
+static IDESC fr30bf_insn_data[FR30BF_INSN_XCHB + 1];
 
 /* Commas between elements are contained in the macros.
    Some of these are conditionally compiled out.  */
@@ -102,11 +102,11 @@ static const struct insn_sem fr30bf_insn_sem[] =
   { FR30_INSN_LDI20, FR30BF_INSN_LDI20, FR30BF_SFMT_LDI20 },
   { FR30_INSN_LDI32, FR30BF_INSN_LDI32, FR30BF_SFMT_LDI32 },
   { FR30_INSN_LD, FR30BF_INSN_LD, FR30BF_SFMT_LD },
-  { FR30_INSN_LDUH, FR30BF_INSN_LDUH, FR30BF_SFMT_LD },
-  { FR30_INSN_LDUB, FR30BF_INSN_LDUB, FR30BF_SFMT_LD },
+  { FR30_INSN_LDUH, FR30BF_INSN_LDUH, FR30BF_SFMT_LDUH },
+  { FR30_INSN_LDUB, FR30BF_INSN_LDUB, FR30BF_SFMT_LDUB },
   { FR30_INSN_LDR13, FR30BF_INSN_LDR13, FR30BF_SFMT_LDR13 },
-  { FR30_INSN_LDR13UH, FR30BF_INSN_LDR13UH, FR30BF_SFMT_LDR13 },
-  { FR30_INSN_LDR13UB, FR30BF_INSN_LDR13UB, FR30BF_SFMT_LDR13 },
+  { FR30_INSN_LDR13UH, FR30BF_INSN_LDR13UH, FR30BF_SFMT_LDR13UH },
+  { FR30_INSN_LDR13UB, FR30BF_INSN_LDR13UB, FR30BF_SFMT_LDR13UB },
   { FR30_INSN_LDR14, FR30BF_INSN_LDR14, FR30BF_SFMT_LDR14 },
   { FR30_INSN_LDR14UH, FR30BF_INSN_LDR14UH, FR30BF_SFMT_LDR14UH },
   { FR30_INSN_LDR14UB, FR30BF_INSN_LDR14UB, FR30BF_SFMT_LDR14UB },
@@ -115,11 +115,11 @@ static const struct insn_sem fr30bf_insn_sem[] =
   { FR30_INSN_LDR15DR, FR30BF_INSN_LDR15DR, FR30BF_SFMT_LDR15DR },
   { FR30_INSN_LDR15PS, FR30BF_INSN_LDR15PS, FR30BF_SFMT_LDR15PS },
   { FR30_INSN_ST, FR30BF_INSN_ST, FR30BF_SFMT_ST },
-  { FR30_INSN_STH, FR30BF_INSN_STH, FR30BF_SFMT_ST },
-  { FR30_INSN_STB, FR30BF_INSN_STB, FR30BF_SFMT_ST },
+  { FR30_INSN_STH, FR30BF_INSN_STH, FR30BF_SFMT_STH },
+  { FR30_INSN_STB, FR30BF_INSN_STB, FR30BF_SFMT_STB },
   { FR30_INSN_STR13, FR30BF_INSN_STR13, FR30BF_SFMT_STR13 },
-  { FR30_INSN_STR13H, FR30BF_INSN_STR13H, FR30BF_SFMT_STR13 },
-  { FR30_INSN_STR13B, FR30BF_INSN_STR13B, FR30BF_SFMT_STR13 },
+  { FR30_INSN_STR13H, FR30BF_INSN_STR13H, FR30BF_SFMT_STR13H },
+  { FR30_INSN_STR13B, FR30BF_INSN_STR13B, FR30BF_SFMT_STR13B },
   { FR30_INSN_STR14, FR30BF_INSN_STR14, FR30BF_SFMT_STR14 },
   { FR30_INSN_STR14H, FR30BF_INSN_STR14H, FR30BF_SFMT_STR14H },
   { FR30_INSN_STR14B, FR30BF_INSN_STR14B, FR30BF_SFMT_STR14B },
@@ -252,7 +252,7 @@ fr30bf_init_idesc_table (SIM_CPU *cpu)
 {
   IDESC *id,*tabend;
   const struct insn_sem *t,*tend;
-  int tabsize = FR30BF_INSN_MAX;
+  int tabsize = sizeof (fr30bf_insn_data) / sizeof (IDESC);
   IDESC *table = fr30bf_insn_data;
 
   memset (table, 0, tabsize * sizeof (IDESC));
@@ -282,31 +282,69 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
 {
   /* Result of decoder.  */
   FR30BF_INSN_TYPE itype;
-  CGEN_INSN_INT insn = base_insn;
 
   {
+    CGEN_INSN_INT insn = base_insn;
 
     {
       unsigned int val = (((insn >> 8) & (255 << 0)));
       switch (val)
       {
-      case 0 : itype = FR30BF_INSN_LDR13; goto extract_sfmt_ldr13;      case 1 : itype = FR30BF_INSN_LDR13UH; goto extract_sfmt_ldr13;      case 2 : itype = FR30BF_INSN_LDR13UB; goto extract_sfmt_ldr13;      case 3 : itype = FR30BF_INSN_LDR15; goto extract_sfmt_ldr15;      case 4 : itype = FR30BF_INSN_LD; goto extract_sfmt_ld;      case 5 : itype = FR30BF_INSN_LDUH; goto extract_sfmt_ld;      case 6 : itype = FR30BF_INSN_LDUB; goto extract_sfmt_ld;      case 7 :
+      case 0 : itype = FR30BF_INSN_LDR13;goto extract_sfmt_ldr13;
+      case 1 : itype = FR30BF_INSN_LDR13UH;goto extract_sfmt_ldr13uh;
+      case 2 : itype = FR30BF_INSN_LDR13UB;goto extract_sfmt_ldr13ub;
+      case 3 : itype = FR30BF_INSN_LDR15;goto extract_sfmt_ldr15;
+      case 4 : itype = FR30BF_INSN_LD;goto extract_sfmt_ld;
+      case 5 : itype = FR30BF_INSN_LDUH;goto extract_sfmt_lduh;
+      case 6 : itype = FR30BF_INSN_LDUB;goto extract_sfmt_ldub;
+      case 7 :
         {
           unsigned int val = (((insn >> 6) & (1 << 1)) | ((insn >> 4) & (1 << 0)));
           switch (val)
           {
-          case 0 : itype = FR30BF_INSN_LDR15GR; goto extract_sfmt_ldr15gr;          case 1 : itype = FR30BF_INSN_MOV2PS; goto extract_sfmt_mov2ps;          case 2 : itype = FR30BF_INSN_LDR15DR; goto extract_sfmt_ldr15dr;          case 3 : itype = FR30BF_INSN_LDR15PS; goto extract_sfmt_ldr15ps;          default : itype = FR30BF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 0 : itype = FR30BF_INSN_LDR15GR;goto extract_sfmt_ldr15gr;
+          case 1 : itype = FR30BF_INSN_MOV2PS;goto extract_sfmt_mov2ps;
+          case 2 : itype = FR30BF_INSN_LDR15DR;goto extract_sfmt_ldr15dr;
+          case 3 : itype = FR30BF_INSN_LDR15PS;goto extract_sfmt_ldr15ps;
+          default : itype = FR30BF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 8 : itype = FR30BF_INSN_DMOV2R13; goto extract_sfmt_dmov2r13;      case 9 : itype = FR30BF_INSN_DMOV2R13H; goto extract_sfmt_dmov2r13h;      case 10 : itype = FR30BF_INSN_DMOV2R13B; goto extract_sfmt_dmov2r13b;      case 11 : itype = FR30BF_INSN_DMOV2R15PD; goto extract_sfmt_dmov2r15pd;      case 12 : itype = FR30BF_INSN_DMOV2R13PI; goto extract_sfmt_dmov2r13pi;      case 13 : itype = FR30BF_INSN_DMOV2R13PIH; goto extract_sfmt_dmov2r13pih;      case 14 : itype = FR30BF_INSN_DMOV2R13PIB; goto extract_sfmt_dmov2r13pib;      case 15 : itype = FR30BF_INSN_ENTER; goto extract_sfmt_enter;      case 16 : itype = FR30BF_INSN_STR13; goto extract_sfmt_str13;      case 17 : itype = FR30BF_INSN_STR13H; goto extract_sfmt_str13;      case 18 : itype = FR30BF_INSN_STR13B; goto extract_sfmt_str13;      case 19 : itype = FR30BF_INSN_STR15; goto extract_sfmt_str15;      case 20 : itype = FR30BF_INSN_ST; goto extract_sfmt_st;      case 21 : itype = FR30BF_INSN_STH; goto extract_sfmt_st;      case 22 : itype = FR30BF_INSN_STB; goto extract_sfmt_st;      case 23 :
+      case 8 : itype = FR30BF_INSN_DMOV2R13;goto extract_sfmt_dmov2r13;
+      case 9 : itype = FR30BF_INSN_DMOV2R13H;goto extract_sfmt_dmov2r13h;
+      case 10 : itype = FR30BF_INSN_DMOV2R13B;goto extract_sfmt_dmov2r13b;
+      case 11 : itype = FR30BF_INSN_DMOV2R15PD;goto extract_sfmt_dmov2r15pd;
+      case 12 : itype = FR30BF_INSN_DMOV2R13PI;goto extract_sfmt_dmov2r13pi;
+      case 13 : itype = FR30BF_INSN_DMOV2R13PIH;goto extract_sfmt_dmov2r13pih;
+      case 14 : itype = FR30BF_INSN_DMOV2R13PIB;goto extract_sfmt_dmov2r13pib;
+      case 15 : itype = FR30BF_INSN_ENTER;goto extract_sfmt_enter;
+      case 16 : itype = FR30BF_INSN_STR13;goto extract_sfmt_str13;
+      case 17 : itype = FR30BF_INSN_STR13H;goto extract_sfmt_str13h;
+      case 18 : itype = FR30BF_INSN_STR13B;goto extract_sfmt_str13b;
+      case 19 : itype = FR30BF_INSN_STR15;goto extract_sfmt_str15;
+      case 20 : itype = FR30BF_INSN_ST;goto extract_sfmt_st;
+      case 21 : itype = FR30BF_INSN_STH;goto extract_sfmt_sth;
+      case 22 : itype = FR30BF_INSN_STB;goto extract_sfmt_stb;
+      case 23 :
         {
           unsigned int val = (((insn >> 6) & (1 << 1)) | ((insn >> 4) & (1 << 0)));
           switch (val)
           {
-          case 0 : itype = FR30BF_INSN_STR15GR; goto extract_sfmt_str15gr;          case 1 : itype = FR30BF_INSN_MOVPS; goto extract_sfmt_movps;          case 2 : itype = FR30BF_INSN_STR15DR; goto extract_sfmt_str15dr;          case 3 : itype = FR30BF_INSN_STR15PS; goto extract_sfmt_str15ps;          default : itype = FR30BF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 0 : itype = FR30BF_INSN_STR15GR;goto extract_sfmt_str15gr;
+          case 1 : itype = FR30BF_INSN_MOVPS;goto extract_sfmt_movps;
+          case 2 : itype = FR30BF_INSN_STR15DR;goto extract_sfmt_str15dr;
+          case 3 : itype = FR30BF_INSN_STR15PS;goto extract_sfmt_str15ps;
+          default : itype = FR30BF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 24 : itype = FR30BF_INSN_DMOVR13; goto extract_sfmt_dmovr13;      case 25 : itype = FR30BF_INSN_DMOVR13H; goto extract_sfmt_dmovr13h;      case 26 : itype = FR30BF_INSN_DMOVR13B; goto extract_sfmt_dmovr13b;      case 27 : itype = FR30BF_INSN_DMOVR15PI; goto extract_sfmt_dmovr15pi;      case 28 : itype = FR30BF_INSN_DMOVR13PI; goto extract_sfmt_dmovr13pi;      case 29 : itype = FR30BF_INSN_DMOVR13PIH; goto extract_sfmt_dmovr13pih;      case 30 : itype = FR30BF_INSN_DMOVR13PIB; goto extract_sfmt_dmovr13pib;      case 31 : itype = FR30BF_INSN_INT; goto extract_sfmt_int;      case 32 : /* fall through */
+      case 24 : itype = FR30BF_INSN_DMOVR13;goto extract_sfmt_dmovr13;
+      case 25 : itype = FR30BF_INSN_DMOVR13H;goto extract_sfmt_dmovr13h;
+      case 26 : itype = FR30BF_INSN_DMOVR13B;goto extract_sfmt_dmovr13b;
+      case 27 : itype = FR30BF_INSN_DMOVR15PI;goto extract_sfmt_dmovr15pi;
+      case 28 : itype = FR30BF_INSN_DMOVR13PI;goto extract_sfmt_dmovr13pi;
+      case 29 : itype = FR30BF_INSN_DMOVR13PIH;goto extract_sfmt_dmovr13pih;
+      case 30 : itype = FR30BF_INSN_DMOVR13PIB;goto extract_sfmt_dmovr13pib;
+      case 31 : itype = FR30BF_INSN_INT;goto extract_sfmt_int;
+      case 32 : /* fall through */
       case 33 : /* fall through */
       case 34 : /* fall through */
       case 35 : /* fall through */
@@ -321,7 +359,8 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 44 : /* fall through */
       case 45 : /* fall through */
       case 46 : /* fall through */
-      case 47 : itype = FR30BF_INSN_LDR14; goto extract_sfmt_ldr14;      case 48 : /* fall through */
+      case 47 : itype = FR30BF_INSN_LDR14;goto extract_sfmt_ldr14;
+      case 48 : /* fall through */
       case 49 : /* fall through */
       case 50 : /* fall through */
       case 51 : /* fall through */
@@ -336,7 +375,8 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 60 : /* fall through */
       case 61 : /* fall through */
       case 62 : /* fall through */
-      case 63 : itype = FR30BF_INSN_STR14; goto extract_sfmt_str14;      case 64 : /* fall through */
+      case 63 : itype = FR30BF_INSN_STR14;goto extract_sfmt_str14;
+      case 64 : /* fall through */
       case 65 : /* fall through */
       case 66 : /* fall through */
       case 67 : /* fall through */
@@ -351,7 +391,8 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 76 : /* fall through */
       case 77 : /* fall through */
       case 78 : /* fall through */
-      case 79 : itype = FR30BF_INSN_LDR14UH; goto extract_sfmt_ldr14uh;      case 80 : /* fall through */
+      case 79 : itype = FR30BF_INSN_LDR14UH;goto extract_sfmt_ldr14uh;
+      case 80 : /* fall through */
       case 81 : /* fall through */
       case 82 : /* fall through */
       case 83 : /* fall through */
@@ -366,7 +407,8 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 92 : /* fall through */
       case 93 : /* fall through */
       case 94 : /* fall through */
-      case 95 : itype = FR30BF_INSN_STR14H; goto extract_sfmt_str14h;      case 96 : /* fall through */
+      case 95 : itype = FR30BF_INSN_STR14H;goto extract_sfmt_str14h;
+      case 96 : /* fall through */
       case 97 : /* fall through */
       case 98 : /* fall through */
       case 99 : /* fall through */
@@ -381,7 +423,8 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 108 : /* fall through */
       case 109 : /* fall through */
       case 110 : /* fall through */
-      case 111 : itype = FR30BF_INSN_LDR14UB; goto extract_sfmt_ldr14ub;      case 112 : /* fall through */
+      case 111 : itype = FR30BF_INSN_LDR14UB;goto extract_sfmt_ldr14ub;
+      case 112 : /* fall through */
       case 113 : /* fall through */
       case 114 : /* fall through */
       case 115 : /* fall through */
@@ -396,23 +439,110 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 124 : /* fall through */
       case 125 : /* fall through */
       case 126 : /* fall through */
-      case 127 : itype = FR30BF_INSN_STR14B; goto extract_sfmt_str14b;      case 128 : itype = FR30BF_INSN_BANDL; goto extract_sfmt_bandl;      case 129 : itype = FR30BF_INSN_BANDH; goto extract_sfmt_bandl;      case 130 : itype = FR30BF_INSN_AND; goto extract_sfmt_and;      case 131 : itype = FR30BF_INSN_ANDCCR; goto extract_sfmt_andccr;      case 132 : itype = FR30BF_INSN_ANDM; goto extract_sfmt_andm;      case 133 : itype = FR30BF_INSN_ANDH; goto extract_sfmt_andh;      case 134 : itype = FR30BF_INSN_ANDB; goto extract_sfmt_andb;      case 135 : itype = FR30BF_INSN_STILM; goto extract_sfmt_stilm;      case 136 : itype = FR30BF_INSN_BTSTL; goto extract_sfmt_btstl;      case 137 : itype = FR30BF_INSN_BTSTH; goto extract_sfmt_btstl;      case 138 : itype = FR30BF_INSN_XCHB; goto extract_sfmt_xchb;      case 139 : itype = FR30BF_INSN_MOV; goto extract_sfmt_mov;      case 140 : itype = FR30BF_INSN_LDM0; goto extract_sfmt_ldm0;      case 141 : itype = FR30BF_INSN_LDM1; goto extract_sfmt_ldm1;      case 142 : itype = FR30BF_INSN_STM0; goto extract_sfmt_stm0;      case 143 : itype = FR30BF_INSN_STM1; goto extract_sfmt_stm1;      case 144 : itype = FR30BF_INSN_BORL; goto extract_sfmt_bandl;      case 145 : itype = FR30BF_INSN_BORH; goto extract_sfmt_bandl;      case 146 : itype = FR30BF_INSN_OR; goto extract_sfmt_and;      case 147 : itype = FR30BF_INSN_ORCCR; goto extract_sfmt_andccr;      case 148 : itype = FR30BF_INSN_ORM; goto extract_sfmt_andm;      case 149 : itype = FR30BF_INSN_ORH; goto extract_sfmt_andh;      case 150 : itype = FR30BF_INSN_ORB; goto extract_sfmt_andb;      case 151 :
+      case 127 : itype = FR30BF_INSN_STR14B;goto extract_sfmt_str14b;
+      case 128 : itype = FR30BF_INSN_BANDL;goto extract_sfmt_bandl;
+      case 129 : itype = FR30BF_INSN_BANDH;goto extract_sfmt_bandl;
+      case 130 : itype = FR30BF_INSN_AND;goto extract_sfmt_and;
+      case 131 : itype = FR30BF_INSN_ANDCCR;goto extract_sfmt_andccr;
+      case 132 : itype = FR30BF_INSN_ANDM;goto extract_sfmt_andm;
+      case 133 : itype = FR30BF_INSN_ANDH;goto extract_sfmt_andh;
+      case 134 : itype = FR30BF_INSN_ANDB;goto extract_sfmt_andb;
+      case 135 : itype = FR30BF_INSN_STILM;goto extract_sfmt_stilm;
+      case 136 : itype = FR30BF_INSN_BTSTL;goto extract_sfmt_btstl;
+      case 137 : itype = FR30BF_INSN_BTSTH;goto extract_sfmt_btstl;
+      case 138 : itype = FR30BF_INSN_XCHB;goto extract_sfmt_xchb;
+      case 139 : itype = FR30BF_INSN_MOV;goto extract_sfmt_mov;
+      case 140 : itype = FR30BF_INSN_LDM0;goto extract_sfmt_ldm0;
+      case 141 : itype = FR30BF_INSN_LDM1;goto extract_sfmt_ldm1;
+      case 142 : itype = FR30BF_INSN_STM0;goto extract_sfmt_stm0;
+      case 143 : itype = FR30BF_INSN_STM1;goto extract_sfmt_stm1;
+      case 144 : itype = FR30BF_INSN_BORL;goto extract_sfmt_bandl;
+      case 145 : itype = FR30BF_INSN_BORH;goto extract_sfmt_bandl;
+      case 146 : itype = FR30BF_INSN_OR;goto extract_sfmt_and;
+      case 147 : itype = FR30BF_INSN_ORCCR;goto extract_sfmt_andccr;
+      case 148 : itype = FR30BF_INSN_ORM;goto extract_sfmt_andm;
+      case 149 : itype = FR30BF_INSN_ORH;goto extract_sfmt_andh;
+      case 150 : itype = FR30BF_INSN_ORB;goto extract_sfmt_andb;
+      case 151 :
         {
           unsigned int val = (((insn >> 4) & (15 << 0)));
           switch (val)
           {
-          case 0 : itype = FR30BF_INSN_JMP; goto extract_sfmt_jmp;          case 1 : itype = FR30BF_INSN_CALLR; goto extract_sfmt_callr;          case 2 : itype = FR30BF_INSN_RET; goto extract_sfmt_ret;          case 3 : itype = FR30BF_INSN_RETI; goto extract_sfmt_reti;          case 4 : itype = FR30BF_INSN_DIV0S; goto extract_sfmt_div0s;          case 5 : itype = FR30BF_INSN_DIV0U; goto extract_sfmt_div0u;          case 6 : itype = FR30BF_INSN_DIV1; goto extract_sfmt_div1;          case 7 : itype = FR30BF_INSN_DIV2; goto extract_sfmt_div2;          case 8 : itype = FR30BF_INSN_EXTSB; goto extract_sfmt_extsb;          case 9 : itype = FR30BF_INSN_EXTUB; goto extract_sfmt_extub;          case 10 : itype = FR30BF_INSN_EXTSH; goto extract_sfmt_extsh;          case 11 : itype = FR30BF_INSN_EXTUH; goto extract_sfmt_extuh;          default : itype = FR30BF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 0 : itype = FR30BF_INSN_JMP;goto extract_sfmt_jmp;
+          case 1 : itype = FR30BF_INSN_CALLR;goto extract_sfmt_callr;
+          case 2 : itype = FR30BF_INSN_RET;goto extract_sfmt_ret;
+          case 3 : itype = FR30BF_INSN_RETI;goto extract_sfmt_reti;
+          case 4 : itype = FR30BF_INSN_DIV0S;goto extract_sfmt_div0s;
+          case 5 : itype = FR30BF_INSN_DIV0U;goto extract_sfmt_div0u;
+          case 6 : itype = FR30BF_INSN_DIV1;goto extract_sfmt_div1;
+          case 7 : itype = FR30BF_INSN_DIV2;goto extract_sfmt_div2;
+          case 8 : itype = FR30BF_INSN_EXTSB;goto extract_sfmt_extsb;
+          case 9 : itype = FR30BF_INSN_EXTUB;goto extract_sfmt_extub;
+          case 10 : itype = FR30BF_INSN_EXTSH;goto extract_sfmt_extsh;
+          case 11 : itype = FR30BF_INSN_EXTUH;goto extract_sfmt_extuh;
+          default : itype = FR30BF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 152 : itype = FR30BF_INSN_BEORL; goto extract_sfmt_bandl;      case 153 : itype = FR30BF_INSN_BEORH; goto extract_sfmt_bandl;      case 154 : itype = FR30BF_INSN_EOR; goto extract_sfmt_and;      case 155 : itype = FR30BF_INSN_LDI20; goto extract_sfmt_ldi20;      case 156 : itype = FR30BF_INSN_EORM; goto extract_sfmt_andm;      case 157 : itype = FR30BF_INSN_EORH; goto extract_sfmt_andh;      case 158 : itype = FR30BF_INSN_EORB; goto extract_sfmt_andb;      case 159 :
+      case 152 : itype = FR30BF_INSN_BEORL;goto extract_sfmt_bandl;
+      case 153 : itype = FR30BF_INSN_BEORH;goto extract_sfmt_bandl;
+      case 154 : itype = FR30BF_INSN_EOR;goto extract_sfmt_and;
+      case 155 : itype = FR30BF_INSN_LDI20;goto extract_sfmt_ldi20;
+      case 156 : itype = FR30BF_INSN_EORM;goto extract_sfmt_andm;
+      case 157 : itype = FR30BF_INSN_EORH;goto extract_sfmt_andh;
+      case 158 : itype = FR30BF_INSN_EORB;goto extract_sfmt_andb;
+      case 159 :
         {
           unsigned int val = (((insn >> 4) & (15 << 0)));
           switch (val)
           {
-          case 0 : itype = FR30BF_INSN_JMPD; goto extract_sfmt_jmp;          case 1 : itype = FR30BF_INSN_CALLRD; goto extract_sfmt_callr;          case 2 : itype = FR30BF_INSN_RET_D; goto extract_sfmt_ret;          case 3 : itype = FR30BF_INSN_INTE; goto extract_sfmt_inte;          case 6 : itype = FR30BF_INSN_DIV3; goto extract_sfmt_div3;          case 7 : itype = FR30BF_INSN_DIV4S; goto extract_sfmt_div4s;          case 8 : itype = FR30BF_INSN_LDI32; goto extract_sfmt_ldi32;          case 9 : itype = FR30BF_INSN_LEAVE; goto extract_sfmt_leave;          case 10 : itype = FR30BF_INSN_NOP; goto extract_sfmt_bnod;          case 12 : itype = FR30BF_INSN_COPOP; goto extract_sfmt_copop;          case 13 : itype = FR30BF_INSN_COPLD; goto extract_sfmt_copop;          case 14 : itype = FR30BF_INSN_COPST; goto extract_sfmt_copop;          case 15 : itype = FR30BF_INSN_COPSV; goto extract_sfmt_copop;          default : itype = FR30BF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 0 : itype = FR30BF_INSN_JMPD;goto extract_sfmt_jmp;
+          case 1 : itype = FR30BF_INSN_CALLRD;goto extract_sfmt_callr;
+          case 2 : itype = FR30BF_INSN_RET_D;goto extract_sfmt_ret;
+          case 3 : itype = FR30BF_INSN_INTE;goto extract_sfmt_inte;
+          case 6 : itype = FR30BF_INSN_DIV3;goto extract_sfmt_div3;
+          case 7 : itype = FR30BF_INSN_DIV4S;goto extract_sfmt_div4s;
+          case 8 : itype = FR30BF_INSN_LDI32;goto extract_sfmt_ldi32;
+          case 9 : itype = FR30BF_INSN_LEAVE;goto extract_sfmt_leave;
+          case 10 : itype = FR30BF_INSN_NOP;goto extract_sfmt_bnod;
+          case 12 : itype = FR30BF_INSN_COPOP;goto extract_sfmt_copop;
+          case 13 : itype = FR30BF_INSN_COPLD;goto extract_sfmt_copop;
+          case 14 : itype = FR30BF_INSN_COPST;goto extract_sfmt_copop;
+          case 15 : itype = FR30BF_INSN_COPSV;goto extract_sfmt_copop;
+          default : itype = FR30BF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 160 : itype = FR30BF_INSN_ADDNI; goto extract_sfmt_addni;      case 161 : itype = FR30BF_INSN_ADDN2; goto extract_sfmt_addn2;      case 162 : itype = FR30BF_INSN_ADDN; goto extract_sfmt_addn;      case 163 : itype = FR30BF_INSN_ADDSP; goto extract_sfmt_addsp;      case 164 : itype = FR30BF_INSN_ADDI; goto extract_sfmt_addi;      case 165 : itype = FR30BF_INSN_ADD2; goto extract_sfmt_add2;      case 166 : itype = FR30BF_INSN_ADD; goto extract_sfmt_add;      case 167 : itype = FR30BF_INSN_ADDC; goto extract_sfmt_addc;      case 168 : itype = FR30BF_INSN_CMPI; goto extract_sfmt_cmpi;      case 169 : itype = FR30BF_INSN_CMP2; goto extract_sfmt_cmp2;      case 170 : itype = FR30BF_INSN_CMP; goto extract_sfmt_cmp;      case 171 : itype = FR30BF_INSN_MULU; goto extract_sfmt_mulu;      case 172 : itype = FR30BF_INSN_SUB; goto extract_sfmt_add;      case 173 : itype = FR30BF_INSN_SUBC; goto extract_sfmt_addc;      case 174 : itype = FR30BF_INSN_SUBN; goto extract_sfmt_addn;      case 175 : itype = FR30BF_INSN_MUL; goto extract_sfmt_mul;      case 176 : itype = FR30BF_INSN_LSRI; goto extract_sfmt_lsli;      case 177 : itype = FR30BF_INSN_LSR2; goto extract_sfmt_lsli;      case 178 : itype = FR30BF_INSN_LSR; goto extract_sfmt_lsl;      case 179 : itype = FR30BF_INSN_MOV2DR; goto extract_sfmt_mov2dr;      case 180 : itype = FR30BF_INSN_LSLI; goto extract_sfmt_lsli;      case 181 : itype = FR30BF_INSN_LSL2; goto extract_sfmt_lsli;      case 182 : itype = FR30BF_INSN_LSL; goto extract_sfmt_lsl;      case 183 : itype = FR30BF_INSN_MOVDR; goto extract_sfmt_movdr;      case 184 : itype = FR30BF_INSN_ASRI; goto extract_sfmt_lsli;      case 185 : itype = FR30BF_INSN_ASR2; goto extract_sfmt_lsli;      case 186 : itype = FR30BF_INSN_ASR; goto extract_sfmt_lsl;      case 187 : itype = FR30BF_INSN_MULUH; goto extract_sfmt_mulh;      case 188 : itype = FR30BF_INSN_LDRES; goto extract_sfmt_ldres;      case 189 : itype = FR30BF_INSN_STRES; goto extract_sfmt_ldres;      case 191 : itype = FR30BF_INSN_MULH; goto extract_sfmt_mulh;      case 192 : /* fall through */
+      case 160 : itype = FR30BF_INSN_ADDNI;goto extract_sfmt_addni;
+      case 161 : itype = FR30BF_INSN_ADDN2;goto extract_sfmt_addn2;
+      case 162 : itype = FR30BF_INSN_ADDN;goto extract_sfmt_addn;
+      case 163 : itype = FR30BF_INSN_ADDSP;goto extract_sfmt_addsp;
+      case 164 : itype = FR30BF_INSN_ADDI;goto extract_sfmt_addi;
+      case 165 : itype = FR30BF_INSN_ADD2;goto extract_sfmt_add2;
+      case 166 : itype = FR30BF_INSN_ADD;goto extract_sfmt_add;
+      case 167 : itype = FR30BF_INSN_ADDC;goto extract_sfmt_addc;
+      case 168 : itype = FR30BF_INSN_CMPI;goto extract_sfmt_cmpi;
+      case 169 : itype = FR30BF_INSN_CMP2;goto extract_sfmt_cmp2;
+      case 170 : itype = FR30BF_INSN_CMP;goto extract_sfmt_cmp;
+      case 171 : itype = FR30BF_INSN_MULU;goto extract_sfmt_mulu;
+      case 172 : itype = FR30BF_INSN_SUB;goto extract_sfmt_add;
+      case 173 : itype = FR30BF_INSN_SUBC;goto extract_sfmt_addc;
+      case 174 : itype = FR30BF_INSN_SUBN;goto extract_sfmt_addn;
+      case 175 : itype = FR30BF_INSN_MUL;goto extract_sfmt_mul;
+      case 176 : itype = FR30BF_INSN_LSRI;goto extract_sfmt_lsli;
+      case 177 : itype = FR30BF_INSN_LSR2;goto extract_sfmt_lsli;
+      case 178 : itype = FR30BF_INSN_LSR;goto extract_sfmt_lsl;
+      case 179 : itype = FR30BF_INSN_MOV2DR;goto extract_sfmt_mov2dr;
+      case 180 : itype = FR30BF_INSN_LSLI;goto extract_sfmt_lsli;
+      case 181 : itype = FR30BF_INSN_LSL2;goto extract_sfmt_lsli;
+      case 182 : itype = FR30BF_INSN_LSL;goto extract_sfmt_lsl;
+      case 183 : itype = FR30BF_INSN_MOVDR;goto extract_sfmt_movdr;
+      case 184 : itype = FR30BF_INSN_ASRI;goto extract_sfmt_lsli;
+      case 185 : itype = FR30BF_INSN_ASR2;goto extract_sfmt_lsli;
+      case 186 : itype = FR30BF_INSN_ASR;goto extract_sfmt_lsl;
+      case 187 : itype = FR30BF_INSN_MULUH;goto extract_sfmt_mulh;
+      case 188 : itype = FR30BF_INSN_LDRES;goto extract_sfmt_ldres;
+      case 189 : itype = FR30BF_INSN_STRES;goto extract_sfmt_ldres;
+      case 191 : itype = FR30BF_INSN_MULH;goto extract_sfmt_mulh;
+      case 192 : /* fall through */
       case 193 : /* fall through */
       case 194 : /* fall through */
       case 195 : /* fall through */
@@ -427,21 +557,56 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 204 : /* fall through */
       case 205 : /* fall through */
       case 206 : /* fall through */
-      case 207 : itype = FR30BF_INSN_LDI8; goto extract_sfmt_ldi8;      case 208 : /* fall through */
+      case 207 : itype = FR30BF_INSN_LDI8;goto extract_sfmt_ldi8;
+      case 208 : /* fall through */
       case 209 : /* fall through */
       case 210 : /* fall through */
       case 211 : /* fall through */
       case 212 : /* fall through */
       case 213 : /* fall through */
       case 214 : /* fall through */
-      case 215 : itype = FR30BF_INSN_CALL; goto extract_sfmt_call;      case 216 : /* fall through */
+      case 215 : itype = FR30BF_INSN_CALL;goto extract_sfmt_call;
+      case 216 : /* fall through */
       case 217 : /* fall through */
       case 218 : /* fall through */
       case 219 : /* fall through */
       case 220 : /* fall through */
       case 221 : /* fall through */
       case 222 : /* fall through */
-      case 223 : itype = FR30BF_INSN_CALLD; goto extract_sfmt_call;      case 224 : itype = FR30BF_INSN_BRA; goto extract_sfmt_brad;      case 225 : itype = FR30BF_INSN_BNO; goto extract_sfmt_bnod;      case 226 : itype = FR30BF_INSN_BEQ; goto extract_sfmt_beqd;      case 227 : itype = FR30BF_INSN_BNE; goto extract_sfmt_beqd;      case 228 : itype = FR30BF_INSN_BC; goto extract_sfmt_bcd;      case 229 : itype = FR30BF_INSN_BNC; goto extract_sfmt_bcd;      case 230 : itype = FR30BF_INSN_BN; goto extract_sfmt_bnd;      case 231 : itype = FR30BF_INSN_BP; goto extract_sfmt_bnd;      case 232 : itype = FR30BF_INSN_BV; goto extract_sfmt_bvd;      case 233 : itype = FR30BF_INSN_BNV; goto extract_sfmt_bvd;      case 234 : itype = FR30BF_INSN_BLT; goto extract_sfmt_bltd;      case 235 : itype = FR30BF_INSN_BGE; goto extract_sfmt_bltd;      case 236 : itype = FR30BF_INSN_BLE; goto extract_sfmt_bled;      case 237 : itype = FR30BF_INSN_BGT; goto extract_sfmt_bled;      case 238 : itype = FR30BF_INSN_BLS; goto extract_sfmt_blsd;      case 239 : itype = FR30BF_INSN_BHI; goto extract_sfmt_blsd;      case 240 : itype = FR30BF_INSN_BRAD; goto extract_sfmt_brad;      case 241 : itype = FR30BF_INSN_BNOD; goto extract_sfmt_bnod;      case 242 : itype = FR30BF_INSN_BEQD; goto extract_sfmt_beqd;      case 243 : itype = FR30BF_INSN_BNED; goto extract_sfmt_beqd;      case 244 : itype = FR30BF_INSN_BCD; goto extract_sfmt_bcd;      case 245 : itype = FR30BF_INSN_BNCD; goto extract_sfmt_bcd;      case 246 : itype = FR30BF_INSN_BND; goto extract_sfmt_bnd;      case 247 : itype = FR30BF_INSN_BPD; goto extract_sfmt_bnd;      case 248 : itype = FR30BF_INSN_BVD; goto extract_sfmt_bvd;      case 249 : itype = FR30BF_INSN_BNVD; goto extract_sfmt_bvd;      case 250 : itype = FR30BF_INSN_BLTD; goto extract_sfmt_bltd;      case 251 : itype = FR30BF_INSN_BGED; goto extract_sfmt_bltd;      case 252 : itype = FR30BF_INSN_BLED; goto extract_sfmt_bled;      case 253 : itype = FR30BF_INSN_BGTD; goto extract_sfmt_bled;      case 254 : itype = FR30BF_INSN_BLSD; goto extract_sfmt_blsd;      case 255 : itype = FR30BF_INSN_BHID; goto extract_sfmt_blsd;      default : itype = FR30BF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 223 : itype = FR30BF_INSN_CALLD;goto extract_sfmt_call;
+      case 224 : itype = FR30BF_INSN_BRA;goto extract_sfmt_brad;
+      case 225 : itype = FR30BF_INSN_BNO;goto extract_sfmt_bnod;
+      case 226 : itype = FR30BF_INSN_BEQ;goto extract_sfmt_beqd;
+      case 227 : itype = FR30BF_INSN_BNE;goto extract_sfmt_beqd;
+      case 228 : itype = FR30BF_INSN_BC;goto extract_sfmt_bcd;
+      case 229 : itype = FR30BF_INSN_BNC;goto extract_sfmt_bcd;
+      case 230 : itype = FR30BF_INSN_BN;goto extract_sfmt_bnd;
+      case 231 : itype = FR30BF_INSN_BP;goto extract_sfmt_bnd;
+      case 232 : itype = FR30BF_INSN_BV;goto extract_sfmt_bvd;
+      case 233 : itype = FR30BF_INSN_BNV;goto extract_sfmt_bvd;
+      case 234 : itype = FR30BF_INSN_BLT;goto extract_sfmt_bltd;
+      case 235 : itype = FR30BF_INSN_BGE;goto extract_sfmt_bltd;
+      case 236 : itype = FR30BF_INSN_BLE;goto extract_sfmt_bled;
+      case 237 : itype = FR30BF_INSN_BGT;goto extract_sfmt_bled;
+      case 238 : itype = FR30BF_INSN_BLS;goto extract_sfmt_blsd;
+      case 239 : itype = FR30BF_INSN_BHI;goto extract_sfmt_blsd;
+      case 240 : itype = FR30BF_INSN_BRAD;goto extract_sfmt_brad;
+      case 241 : itype = FR30BF_INSN_BNOD;goto extract_sfmt_bnod;
+      case 242 : itype = FR30BF_INSN_BEQD;goto extract_sfmt_beqd;
+      case 243 : itype = FR30BF_INSN_BNED;goto extract_sfmt_beqd;
+      case 244 : itype = FR30BF_INSN_BCD;goto extract_sfmt_bcd;
+      case 245 : itype = FR30BF_INSN_BNCD;goto extract_sfmt_bcd;
+      case 246 : itype = FR30BF_INSN_BND;goto extract_sfmt_bnd;
+      case 247 : itype = FR30BF_INSN_BPD;goto extract_sfmt_bnd;
+      case 248 : itype = FR30BF_INSN_BVD;goto extract_sfmt_bvd;
+      case 249 : itype = FR30BF_INSN_BNVD;goto extract_sfmt_bvd;
+      case 250 : itype = FR30BF_INSN_BLTD;goto extract_sfmt_bltd;
+      case 251 : itype = FR30BF_INSN_BGED;goto extract_sfmt_bltd;
+      case 252 : itype = FR30BF_INSN_BLED;goto extract_sfmt_bled;
+      case 253 : itype = FR30BF_INSN_BGTD;goto extract_sfmt_bled;
+      case 254 : itype = FR30BF_INSN_BLSD;goto extract_sfmt_blsd;
+      case 255 : itype = FR30BF_INSN_BHID;goto extract_sfmt_blsd;
+      default : itype = FR30BF_INSN_X_INVALID; goto extract_sfmt_empty;
       }
     }
   }
@@ -464,6 +629,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_add:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add.f
     UINT f_Rj;
     UINT f_Ri;
@@ -494,6 +660,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addi:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addi.f
     UINT f_u4;
     UINT f_Ri;
@@ -522,6 +689,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_add2:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add2.f
     SI f_m4;
     UINT f_Ri;
@@ -550,6 +718,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addc:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add.f
     UINT f_Rj;
     UINT f_Ri;
@@ -580,6 +749,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addn:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add.f
     UINT f_Rj;
     UINT f_Ri;
@@ -610,6 +780,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addni:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addi.f
     UINT f_u4;
     UINT f_Ri;
@@ -638,6 +809,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addn2:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add2.f
     SI f_m4;
     UINT f_Ri;
@@ -666,6 +838,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_cmp:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_str13.f
     UINT f_Rj;
     UINT f_Ri;
@@ -695,6 +868,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_cmpi:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addi.f
     UINT f_u4;
     UINT f_Ri;
@@ -722,6 +896,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_cmp2:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add2.f
     SI f_m4;
     UINT f_Ri;
@@ -749,6 +924,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_and:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add.f
     UINT f_Rj;
     UINT f_Ri;
@@ -779,6 +955,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_andm:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_str13.f
     UINT f_Rj;
     UINT f_Ri;
@@ -808,6 +985,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_andh:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_str13.f
     UINT f_Rj;
     UINT f_Ri;
@@ -837,6 +1015,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_andb:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_str13.f
     UINT f_Rj;
     UINT f_Ri;
@@ -866,6 +1045,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bandl:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addi.f
     UINT f_u4;
     UINT f_Ri;
@@ -893,6 +1073,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_btstl:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addi.f
     UINT f_u4;
     UINT f_Ri;
@@ -920,6 +1101,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_mul:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_str13.f
     UINT f_Rj;
     UINT f_Ri;
@@ -949,6 +1131,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_mulu:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_str13.f
     UINT f_Rj;
     UINT f_Ri;
@@ -978,6 +1161,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_mulh:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_str13.f
     UINT f_Rj;
     UINT f_Ri;
@@ -1007,6 +1191,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_div0s:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_mov2dr.f
     UINT f_Ri;
 
@@ -1044,6 +1229,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_div1:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_mov2dr.f
     UINT f_Ri;
 
@@ -1068,6 +1254,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_div2:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_mov2dr.f
     UINT f_Ri;
 
@@ -1118,6 +1305,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_lsl:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add.f
     UINT f_Rj;
     UINT f_Ri;
@@ -1148,6 +1336,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_lsli:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addi.f
     UINT f_u4;
     UINT f_Ri;
@@ -1176,6 +1365,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ldi8:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_ldi8.f
     UINT f_i8;
     UINT f_Ri;
@@ -1203,6 +1393,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ldi20:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_ldi20.f
     UINT f_i20_16;
     UINT f_i20_4;
@@ -1239,6 +1430,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ldi32:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_ldi32.f
     UINT f_i32;
     UINT f_Ri;
@@ -1271,6 +1463,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ld:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_ldr13.f
     UINT f_Rj;
     UINT f_Ri;
@@ -1297,9 +1490,70 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
+ extract_sfmt_lduh:
+  {
+    const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldr13.f
+    UINT f_Rj;
+    UINT f_Ri;
+
+    f_Rj = EXTRACT_MSB0_UINT (insn, 16, 8, 4);
+    f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_Rj) = f_Rj;
+  FLD (f_Ri) = f_Ri;
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lduh", "f_Rj 0x%x", 'x', f_Rj, "f_Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Rj) = f_Rj;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldub:
+  {
+    const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldr13.f
+    UINT f_Rj;
+    UINT f_Ri;
+
+    f_Rj = EXTRACT_MSB0_UINT (insn, 16, 8, 4);
+    f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_Rj) = f_Rj;
+  FLD (f_Ri) = f_Ri;
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldub", "f_Rj 0x%x", 'x', f_Rj, "f_Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Rj) = f_Rj;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
  extract_sfmt_ldr13:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_ldr13.f
     UINT f_Rj;
     UINT f_Ri;
@@ -1319,7 +1573,69 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   if (PROFILE_MODEL_P (current_cpu))
     {
       FLD (in_Rj) = f_Rj;
-      FLD (in_h_gr_13) = 13;
+      FLD (in_h_gr_SI_13) = 13;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldr13uh:
+  {
+    const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldr13.f
+    UINT f_Rj;
+    UINT f_Ri;
+
+    f_Rj = EXTRACT_MSB0_UINT (insn, 16, 8, 4);
+    f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_Rj) = f_Rj;
+  FLD (f_Ri) = f_Ri;
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldr13uh", "f_Rj 0x%x", 'x', f_Rj, "f_Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Rj) = f_Rj;
+      FLD (in_h_gr_SI_13) = 13;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldr13ub:
+  {
+    const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldr13.f
+    UINT f_Rj;
+    UINT f_Ri;
+
+    f_Rj = EXTRACT_MSB0_UINT (insn, 16, 8, 4);
+    f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_Rj) = f_Rj;
+  FLD (f_Ri) = f_Ri;
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldr13ub", "f_Rj 0x%x", 'x', f_Rj, "f_Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Rj) = f_Rj;
+      FLD (in_h_gr_SI_13) = 13;
       FLD (out_Ri) = f_Ri;
     }
 #endif
@@ -1330,6 +1646,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ldr14:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_ldr14.f
     SI f_disp10;
     UINT f_Ri;
@@ -1347,7 +1664,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (in_h_gr_14) = 14;
+      FLD (in_h_gr_SI_14) = 14;
       FLD (out_Ri) = f_Ri;
     }
 #endif
@@ -1358,6 +1675,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ldr14uh:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_ldr14uh.f
     SI f_disp9;
     UINT f_Ri;
@@ -1375,7 +1693,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (in_h_gr_14) = 14;
+      FLD (in_h_gr_SI_14) = 14;
       FLD (out_Ri) = f_Ri;
     }
 #endif
@@ -1386,6 +1704,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ldr14ub:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_ldr14ub.f
     INT f_disp8;
     UINT f_Ri;
@@ -1403,7 +1722,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (in_h_gr_14) = 14;
+      FLD (in_h_gr_SI_14) = 14;
       FLD (out_Ri) = f_Ri;
     }
 #endif
@@ -1414,6 +1733,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ldr15:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_ldr15.f
     USI f_udisp6;
     UINT f_Ri;
@@ -1431,7 +1751,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (in_h_gr_15) = 15;
+      FLD (in_h_gr_SI_15) = 15;
       FLD (out_Ri) = f_Ri;
     }
 #endif
@@ -1442,6 +1762,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ldr15gr:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_ldr15gr.f
     UINT f_Ri;
 
@@ -1456,9 +1777,9 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (in_h_gr_15) = 15;
+      FLD (in_h_gr_SI_15) = 15;
       FLD (out_Ri) = f_Ri;
-      FLD (out_h_gr_15) = 15;
+      FLD (out_h_gr_SI_15) = 15;
     }
 #endif
 #undef FLD
@@ -1468,6 +1789,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ldr15dr:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_ldr15dr.f
     UINT f_Rs2;
 
@@ -1481,8 +1803,8 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (in_h_gr_15) = 15;
-      FLD (out_h_gr_15) = 15;
+      FLD (in_h_gr_SI_15) = 15;
+      FLD (out_h_gr_SI_15) = 15;
     }
 #endif
 #undef FLD
@@ -1502,8 +1824,8 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (in_h_gr_15) = 15;
-      FLD (out_h_gr_15) = 15;
+      FLD (in_h_gr_SI_15) = 15;
+      FLD (out_h_gr_SI_15) = 15;
     }
 #endif
 #undef FLD
@@ -1513,6 +1835,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_st:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_str13.f
     UINT f_Rj;
     UINT f_Ri;
@@ -1539,9 +1862,70 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
+ extract_sfmt_sth:
+  {
+    const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_str13.f
+    UINT f_Rj;
+    UINT f_Ri;
+
+    f_Rj = EXTRACT_MSB0_UINT (insn, 16, 8, 4);
+    f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_Ri) = f_Ri;
+  FLD (f_Rj) = f_Rj;
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth", "f_Ri 0x%x", 'x', f_Ri, "f_Rj 0x%x", 'x', f_Rj, "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (in_Rj) = f_Rj;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_stb:
+  {
+    const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_str13.f
+    UINT f_Rj;
+    UINT f_Ri;
+
+    f_Rj = EXTRACT_MSB0_UINT (insn, 16, 8, 4);
+    f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_Ri) = f_Ri;
+  FLD (f_Rj) = f_Rj;
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "f_Ri 0x%x", 'x', f_Ri, "f_Rj 0x%x", 'x', f_Rj, "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (in_Rj) = f_Rj;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
  extract_sfmt_str13:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_str13.f
     UINT f_Rj;
     UINT f_Ri;
@@ -1562,7 +1946,69 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
     {
       FLD (in_Ri) = f_Ri;
       FLD (in_Rj) = f_Rj;
-      FLD (in_h_gr_13) = 13;
+      FLD (in_h_gr_SI_13) = 13;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_str13h:
+  {
+    const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_str13.f
+    UINT f_Rj;
+    UINT f_Ri;
+
+    f_Rj = EXTRACT_MSB0_UINT (insn, 16, 8, 4);
+    f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_Ri) = f_Ri;
+  FLD (f_Rj) = f_Rj;
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_str13h", "f_Ri 0x%x", 'x', f_Ri, "f_Rj 0x%x", 'x', f_Rj, "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (in_Rj) = f_Rj;
+      FLD (in_h_gr_SI_13) = 13;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_str13b:
+  {
+    const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_str13.f
+    UINT f_Rj;
+    UINT f_Ri;
+
+    f_Rj = EXTRACT_MSB0_UINT (insn, 16, 8, 4);
+    f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_Ri) = f_Ri;
+  FLD (f_Rj) = f_Rj;
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_str13b", "f_Ri 0x%x", 'x', f_Ri, "f_Rj 0x%x", 'x', f_Rj, "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (in_Rj) = f_Rj;
+      FLD (in_h_gr_SI_13) = 13;
     }
 #endif
 #undef FLD
@@ -1572,6 +2018,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_str14:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_str14.f
     SI f_disp10;
     UINT f_Ri;
@@ -1590,7 +2037,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   if (PROFILE_MODEL_P (current_cpu))
     {
       FLD (in_Ri) = f_Ri;
-      FLD (in_h_gr_14) = 14;
+      FLD (in_h_gr_SI_14) = 14;
     }
 #endif
 #undef FLD
@@ -1600,6 +2047,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_str14h:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_str14h.f
     SI f_disp9;
     UINT f_Ri;
@@ -1618,7 +2066,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   if (PROFILE_MODEL_P (current_cpu))
     {
       FLD (in_Ri) = f_Ri;
-      FLD (in_h_gr_14) = 14;
+      FLD (in_h_gr_SI_14) = 14;
     }
 #endif
 #undef FLD
@@ -1628,6 +2076,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_str14b:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_str14b.f
     INT f_disp8;
     UINT f_Ri;
@@ -1646,7 +2095,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   if (PROFILE_MODEL_P (current_cpu))
     {
       FLD (in_Ri) = f_Ri;
-      FLD (in_h_gr_14) = 14;
+      FLD (in_h_gr_SI_14) = 14;
     }
 #endif
 #undef FLD
@@ -1656,6 +2105,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_str15:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_str15.f
     USI f_udisp6;
     UINT f_Ri;
@@ -1674,7 +2124,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   if (PROFILE_MODEL_P (current_cpu))
     {
       FLD (in_Ri) = f_Ri;
-      FLD (in_h_gr_15) = 15;
+      FLD (in_h_gr_SI_15) = 15;
     }
 #endif
 #undef FLD
@@ -1684,6 +2134,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_str15gr:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_str15gr.f
     UINT f_Ri;
 
@@ -1699,8 +2150,8 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   if (PROFILE_MODEL_P (current_cpu))
     {
       FLD (in_Ri) = f_Ri;
-      FLD (in_h_gr_15) = 15;
-      FLD (out_h_gr_15) = 15;
+      FLD (in_h_gr_SI_15) = 15;
+      FLD (out_h_gr_SI_15) = 15;
     }
 #endif
 #undef FLD
@@ -1710,6 +2161,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_str15dr:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_ldr15dr.f
     UINT f_Rs2;
 
@@ -1723,8 +2175,8 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (in_h_gr_15) = 15;
-      FLD (out_h_gr_15) = 15;
+      FLD (in_h_gr_SI_15) = 15;
+      FLD (out_h_gr_SI_15) = 15;
     }
 #endif
 #undef FLD
@@ -1744,8 +2196,8 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (in_h_gr_15) = 15;
-      FLD (out_h_gr_15) = 15;
+      FLD (in_h_gr_SI_15) = 15;
+      FLD (out_h_gr_SI_15) = 15;
     }
 #endif
 #undef FLD
@@ -1755,6 +2207,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_mov:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_ldr13.f
     UINT f_Rj;
     UINT f_Ri;
@@ -1784,6 +2237,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_movdr:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_movdr.f
     UINT f_Rs1;
     UINT f_Ri;
@@ -1811,6 +2265,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_movps:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_movdr.f
     UINT f_Ri;
 
@@ -1835,6 +2290,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_mov2dr:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_mov2dr.f
     UINT f_Rs1;
     UINT f_Ri;
@@ -1862,6 +2318,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_mov2ps:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_mov2dr.f
     UINT f_Ri;
 
@@ -1886,6 +2343,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_jmp:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_mov2dr.f
     UINT f_Ri;
 
@@ -1910,6 +2368,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_callr:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_mov2dr.f
     UINT f_Ri;
 
@@ -1934,6 +2393,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_call:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_call.f
     SI f_rel12;
 
@@ -1975,6 +2435,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_int:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_int.f
     UINT f_u8;
 
@@ -2035,6 +2496,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_brad:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_brad.f
     SI f_rel9;
 
@@ -2070,6 +2532,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_beqd:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_brad.f
     SI f_rel9;
 
@@ -2092,6 +2555,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bcd:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_brad.f
     SI f_rel9;
 
@@ -2114,6 +2578,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bnd:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_brad.f
     SI f_rel9;
 
@@ -2136,6 +2601,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bvd:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_brad.f
     SI f_rel9;
 
@@ -2158,6 +2624,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bltd:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_brad.f
     SI f_rel9;
 
@@ -2180,6 +2647,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bled:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_brad.f
     SI f_rel9;
 
@@ -2202,6 +2670,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_blsd:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_brad.f
     SI f_rel9;
 
@@ -2224,6 +2693,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_dmovr13:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_dmovr13pi.f
     USI f_dir10;
 
@@ -2237,7 +2707,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (in_h_gr_13) = 13;
+      FLD (in_h_gr_SI_13) = 13;
     }
 #endif
 #undef FLD
@@ -2247,6 +2717,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_dmovr13h:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_dmovr13pih.f
     USI f_dir9;
 
@@ -2260,7 +2731,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (in_h_gr_13) = 13;
+      FLD (in_h_gr_SI_13) = 13;
     }
 #endif
 #undef FLD
@@ -2270,6 +2741,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_dmovr13b:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_dmovr13pib.f
     UINT f_dir8;
 
@@ -2283,7 +2755,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (in_h_gr_13) = 13;
+      FLD (in_h_gr_SI_13) = 13;
     }
 #endif
 #undef FLD
@@ -2293,6 +2765,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_dmovr13pi:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_dmovr13pi.f
     USI f_dir10;
 
@@ -2306,8 +2779,8 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (in_h_gr_13) = 13;
-      FLD (out_h_gr_13) = 13;
+      FLD (in_h_gr_SI_13) = 13;
+      FLD (out_h_gr_SI_13) = 13;
     }
 #endif
 #undef FLD
@@ -2317,6 +2790,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_dmovr13pih:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_dmovr13pih.f
     USI f_dir9;
 
@@ -2330,8 +2804,8 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (in_h_gr_13) = 13;
-      FLD (out_h_gr_13) = 13;
+      FLD (in_h_gr_SI_13) = 13;
+      FLD (out_h_gr_SI_13) = 13;
     }
 #endif
 #undef FLD
@@ -2341,6 +2815,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_dmovr13pib:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_dmovr13pib.f
     UINT f_dir8;
 
@@ -2354,8 +2829,8 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (in_h_gr_13) = 13;
-      FLD (out_h_gr_13) = 13;
+      FLD (in_h_gr_SI_13) = 13;
+      FLD (out_h_gr_SI_13) = 13;
     }
 #endif
 #undef FLD
@@ -2365,6 +2840,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_dmovr15pi:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_dmovr15pi.f
     USI f_dir10;
 
@@ -2378,8 +2854,8 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (in_h_gr_15) = 15;
-      FLD (out_h_gr_15) = 15;
+      FLD (in_h_gr_SI_15) = 15;
+      FLD (out_h_gr_SI_15) = 15;
     }
 #endif
 #undef FLD
@@ -2389,6 +2865,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_dmov2r13:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_dmovr13pi.f
     USI f_dir10;
 
@@ -2402,7 +2879,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (out_h_gr_13) = 13;
+      FLD (out_h_gr_SI_13) = 13;
     }
 #endif
 #undef FLD
@@ -2412,6 +2889,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_dmov2r13h:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_dmovr13pih.f
     USI f_dir9;
 
@@ -2425,7 +2903,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (out_h_gr_13) = 13;
+      FLD (out_h_gr_SI_13) = 13;
     }
 #endif
 #undef FLD
@@ -2435,6 +2913,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_dmov2r13b:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_dmovr13pib.f
     UINT f_dir8;
 
@@ -2448,7 +2927,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (out_h_gr_13) = 13;
+      FLD (out_h_gr_SI_13) = 13;
     }
 #endif
 #undef FLD
@@ -2458,6 +2937,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_dmov2r13pi:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_dmovr13pi.f
     USI f_dir10;
 
@@ -2471,8 +2951,8 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (in_h_gr_13) = 13;
-      FLD (out_h_gr_13) = 13;
+      FLD (in_h_gr_SI_13) = 13;
+      FLD (out_h_gr_SI_13) = 13;
     }
 #endif
 #undef FLD
@@ -2482,6 +2962,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_dmov2r13pih:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_dmovr13pih.f
     USI f_dir9;
 
@@ -2495,8 +2976,8 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (in_h_gr_13) = 13;
-      FLD (out_h_gr_13) = 13;
+      FLD (in_h_gr_SI_13) = 13;
+      FLD (out_h_gr_SI_13) = 13;
     }
 #endif
 #undef FLD
@@ -2506,6 +2987,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_dmov2r13pib:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_dmovr13pib.f
     UINT f_dir8;
 
@@ -2519,8 +3001,8 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (in_h_gr_13) = 13;
-      FLD (out_h_gr_13) = 13;
+      FLD (in_h_gr_SI_13) = 13;
+      FLD (out_h_gr_SI_13) = 13;
     }
 #endif
 #undef FLD
@@ -2530,6 +3012,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_dmov2r15pd:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_dmovr15pi.f
     USI f_dir10;
 
@@ -2543,8 +3026,8 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (in_h_gr_15) = 15;
-      FLD (out_h_gr_15) = 15;
+      FLD (in_h_gr_SI_15) = 15;
+      FLD (out_h_gr_SI_15) = 15;
     }
 #endif
 #undef FLD
@@ -2554,6 +3037,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ldres:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add2.f
     UINT f_Ri;
 
@@ -2595,6 +3079,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_andccr:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_int.f
     UINT f_u8;
 
@@ -2611,6 +3096,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_stilm:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_int.f
     UINT f_u8;
 
@@ -2627,6 +3113,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addsp:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_addsp.f
     SI f_s10;
 
@@ -2640,8 +3127,8 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (in_h_gr_15) = 15;
-      FLD (out_h_gr_15) = 15;
+      FLD (in_h_gr_SI_15) = 15;
+      FLD (out_h_gr_SI_15) = 15;
     }
 #endif
 #undef FLD
@@ -2651,6 +3138,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_extsb:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add2.f
     UINT f_Ri;
 
@@ -2676,6 +3164,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_extub:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add2.f
     UINT f_Ri;
 
@@ -2701,6 +3190,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_extsh:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add2.f
     UINT f_Ri;
 
@@ -2726,6 +3216,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_extuh:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add2.f
     UINT f_Ri;
 
@@ -2751,6 +3242,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ldm0:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_ldm0.f
     UINT f_reglist_low_ld;
 
@@ -2764,16 +3256,16 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (in_h_gr_15) = 15;
-      FLD (out_h_gr_0) = 0;
-      FLD (out_h_gr_1) = 1;
-      FLD (out_h_gr_15) = 15;
-      FLD (out_h_gr_2) = 2;
-      FLD (out_h_gr_3) = 3;
-      FLD (out_h_gr_4) = 4;
-      FLD (out_h_gr_5) = 5;
-      FLD (out_h_gr_6) = 6;
-      FLD (out_h_gr_7) = 7;
+      FLD (in_h_gr_SI_15) = 15;
+      FLD (out_h_gr_SI_0) = 0;
+      FLD (out_h_gr_SI_1) = 1;
+      FLD (out_h_gr_SI_15) = 15;
+      FLD (out_h_gr_SI_2) = 2;
+      FLD (out_h_gr_SI_3) = 3;
+      FLD (out_h_gr_SI_4) = 4;
+      FLD (out_h_gr_SI_5) = 5;
+      FLD (out_h_gr_SI_6) = 6;
+      FLD (out_h_gr_SI_7) = 7;
     }
 #endif
 #undef FLD
@@ -2783,6 +3275,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ldm1:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_ldm1.f
     UINT f_reglist_hi_ld;
 
@@ -2796,15 +3289,15 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (in_h_gr_15) = 15;
-      FLD (out_h_gr_10) = 10;
-      FLD (out_h_gr_11) = 11;
-      FLD (out_h_gr_12) = 12;
-      FLD (out_h_gr_13) = 13;
-      FLD (out_h_gr_14) = 14;
-      FLD (out_h_gr_15) = 15;
-      FLD (out_h_gr_8) = 8;
-      FLD (out_h_gr_9) = 9;
+      FLD (in_h_gr_SI_15) = 15;
+      FLD (out_h_gr_SI_10) = 10;
+      FLD (out_h_gr_SI_11) = 11;
+      FLD (out_h_gr_SI_12) = 12;
+      FLD (out_h_gr_SI_13) = 13;
+      FLD (out_h_gr_SI_14) = 14;
+      FLD (out_h_gr_SI_15) = 15;
+      FLD (out_h_gr_SI_8) = 8;
+      FLD (out_h_gr_SI_9) = 9;
     }
 #endif
 #undef FLD
@@ -2814,6 +3307,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_stm0:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_stm0.f
     UINT f_reglist_low_st;
 
@@ -2827,16 +3321,16 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (in_h_gr_0) = 0;
-      FLD (in_h_gr_1) = 1;
-      FLD (in_h_gr_15) = 15;
-      FLD (in_h_gr_2) = 2;
-      FLD (in_h_gr_3) = 3;
-      FLD (in_h_gr_4) = 4;
-      FLD (in_h_gr_5) = 5;
-      FLD (in_h_gr_6) = 6;
-      FLD (in_h_gr_7) = 7;
-      FLD (out_h_gr_15) = 15;
+      FLD (in_h_gr_SI_0) = 0;
+      FLD (in_h_gr_SI_1) = 1;
+      FLD (in_h_gr_SI_15) = 15;
+      FLD (in_h_gr_SI_2) = 2;
+      FLD (in_h_gr_SI_3) = 3;
+      FLD (in_h_gr_SI_4) = 4;
+      FLD (in_h_gr_SI_5) = 5;
+      FLD (in_h_gr_SI_6) = 6;
+      FLD (in_h_gr_SI_7) = 7;
+      FLD (out_h_gr_SI_15) = 15;
     }
 #endif
 #undef FLD
@@ -2846,6 +3340,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_stm1:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_stm1.f
     UINT f_reglist_hi_st;
 
@@ -2859,15 +3354,15 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (in_h_gr_10) = 10;
-      FLD (in_h_gr_11) = 11;
-      FLD (in_h_gr_12) = 12;
-      FLD (in_h_gr_13) = 13;
-      FLD (in_h_gr_14) = 14;
-      FLD (in_h_gr_15) = 15;
-      FLD (in_h_gr_8) = 8;
-      FLD (in_h_gr_9) = 9;
-      FLD (out_h_gr_15) = 15;
+      FLD (in_h_gr_SI_10) = 10;
+      FLD (in_h_gr_SI_11) = 11;
+      FLD (in_h_gr_SI_12) = 12;
+      FLD (in_h_gr_SI_13) = 13;
+      FLD (in_h_gr_SI_14) = 14;
+      FLD (in_h_gr_SI_15) = 15;
+      FLD (in_h_gr_SI_8) = 8;
+      FLD (in_h_gr_SI_9) = 9;
+      FLD (out_h_gr_SI_15) = 15;
     }
 #endif
 #undef FLD
@@ -2877,6 +3372,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_enter:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_enter.f
     USI f_u10;
 
@@ -2890,10 +3386,10 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (in_h_gr_14) = 14;
-      FLD (in_h_gr_15) = 15;
-      FLD (out_h_gr_14) = 14;
-      FLD (out_h_gr_15) = 15;
+      FLD (in_h_gr_SI_14) = 14;
+      FLD (in_h_gr_SI_15) = 15;
+      FLD (out_h_gr_SI_14) = 14;
+      FLD (out_h_gr_SI_15) = 15;
     }
 #endif
 #undef FLD
@@ -2913,10 +3409,10 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
-      FLD (in_h_gr_14) = 14;
-      FLD (in_h_gr_15) = 15;
-      FLD (out_h_gr_14) = 14;
-      FLD (out_h_gr_15) = 15;
+      FLD (in_h_gr_SI_14) = 14;
+      FLD (in_h_gr_SI_15) = 15;
+      FLD (out_h_gr_SI_14) = 14;
+      FLD (out_h_gr_SI_15) = 15;
     }
 #endif
 #undef FLD
@@ -2926,6 +3422,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_xchb:
   {
     const IDESC *idesc = &fr30bf_insn_data[itype];
+    CGEN_INSN_INT insn = base_insn;
 #define FLD(f) abuf->fields.sfmt_add.f
     UINT f_Rj;
     UINT f_Ri;
diff --git a/sim/fr30/decode.h b/sim/fr30/decode.h
index 4cc1ffb..65f6181 100644
--- a/sim/fr30/decode.h
+++ b/sim/fr30/decode.h
@@ -2,9 +2,9 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
 
-This file is part of the GNU Simulators.
+This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
@@ -89,9 +89,11 @@ typedef enum fr30bf_sfmt_type {
  , FR30BF_SFMT_DIV0S, FR30BF_SFMT_DIV0U, FR30BF_SFMT_DIV1, FR30BF_SFMT_DIV2
  , FR30BF_SFMT_DIV3, FR30BF_SFMT_DIV4S, FR30BF_SFMT_LSL, FR30BF_SFMT_LSLI
  , FR30BF_SFMT_LDI8, FR30BF_SFMT_LDI20, FR30BF_SFMT_LDI32, FR30BF_SFMT_LD
- , FR30BF_SFMT_LDR13, FR30BF_SFMT_LDR14, FR30BF_SFMT_LDR14UH, FR30BF_SFMT_LDR14UB
+ , FR30BF_SFMT_LDUH, FR30BF_SFMT_LDUB, FR30BF_SFMT_LDR13, FR30BF_SFMT_LDR13UH
+ , FR30BF_SFMT_LDR13UB, FR30BF_SFMT_LDR14, FR30BF_SFMT_LDR14UH, FR30BF_SFMT_LDR14UB
  , FR30BF_SFMT_LDR15, FR30BF_SFMT_LDR15GR, FR30BF_SFMT_LDR15DR, FR30BF_SFMT_LDR15PS
- , FR30BF_SFMT_ST, FR30BF_SFMT_STR13, FR30BF_SFMT_STR14, FR30BF_SFMT_STR14H
+ , FR30BF_SFMT_ST, FR30BF_SFMT_STH, FR30BF_SFMT_STB, FR30BF_SFMT_STR13
+ , FR30BF_SFMT_STR13H, FR30BF_SFMT_STR13B, FR30BF_SFMT_STR14, FR30BF_SFMT_STR14H
  , FR30BF_SFMT_STR14B, FR30BF_SFMT_STR15, FR30BF_SFMT_STR15GR, FR30BF_SFMT_STR15DR
  , FR30BF_SFMT_STR15PS, FR30BF_SFMT_MOV, FR30BF_SFMT_MOVDR, FR30BF_SFMT_MOVPS
  , FR30BF_SFMT_MOV2DR, FR30BF_SFMT_MOV2PS, FR30BF_SFMT_JMP, FR30BF_SFMT_CALLR
diff --git a/sim/fr30/model.c b/sim/fr30/model.c
index 611d40f..a90f340 100644
--- a/sim/fr30/model.c
+++ b/sim/fr30/model.c
@@ -2,9 +2,9 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
 
-This file is part of the GNU Simulators.
+This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
@@ -3984,7 +3984,7 @@ fr30_init_cpu (SIM_CPU *cpu)
   CPU_PC_FETCH (cpu) = fr30bf_h_pc_get;
   CPU_PC_STORE (cpu) = fr30bf_h_pc_set;
   CPU_GET_IDATA (cpu) = fr30bf_get_idata;
-  CPU_MAX_INSNS (cpu) = FR30BF_INSN_MAX;
+  CPU_MAX_INSNS (cpu) = FR30BF_INSN_XCHB + 1;
   CPU_INSN_NAME (cpu) = cgen_insn_name;
   CPU_FULL_ENGINE_FN (cpu) = fr30bf_engine_run_full;
 #if WITH_FAST
diff --git a/sim/fr30/sem-switch.c b/sim/fr30/sem-switch.c
index 7dc7f7f..837e29f 100644
--- a/sim/fr30/sem-switch.c
+++ b/sim/fr30/sem-switch.c
@@ -2,9 +2,9 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
 
-This file is part of the GNU Simulators.
+This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
diff --git a/sim/fr30/sem.c b/sim/fr30/sem.c
index fb5893c..fb90a55 100644
--- a/sim/fr30/sem.c
+++ b/sim/fr30/sem.c
@@ -2,9 +2,9 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
 
-This file is part of the GNU Simulators.
+This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by