* allinsn.exp: Add new tests.

	* bandor.s: New file.
	* bandornot.s: New file.
	* bclr.s: New file.
	* bld.s: New file.
	* bldnot.s: New file.
	* bset.s: New file.
	* bst.s: New file.
	* bxor.s: New file.
	* clip.s: New file.
	* div.s: New file.
	* fail.s: New file, make sure fail works.
	* fsca.s: New file.
	* fsrra.s: New file.
	* mov.s: New file.
	* mulr.s: New file.
	* pass.s: New file, make sure pass works.
	* pushpop.s: New file.
	* resbank.s: New file.
	* testutils.inc (bf8k, bt8k, assertmem): New macros.

22 files changed, 2280 insertions, 4 deletions

diff --git a/sim/testsuite/sim/sh/ChangeLog b/sim/testsuite/sim/sh/ChangeLog
index e3fecbd..b1ad5ca 100644
--- a/sim/testsuite/sim/sh/ChangeLog
+++ b/sim/testsuite/sim/sh/ChangeLog
@@ -1,3 +1,27 @@
+2004-09-08  Michael Snyder  <msnyder@redhat.com>
+
+	Commited by Corinna Vinschen <vinschen@redhat.com>
+	* allinsn.exp: Add new tests.
+	* bandor.s: New file.
+	* bandornot.s: New file.
+	* bclr.s: New file.
+	* bld.s: New file.
+	* bldnot.s: New file.
+	* bset.s: New file.
+	* bst.s: New file.
+	* bxor.s: New file.
+	* clip.s: New file.
+	* div.s: New file.
+	* fail.s: New file, make sure fail works.
+	* fsca.s: New file.
+	* fsrra.s: New file.
+	* mov.s: New file.
+	* mulr.s: New file.
+	* pass.s: New file, make sure pass works.
+	* pushpop.s: New file.
+	* resbank.s: New file.
+	* testutils.inc (bf8k, bt8k, assertmem): New macros.
+
 2004-02-12  Michael Snyder  <msnyder@redhat.com>
 
 	* and.s, movi.s, sett.s: New files.
diff --git a/sim/testsuite/sim/sh/allinsn.exp b/sim/testsuite/sim/sh/allinsn.exp
index 0ec39f5..d7e9ddc 100644
--- a/sim/testsuite/sim/sh/allinsn.exp
+++ b/sim/testsuite/sim/sh/allinsn.exp
@@ -5,6 +5,16 @@ set all "sh shdsp"
 if [istarget sh-*elf] {
     run_sim_test add.s    $all
     run_sim_test and.s    $all
+    run_sim_test bandor.s sh
+    run_sim_test bandornot.s sh
+    run_sim_test bclr.s   sh
+    run_sim_test bld.s    sh
+    run_sim_test bldnot.s sh
+    run_sim_test bset.s   sh
+    run_sim_test bst.s    sh
+    run_sim_test bxor.s   sh
+    run_sim_test clip.s   sh
+    run_sim_test div.s    sh
     run_sim_test dmxy.s   shdsp
     run_sim_test fabs.s   sh
     run_sim_test fadd.s   sh
@@ -32,10 +42,12 @@ if [istarget sh-*elf] {
     run_sim_test loop.s   shdsp
     run_sim_test macl.s   sh
     run_sim_test macw.s   sh
+    run_sim_test mov.s    $all
     run_sim_test movi.s   $all
     run_sim_test movli.s  $all
     run_sim_test movua.s  $all
     run_sim_test movxy.s  shdsp
+    run_sim_test mulr.s   sh
     run_sim_test pabs.s   shdsp
     run_sim_test paddc.s  shdsp
     run_sim_test padd.s   shdsp
@@ -52,7 +64,9 @@ if [istarget sh-*elf] {
     run_sim_test pshlr.s  shdsp
     run_sim_test psub.s   shdsp
     run_sim_test pswap.s  shdsp
-    run_sim_test sett.s   $all
+    run_sim_test pushpop.s sh
+    run_sim_test resbank.s sh
+    run_sim_test sett.s   sh
     run_sim_test shll.s   $all
     run_sim_test shll2.s  $all
     run_sim_test shll8.s  $all
diff --git a/sim/testsuite/sim/sh/bandor.s b/sim/testsuite/sim/sh/bandor.s
new file mode 100644
index 0000000..9ada485
--- /dev/null
+++ b/sim/testsuite/sim/sh/bandor.s
@@ -0,0 +1,120 @@
+# sh testcase for band, bor
+# mach:	 all
+# as(sh):	-defsym sim_cpu=0
+# as(shdsp):	-defsym sim_cpu=1 -dsp 
+
+	.include "testutils.inc"
+
+	.align 2
+_x:	.long	0xa5a5a5a5
+
+	start
+
+bandor_b_imm_disp12_reg:
+	set_grs_a5a5
+	# Make sure T is true to start.
+	sett
+
+	mov.l	x, r1
+
+	band.b	#0, @(3, r1)
+	bf8k	mfail
+	bor.b	#1, @(3, r1)
+	bf8k	mfail
+	band.b	#2, @(3, r1)
+	bf8k	mfail
+	bor.b	#3, @(3, r1)
+	bf8k	mfail
+
+	bor.b	#4, @(3, r1)
+	bf8k	mfail
+	band.b	#5, @(3, r1)
+	bf8k	mfail
+	bor.b	#6, @(3, r1)
+	bf8k	mfail
+	band.b	#7, @(3, r1)
+	bf8k	mfail
+
+	band.b	#0, @(2, r1)
+	bf8k	mfail
+	bor.b	#1, @(2, r1)
+	bf8k	mfail
+	band.b	#2, @(2, r1)
+	bf8k	mfail
+	bor.b	#3, @(2, r1)
+	bf8k	mfail
+
+	bra	.L2
+	nop
+
+	.align 2
+x:	.long	_x
+
+.L2:
+	bor.b	#4, @(2, r1)
+	bf8k	mfail
+	band.b	#5, @(2, r1)
+	bf8k	mfail
+	bor.b	#6, @(2, r1)
+	bf8k	mfail
+	band.b	#7, @(2, r1)
+	bf8k	mfail
+
+	band.b	#0, @(1, r1)
+	bf8k	mfail
+	bor.b	#1, @(1, r1)
+	bf8k	mfail
+	band.b	#2, @(1, r1)
+	bf8k	mfail
+	bor.b	#3, @(1, r1)
+	bf8k	mfail
+
+	bor.b	#4, @(1, r1)
+	bf8k	mfail
+	band.b	#5, @(1, r1)
+	bf8k	mfail
+	bor.b	#6, @(1, r1)
+	bf8k	mfail
+	band.b	#7, @(1, r1)
+	bf8k	mfail
+
+	band.b	#0, @(0, r1)
+	bf8k	mfail
+	bor.b	#1, @(0, r1)
+	bf8k	mfail
+	band.b	#2, @(0, r1)
+	bf8k	mfail
+	bor.b	#3, @(0, r1)
+	bf8k	mfail
+
+	bor.b	#4, @(0, r1)
+	bf8k	mfail
+	band.b	#5, @(0, r1)
+	bf8k	mfail
+	bor.b	#6, @(0, r1)
+	bf8k	mfail
+	band.b	#7, @(0, r1)
+	bf8k	mfail
+
+	assertreg _x, r1
+
+	test_gr_a5a5 r0
+	test_gr_a5a5 r2
+	test_gr_a5a5 r3
+	test_gr_a5a5 r4
+	test_gr_a5a5 r5
+	test_gr_a5a5 r6
+	test_gr_a5a5 r7
+	test_gr_a5a5 r8
+	test_gr_a5a5 r9
+	test_gr_a5a5 r10
+	test_gr_a5a5 r11
+	test_gr_a5a5 r12
+	test_gr_a5a5 r13
+	test_gr_a5a5 r14
+
+	pass
+
+	exit 0
+
+
diff --git a/sim/testsuite/sim/sh/bandornot.s b/sim/testsuite/sim/sh/bandornot.s
new file mode 100644
index 0000000..1787d0d
--- /dev/null
+++ b/sim/testsuite/sim/sh/bandornot.s
@@ -0,0 +1,120 @@
+# sh testcase for bandnot, bornot
+# mach:	 all
+# as(sh):	-defsym sim_cpu=0
+# as(shdsp):	-defsym sim_cpu=1 -dsp 
+
+	.include "testutils.inc"
+
+	.align 2
+_x:	.long	0xa5a5a5a5
+
+	start
+
+bandor_b_imm_disp12_reg:
+	set_grs_a5a5
+	# Make sure T is true to start.
+	sett
+
+	mov.l	x, r1
+
+	bandnot.b	#0, @(3, r1)
+	bt8k	mfail
+	bornot.b	#1, @(3, r1)
+	bf8k	mfail
+	bandnot.b	#2, @(3, r1)
+	bt8k	mfail
+	bornot.b	#3, @(3, r1)
+	bf8k	mfail
+
+	bornot.b	#4, @(3, r1)
+	bf8k	mfail
+	bandnot.b	#5, @(3, r1)
+	bt8k	mfail
+	bornot.b	#6, @(3, r1)
+	bf8k	mfail
+	bandnot.b	#7, @(3, r1)
+	bt8k	mfail
+
+	bandnot.b	#0, @(2, r1)
+	bt8k	mfail
+	bornot.b	#1, @(2, r1)
+	bf8k	mfail
+	bandnot.b	#2, @(2, r1)
+	bt8k	mfail
+	bornot.b	#3, @(2, r1)
+	bf8k	mfail
+
+	bra	.L2
+	nop
+
+	.align 2
+x:	.long	_x
+
+.L2:
+	bornot.b	#4, @(2, r1)
+	bf8k	mfail
+	bandnot.b	#5, @(2, r1)
+	bt8k	mfail
+	bornot.b	#6, @(2, r1)
+	bf8k	mfail
+	bandnot.b	#7, @(2, r1)
+	bt8k	mfail
+
+	bandnot.b	#0, @(1, r1)
+	bt8k	mfail
+	bornot.b	#1, @(1, r1)
+	bf8k	mfail
+	bandnot.b	#2, @(1, r1)
+	bt8k	mfail
+	bornot.b	#3, @(1, r1)
+	bf8k	mfail
+
+	bornot.b	#4, @(1, r1)
+	bf8k	mfail
+	bandnot.b	#5, @(1, r1)
+	bt8k	mfail
+	bornot.b	#6, @(1, r1)
+	bf8k	mfail
+	bandnot.b	#7, @(1, r1)
+	bt8k	mfail
+
+	bandnot.b	#0, @(0, r1)
+	bt8k	mfail
+	bornot.b	#1, @(0, r1)
+	bf8k	mfail
+	bandnot.b	#2, @(0, r1)
+	bt8k	mfail
+	bornot.b	#3, @(0, r1)
+	bf8k	mfail
+
+	bornot.b	#4, @(0, r1)
+	bf8k	mfail
+	bandnot.b	#5, @(0, r1)
+	bt8k	mfail
+	bornot.b	#6, @(0, r1)
+	bf8k	mfail
+	bandnot.b	#7, @(0, r1)
+	bt8k	mfail
+
+	assertreg _x, r1
+
+	test_gr_a5a5 r0
+	test_gr_a5a5 r2
+	test_gr_a5a5 r3
+	test_gr_a5a5 r4
+	test_gr_a5a5 r5
+	test_gr_a5a5 r6
+	test_gr_a5a5 r7
+	test_gr_a5a5 r8
+	test_gr_a5a5 r9
+	test_gr_a5a5 r10
+	test_gr_a5a5 r11
+	test_gr_a5a5 r12
+	test_gr_a5a5 r13
+	test_gr_a5a5 r14
+
+	pass
+
+	exit 0
+
+
diff --git a/sim/testsuite/sim/sh/bclr.s b/sim/testsuite/sim/sh/bclr.s
new file mode 100644
index 0000000..cbe1c7e
--- /dev/null
+++ b/sim/testsuite/sim/sh/bclr.s
@@ -0,0 +1,139 @@
+# sh testcase for bclr
+# mach:	 all
+# as(sh):	-defsym sim_cpu=0
+# as(shdsp):	-defsym sim_cpu=1 -dsp 
+
+	.include "testutils.inc"
+
+	.align 2
+_x:	.long	0xffffffff
+_y:	.long	0x55555555
+
+	start
+
+bclr_b_imm_disp12_reg:
+	set_grs_a5a5
+	mov.l	x, r1
+
+	bclr.b	#0, @(3, r1)
+	assertmem _x, 0xfffffffe
+	bclr.b	#1, @(3, r1)
+	assertmem _x, 0xfffffffc
+	bclr.b	#2, @(3, r1)
+	assertmem _x, 0xfffffff8
+	bclr.b	#3, @(3, r1)
+	assertmem _x, 0xfffffff0
+
+	bclr.b	#4, @(3, r1)
+	assertmem _x, 0xffffffe0
+	bclr.b	#5, @(3, r1)
+	assertmem _x, 0xffffffc0
+	bclr.b	#6, @(3, r1)
+	assertmem _x, 0xffffff80
+	bclr.b	#7, @(3, r1)
+	assertmem _x, 0xffffff00
+
+	bclr.b	#0, @(2, r1)
+	assertmem _x, 0xfffffe00
+	bclr.b	#1, @(2, r1)
+	assertmem _x, 0xfffffc00
+	bclr.b	#2, @(2, r1)
+	assertmem _x, 0xfffff800
+	bclr.b	#3, @(2, r1)
+	assertmem _x, 0xfffff000
+
+	bra	.L2
+	nop
+
+	.align 2
+x:	.long	_x
+y:	.long	_y
+
+.L2:
+	bclr.b	#4, @(2, r1)
+	assertmem _x, 0xffffe000
+	bclr.b	#5, @(2, r1)
+	assertmem _x, 0xffffc000
+	bclr.b	#6, @(2, r1)
+	assertmem _x, 0xffff8000
+	bclr.b	#7, @(2, r1)
+	assertmem _x, 0xffff0000
+
+	bclr.b	#0, @(1, r1)
+	assertmem _x, 0xfffe0000
+	bclr.b	#1, @(1, r1)
+	assertmem _x, 0xfffc0000
+	bclr.b	#2, @(1, r1)
+	assertmem _x, 0xfff80000
+	bclr.b	#3, @(1, r1)
+	assertmem _x, 0xfff00000
+
+	bclr.b	#4, @(1, r1)
+	assertmem _x, 0xffe00000
+	bclr.b	#5, @(1, r1)
+	assertmem _x, 0xffc00000
+	bclr.b	#6, @(1, r1)
+	assertmem _x, 0xff800000
+	bclr.b	#7, @(1, r1)
+	assertmem _x, 0xff000000
+
+	bclr.b	#0, @(0, r1)
+	assertmem _x, 0xfe000000
+	bclr.b	#1, @(0, r1)
+	assertmem _x, 0xfc000000
+	bclr.b	#2, @(0, r1)
+	assertmem _x, 0xf8000000
+	bclr.b	#3, @(0, r1)
+	assertmem _x, 0xf0000000
+
+	bclr.b	#4, @(0, r1)
+	assertmem _x, 0xe0000000
+	bclr.b	#5, @(0, r1)
+	assertmem _x, 0xc0000000
+	bclr.b	#6, @(0, r1)
+	assertmem _x, 0x80000000
+	bclr.b	#7, @(0, r1)
+	assertmem _x, 0x00000000
+
+	assertreg _x, r1
+
+bclr_imm_reg:
+	set_greg 0xff, r1
+	bclr	#0, r1
+	assertreg 0xfe, r1
+	bclr	#1, r1
+	assertreg 0xfc, r1
+	bclr	#2, r1
+	assertreg 0xf8, r1
+	bclr	#3, r1
+	assertreg 0xf0, r1
+
+	bclr	#4, r1
+	assertreg 0xe0, r1
+	bclr	#5, r1
+	assertreg 0xc0, r1
+	bclr	#6, r1
+	assertreg 0x80, r1
+	bclr	#7, r1
+	assertreg 0x00, r1
+
+	test_gr_a5a5 r0
+	test_gr_a5a5 r2
+	test_gr_a5a5 r3
+	test_gr_a5a5 r4
+	test_gr_a5a5 r5
+	test_gr_a5a5 r6
+	test_gr_a5a5 r7
+	test_gr_a5a5 r8
+	test_gr_a5a5 r9
+	test_gr_a5a5 r10
+	test_gr_a5a5 r11
+	test_gr_a5a5 r12
+	test_gr_a5a5 r13
+	test_gr_a5a5 r14
+
+	pass
+
+	exit 0
+
+
diff --git a/sim/testsuite/sim/sh/bld.s b/sim/testsuite/sim/sh/bld.s
new file mode 100644
index 0000000..172718d
--- /dev/null
+++ b/sim/testsuite/sim/sh/bld.s
@@ -0,0 +1,121 @@
+# sh testcase for bld
+# mach:	 all
+# as(sh):	-defsym sim_cpu=0
+# as(shdsp):	-defsym sim_cpu=1 -dsp 
+
+	.include "testutils.inc"
+
+	.align 2
+_x:	.long	0xa5a5a5a5
+_y:	.long	0x55555555
+
+	start
+
+bld_b_imm_disp12_reg:
+	set_grs_a5a5
+	mov.l	x, r1
+
+	bld.b	#0, @(0, r1)
+	bf8k	mfail
+	bld.b	#1, @(0, r1)
+	bt8k	mfail
+	bld.b	#2, @(0, r1)
+	bf8k	mfail
+	bld.b	#3, @(0, r1)
+	bt8k	mfail
+
+	bld.b	#4, @(0, r1)
+	bt8k	mfail
+	bld.b	#5, @(0, r1)
+	bf8k	mfail
+	bld.b	#6, @(0, r1)
+	bt8k	mfail
+	bld.b	#7, @(0, r1)
+	bf8k	mfail
+
+	bld.b	#0, @(1, r1)
+	bf8k	mfail
+	bld.b	#1, @(1, r1)
+	bt8k	mfail
+	bld.b	#2, @(1, r1)
+	bf8k	mfail
+	bld.b	#3, @(1, r1)
+	bt8k	mfail
+
+	bld.b	#4, @(1, r1)
+	bt8k	mfail
+	bld.b	#5, @(1, r1)
+	bf8k	mfail
+	bld.b	#6, @(1, r1)
+	bt8k	mfail
+	bld.b	#7, @(1, r1)
+	bf8k	mfail
+
+	bld.b	#0, @(2, r1)
+	bf8k	mfail
+	bld.b	#1, @(2, r1)
+	bt8k	mfail
+	bld.b	#2, @(2, r1)
+	bf8k	mfail
+	bld.b	#3, @(2, r1)
+	bt8k	mfail
+
+	bld.b	#4, @(2, r1)
+	bt8k	mfail
+	bld.b	#5, @(2, r1)
+	bf8k	mfail
+	bld.b	#6, @(2, r1)
+	bt8k	mfail
+	bld.b	#7, @(2, r1)
+	bf8k	mfail
+
+	bld.b	#0, @(3, r1)
+	bf8k	mfail
+	bld.b	#1, @(3, r1)
+	bt8k	mfail
+	bld.b	#2, @(3, r1)
+	bf8k	mfail
+	bld.b	#3, @(3, r1)
+	bt8k	mfail
+
+	bld.b	#4, @(3, r1)
+	bt8k	mfail
+	bld.b	#5, @(3, r1)
+	bf8k	mfail
+	bld.b	#6, @(3, r1)
+	bt8k	mfail
+	bld.b	#7, @(3, r1)
+	bf8k	mfail
+
+	assertreg _x, r1
+
+bld_imm_reg:
+	set_greg 0xa5a5a5a5, r1
+	bld	#0, r1
+	bf8k	mfail
+	bld	#1, r1
+	bt8k	mfail
+	bld	#2, r1
+	bf8k	mfail
+	bld	#3, r1
+	bt8k	mfail
+
+	bld	#4, r1
+	bt8k	mfail
+	bld	#5, r1
+	bf8k	mfail
+	bld	#6, r1
+	bt8k	mfail
+	bld	#7, r1
+	bf8k	mfail
+
+	test_grs_a5a5
+
+	pass
+
+	exit 0
+
+	.align 2
+x:	.long	_x
+y:	.long	_y
+
diff --git a/sim/testsuite/sim/sh/bldnot.s b/sim/testsuite/sim/sh/bldnot.s
new file mode 100644
index 0000000..eda87de
--- /dev/null
+++ b/sim/testsuite/sim/sh/bldnot.s
@@ -0,0 +1,102 @@
+# sh testcase for bldnot
+# mach:	 all
+# as(sh):	-defsym sim_cpu=0
+# as(shdsp):	-defsym sim_cpu=1 -dsp 
+
+	.include "testutils.inc"
+
+	.align 2
+_x:	.long	0xa5a5a5a5
+_y:	.long	0x55555555
+
+	start
+
+bldnot_b_imm_disp12_reg:
+	set_grs_a5a5
+	mov.l	x, r1
+
+	bldnot.b	#0, @(0, r1)
+	bt8k	mfail
+	bldnot.b	#1, @(0, r1)
+	bf8k	mfail
+	bldnot.b	#2, @(0, r1)
+	bt8k	mfail
+	bldnot.b	#3, @(0, r1)
+	bf8k	mfail
+
+	bldnot.b	#4, @(0, r1)
+	bf8k	mfail
+	bldnot.b	#5, @(0, r1)
+	bt8k	mfail
+	bldnot.b	#6, @(0, r1)
+	bf8k	mfail
+	bldnot.b	#7, @(0, r1)
+	bt8k	mfail
+
+	bldnot.b	#0, @(1, r1)
+	bt8k	mfail
+	bldnot.b	#1, @(1, r1)
+	bf8k	mfail
+	bldnot.b	#2, @(1, r1)
+	bt8k	mfail
+	bldnot.b	#3, @(1, r1)
+	bf8k	mfail
+
+	bldnot.b	#4, @(1, r1)
+	bf8k	mfail
+	bldnot.b	#5, @(1, r1)
+	bt8k	mfail
+	bldnot.b	#6, @(1, r1)
+	bf8k	mfail
+	bldnot.b	#7, @(1, r1)
+	bt8k	mfail
+
+	bldnot.b	#0, @(2, r1)
+	bt8k	mfail
+	bldnot.b	#1, @(2, r1)
+	bf8k	mfail
+	bldnot.b	#2, @(2, r1)
+	bt8k	mfail
+	bldnot.b	#3, @(2, r1)
+	bf8k	mfail
+
+	bldnot.b	#4, @(2, r1)
+	bf8k	mfail
+	bldnot.b	#5, @(2, r1)
+	bt8k	mfail
+	bldnot.b	#6, @(2, r1)
+	bf8k	mfail
+	bldnot.b	#7, @(2, r1)
+	bt8k	mfail
+
+	bldnot.b	#0, @(3, r1)
+	bt8k	mfail
+	bldnot.b	#1, @(3, r1)
+	bf8k	mfail
+	bldnot.b	#2, @(3, r1)
+	bt8k	mfail
+	bldnot.b	#3, @(3, r1)
+	bf8k	mfail
+
+	bldnot.b	#4, @(3, r1)
+	bf8k	mfail
+	bldnot.b	#5, @(3, r1)
+	bt8k	mfail
+	bldnot.b	#6, @(3, r1)
+	bf8k	mfail
+	bldnot.b	#7, @(3, r1)
+	bt8k	mfail
+
+	assertreg _x, r1
+	set_greg 0xa5a5a5a5, r1
+
+	test_grs_a5a5
+
+	pass
+
+	exit 0
+
+	.align 2
+x:	.long	_x
+y:	.long	_y
+
diff --git a/sim/testsuite/sim/sh/bset.s b/sim/testsuite/sim/sh/bset.s
new file mode 100644
index 0000000..13ae246
--- /dev/null
+++ b/sim/testsuite/sim/sh/bset.s
@@ -0,0 +1,139 @@
+# sh testcase for bset
+# mach:	 all
+# as(sh):	-defsym sim_cpu=0
+# as(shdsp):	-defsym sim_cpu=1 -dsp 
+
+	.include "testutils.inc"
+
+	.align 2
+_x:	.long	0
+_y:	.long	0x55555555
+
+	start
+
+bset_b_imm_disp12_reg:
+	set_grs_a5a5
+	mov.l	x, r1
+
+	bset.b	#0, @(3, r1)
+	assertmem _x, 0x1
+	bset.b	#1, @(3, r1)
+	assertmem _x, 0x3
+	bset.b	#2, @(3, r1)
+	assertmem _x, 0x7
+	bset.b	#3, @(3, r1)
+	assertmem _x, 0xf
+
+	bset.b	#4, @(3, r1)
+	assertmem _x, 0x1f
+	bset.b	#5, @(3, r1)
+	assertmem _x, 0x3f
+	bset.b	#6, @(3, r1)
+	assertmem _x, 0x7f
+	bset.b	#7, @(3, r1)
+	assertmem _x, 0xff
+
+	bset.b	#0, @(2, r1)
+	assertmem _x, 0x1ff
+	bset.b	#1, @(2, r1)
+	assertmem _x, 0x3ff
+	bset.b	#2, @(2, r1)
+	assertmem _x, 0x7ff
+	bset.b	#3, @(2, r1)
+	assertmem _x, 0xfff
+
+	bra	.L2
+	nop
+
+	.align 2
+x:	.long	_x
+y:	.long	_y
+
+.L2:
+	bset.b	#4, @(2, r1)
+	assertmem _x, 0x1fff
+	bset.b	#5, @(2, r1)
+	assertmem _x, 0x3fff
+	bset.b	#6, @(2, r1)
+	assertmem _x, 0x7fff
+	bset.b	#7, @(2, r1)
+	assertmem _x, 0xffff
+
+	bset.b	#0, @(1, r1)
+	assertmem _x, 0x1ffff
+	bset.b	#1, @(1, r1)
+	assertmem _x, 0x3ffff
+	bset.b	#2, @(1, r1)
+	assertmem _x, 0x7ffff
+	bset.b	#3, @(1, r1)
+	assertmem _x, 0xfffff
+
+	bset.b	#4, @(1, r1)
+	assertmem _x, 0x1fffff
+	bset.b	#5, @(1, r1)
+	assertmem _x, 0x3fffff
+	bset.b	#6, @(1, r1)
+	assertmem _x, 0x7fffff
+	bset.b	#7, @(1, r1)
+	assertmem _x, 0xffffff
+
+	bset.b	#0, @(0, r1)
+	assertmem _x, 0x1ffffff
+	bset.b	#1, @(0, r1)
+	assertmem _x, 0x3ffffff
+	bset.b	#2, @(0, r1)
+	assertmem _x, 0x7ffffff
+	bset.b	#3, @(0, r1)
+	assertmem _x, 0xfffffff
+
+	bset.b	#4, @(0, r1)
+	assertmem _x, 0x1fffffff
+	bset.b	#5, @(0, r1)
+	assertmem _x, 0x3fffffff
+	bset.b	#6, @(0, r1)
+	assertmem _x, 0x7fffffff
+	bset.b	#7, @(0, r1)
+	assertmem _x, 0xffffffff
+
+	assertreg _x, r1
+
+bset_imm_reg:
+	set_greg 0, r1
+	bset	#0, r1
+	assertreg 0x1, r1
+	bset	#1, r1
+	assertreg 0x3, r1
+	bset	#2, r1
+	assertreg 0x7, r1
+	bset	#3, r1
+	assertreg 0xf, r1
+
+	bset	#4, r1
+	assertreg 0x1f, r1
+	bset	#5, r1
+	assertreg 0x3f, r1
+	bset	#6, r1
+	assertreg 0x7f, r1
+	bset	#7, r1
+	assertreg 0xff, r1
+
+	test_gr_a5a5 r0
+	test_gr_a5a5 r2
+	test_gr_a5a5 r3
+	test_gr_a5a5 r4
+	test_gr_a5a5 r5
+	test_gr_a5a5 r6
+	test_gr_a5a5 r7
+	test_gr_a5a5 r8
+	test_gr_a5a5 r9
+	test_gr_a5a5 r10
+	test_gr_a5a5 r11
+	test_gr_a5a5 r12
+	test_gr_a5a5 r13
+	test_gr_a5a5 r14
+
+	pass
+
+	exit 0
+
+
diff --git a/sim/testsuite/sim/sh/bst.s b/sim/testsuite/sim/sh/bst.s
new file mode 100644
index 0000000..e8b6d65
--- /dev/null
+++ b/sim/testsuite/sim/sh/bst.s
@@ -0,0 +1,142 @@
+# sh testcase for bst
+# mach:	 all
+# as(sh):	-defsym sim_cpu=0
+# as(shdsp):	-defsym sim_cpu=1 -dsp 
+
+	.include "testutils.inc"
+
+	.align 2
+_x:	.long	0
+_y:	.long	0x55555555
+
+	start
+
+bst_b_imm_disp12_reg:
+	set_grs_a5a5
+	# Make sure T is true to start.
+	sett
+
+	mov.l	x, r1
+
+	bst.b	#0, @(3, r1)
+	assertmem _x, 0x1
+	bst.b	#1, @(3, r1)
+	assertmem _x, 0x3
+	bst.b	#2, @(3, r1)
+	assertmem _x, 0x7
+	bst.b	#3, @(3, r1)
+	assertmem _x, 0xf
+
+	bst.b	#4, @(3, r1)
+	assertmem _x, 0x1f
+	bst.b	#5, @(3, r1)
+	assertmem _x, 0x3f
+	bst.b	#6, @(3, r1)
+	assertmem _x, 0x7f
+	bst.b	#7, @(3, r1)
+	assertmem _x, 0xff
+
+	bst.b	#0, @(2, r1)
+	assertmem _x, 0x1ff
+	bst.b	#1, @(2, r1)
+	assertmem _x, 0x3ff
+	bst.b	#2, @(2, r1)
+	assertmem _x, 0x7ff
+	bst.b	#3, @(2, r1)
+	assertmem _x, 0xfff
+
+	bra	.L2
+	nop
+
+	.align 2
+x:	.long	_x
+y:	.long	_y
+
+.L2:
+	bst.b	#4, @(2, r1)
+	assertmem _x, 0x1fff
+	bst.b	#5, @(2, r1)
+	assertmem _x, 0x3fff
+	bst.b	#6, @(2, r1)
+	assertmem _x, 0x7fff
+	bst.b	#7, @(2, r1)
+	assertmem _x, 0xffff
+
+	bst.b	#0, @(1, r1)
+	assertmem _x, 0x1ffff
+	bst.b	#1, @(1, r1)
+	assertmem _x, 0x3ffff
+	bst.b	#2, @(1, r1)
+	assertmem _x, 0x7ffff
+	bst.b	#3, @(1, r1)
+	assertmem _x, 0xfffff
+
+	bst.b	#4, @(1, r1)
+	assertmem _x, 0x1fffff
+	bst.b	#5, @(1, r1)
+	assertmem _x, 0x3fffff
+	bst.b	#6, @(1, r1)
+	assertmem _x, 0x7fffff
+	bst.b	#7, @(1, r1)
+	assertmem _x, 0xffffff
+
+	bst.b	#0, @(0, r1)
+	assertmem _x, 0x1ffffff
+	bst.b	#1, @(0, r1)
+	assertmem _x, 0x3ffffff
+	bst.b	#2, @(0, r1)
+	assertmem _x, 0x7ffffff
+	bst.b	#3, @(0, r1)
+	assertmem _x, 0xfffffff
+
+	bst.b	#4, @(0, r1)
+	assertmem _x, 0x1fffffff
+	bst.b	#5, @(0, r1)
+	assertmem _x, 0x3fffffff
+	bst.b	#6, @(0, r1)
+	assertmem _x, 0x7fffffff
+	bst.b	#7, @(0, r1)
+	assertmem _x, 0xffffffff
+
+	assertreg _x, r1
+
+bst_imm_reg:
+	set_greg 0, r1
+	bst	#0, r1
+	assertreg 0x1, r1
+	bst	#1, r1
+	assertreg 0x3, r1
+	bst	#2, r1
+	assertreg 0x7, r1
+	bst	#3, r1
+	assertreg 0xf, r1
+
+	bst	#4, r1
+	assertreg 0x1f, r1
+	bst	#5, r1
+	assertreg 0x3f, r1
+	bst	#6, r1
+	assertreg 0x7f, r1
+	bst	#7, r1
+	assertreg 0xff, r1
+
+	test_gr_a5a5 r0
+	test_gr_a5a5 r2
+	test_gr_a5a5 r3
+	test_gr_a5a5 r4
+	test_gr_a5a5 r5
+	test_gr_a5a5 r6
+	test_gr_a5a5 r7
+	test_gr_a5a5 r8
+	test_gr_a5a5 r9
+	test_gr_a5a5 r10
+	test_gr_a5a5 r11
+	test_gr_a5a5 r12
+	test_gr_a5a5 r13
+	test_gr_a5a5 r14
+
+	pass
+
+	exit 0
+
+
diff --git a/sim/testsuite/sim/sh/bxor.s b/sim/testsuite/sim/sh/bxor.s
new file mode 100644
index 0000000..abedd38
--- /dev/null
+++ b/sim/testsuite/sim/sh/bxor.s
@@ -0,0 +1,120 @@
+# sh testcase for bxor
+# mach:	 all
+# as(sh):	-defsym sim_cpu=0
+# as(shdsp):	-defsym sim_cpu=1 -dsp 
+
+	.include "testutils.inc"
+
+	.align 2
+_x:	.long	0xa5a5a5a5
+
+	start
+
+bxor_b_imm_disp12_reg:
+	set_grs_a5a5
+	# Make sure T is true to start.
+	sett
+
+	mov.l	x, r1
+
+	bxor.b	#0, @(3, r1)
+	bt8k	mfail
+	bxor.b	#1, @(3, r1)
+	bt8k	mfail
+	bxor.b	#2, @(3, r1)
+	bf8k	mfail
+	bxor.b	#3, @(3, r1)
+	bf8k	mfail
+
+	bxor.b	#4, @(3, r1)
+	bf8k	mfail
+	bxor.b	#5, @(3, r1)
+	bt8k	mfail
+	bxor.b	#6, @(3, r1)
+	bt8k	mfail
+	bxor.b	#7, @(3, r1)
+	bf8k	mfail
+
+	bxor.b	#0, @(2, r1)
+	bt8k	mfail
+	bxor.b	#1, @(2, r1)
+	bt8k	mfail
+	bxor.b	#2, @(2, r1)
+	bf8k	mfail
+	bxor.b	#3, @(2, r1)
+	bf8k	mfail
+
+	bra	.L2
+	nop
+
+	.align 2
+x:	.long	_x
+
+.L2:
+	bxor.b	#4, @(2, r1)
+	bf8k	mfail
+	bxor.b	#5, @(2, r1)
+	bt8k	mfail
+	bxor.b	#6, @(2, r1)
+	bt8k	mfail
+	bxor.b	#7, @(2, r1)
+	bf8k	mfail
+
+	bxor.b	#0, @(1, r1)
+	bt8k	mfail
+	bxor.b	#1, @(1, r1)
+	bt8k	mfail
+	bxor.b	#2, @(1, r1)
+	bf8k	mfail
+	bxor.b	#3, @(1, r1)
+	bf8k	mfail
+
+	bxor.b	#4, @(1, r1)
+	bf8k	mfail
+	bxor.b	#5, @(1, r1)
+	bt8k	mfail
+	bxor.b	#6, @(1, r1)
+	bt8k	mfail
+	bxor.b	#7, @(1, r1)
+	bf8k	mfail
+
+	bxor.b	#0, @(0, r1)
+	bt8k	mfail
+	bxor.b	#1, @(0, r1)
+	bt8k	mfail
+	bxor.b	#2, @(0, r1)
+	bf8k	mfail
+	bxor.b	#3, @(0, r1)
+	bf8k	mfail
+
+	bxor.b	#4, @(0, r1)
+	bf8k	mfail
+	bxor.b	#5, @(0, r1)
+	bt8k	mfail
+	bxor.b	#6, @(0, r1)
+	bt8k	mfail
+	bxor.b	#7, @(0, r1)
+	bf8k	mfail
+
+	assertreg _x, r1
+
+	test_gr_a5a5 r0
+	test_gr_a5a5 r2
+	test_gr_a5a5 r3
+	test_gr_a5a5 r4
+	test_gr_a5a5 r5
+	test_gr_a5a5 r6
+	test_gr_a5a5 r7
+	test_gr_a5a5 r8
+	test_gr_a5a5 r9
+	test_gr_a5a5 r10
+	test_gr_a5a5 r11
+	test_gr_a5a5 r12
+	test_gr_a5a5 r13
+	test_gr_a5a5 r14
+
+	pass
+
+	exit 0
+
+
diff --git a/sim/testsuite/sim/sh/clip.s b/sim/testsuite/sim/sh/clip.s
new file mode 100644
index 0000000..12770c381
--- /dev/null
+++ b/sim/testsuite/sim/sh/clip.s
@@ -0,0 +1,89 @@
+# sh testcase for clips, clipu
+# mach:	 all
+# as(sh):	-defsym sim_cpu=0
+# as(shdsp):	-defsym sim_cpu=1 -dsp 
+
+	.include "testutils.inc"
+
+	start
+
+clips_b:
+	set_grs_a5a5
+	clips.b	r1
+	test_gr0_a5a5
+	assertreg 0xffffff80 r1
+	test_gr_a5a5 r2
+	test_gr_a5a5 r3
+	test_gr_a5a5 r4
+	test_gr_a5a5 r5
+	test_gr_a5a5 r6
+	test_gr_a5a5 r7
+	test_gr_a5a5 r8
+	test_gr_a5a5 r9
+	test_gr_a5a5 r10
+	test_gr_a5a5 r11
+	test_gr_a5a5 r12
+	test_gr_a5a5 r13
+	test_gr_a5a5 r14
+
+clipu_b:
+	set_grs_a5a5
+	clipu.b	r1
+	test_gr0_a5a5
+	assertreg 0xff r1
+	test_gr_a5a5 r2
+	test_gr_a5a5 r3
+	test_gr_a5a5 r4
+	test_gr_a5a5 r5
+	test_gr_a5a5 r6
+	test_gr_a5a5 r7
+	test_gr_a5a5 r8
+	test_gr_a5a5 r9
+	test_gr_a5a5 r10
+	test_gr_a5a5 r11
+	test_gr_a5a5 r12
+	test_gr_a5a5 r13
+	test_gr_a5a5 r14
+	
+clips_w:
+	set_grs_a5a5
+	clips.w	r1
+	test_gr0_a5a5
+	assertreg 0xffff8000 r1
+	test_gr_a5a5 r2
+	test_gr_a5a5 r3
+	test_gr_a5a5 r4
+	test_gr_a5a5 r5
+	test_gr_a5a5 r6
+	test_gr_a5a5 r7
+	test_gr_a5a5 r8
+	test_gr_a5a5 r9
+	test_gr_a5a5 r10
+	test_gr_a5a5 r11
+	test_gr_a5a5 r12
+	test_gr_a5a5 r13
+	test_gr_a5a5 r14
+
+clipu_w:
+	set_grs_a5a5
+	clipu.w	r1
+	test_gr0_a5a5
+	assertreg 0xffff r1
+	test_gr_a5a5 r2
+	test_gr_a5a5 r3
+	test_gr_a5a5 r4
+	test_gr_a5a5 r5
+	test_gr_a5a5 r6
+	test_gr_a5a5 r7
+	test_gr_a5a5 r8
+	test_gr_a5a5 r9
+	test_gr_a5a5 r10
+	test_gr_a5a5 r11
+	test_gr_a5a5 r12
+	test_gr_a5a5 r13
+	test_gr_a5a5 r14
+	
+	pass
+
+	exit 0
+
diff --git a/sim/testsuite/sim/sh/div.s b/sim/testsuite/sim/sh/div.s
new file mode 100644
index 0000000..8293c21
--- /dev/null
+++ b/sim/testsuite/sim/sh/div.s
@@ -0,0 +1,199 @@
+# sh testcase for divs and divu
+# mach:	 all
+# as(sh):	-defsym sim_cpu=0
+# as(shdsp):	-defsym sim_cpu=1 -dsp 
+
+	.include "testutils.inc"
+
+	start
+
+divs_1:	! divide by one
+	set_grs_a5a5
+	mov	#1, r0
+	divs	r0, r1
+	assertreg0   1
+	test_gr_a5a5 r1
+	test_gr_a5a5 r2
+	test_gr_a5a5 r3
+	test_gr_a5a5 r4
+	test_gr_a5a5 r5
+	test_gr_a5a5 r6
+	test_gr_a5a5 r7
+	test_gr_a5a5 r8
+	test_gr_a5a5 r9
+	test_gr_a5a5 r10
+	test_gr_a5a5 r11
+	test_gr_a5a5 r12
+	test_gr_a5a5 r13
+	test_gr_a5a5 r14
+
+divs_2:	! divide by two
+	set_grs_a5a5
+	mov	#2, r0
+	divs	r0, r1
+	assertreg0   2
+	assertreg 0xd2d2d2d3, r1
+	test_gr_a5a5 r2
+	test_gr_a5a5 r3
+	test_gr_a5a5 r4
+	test_gr_a5a5 r5
+	test_gr_a5a5 r6
+	test_gr_a5a5 r7
+	test_gr_a5a5 r8
+	test_gr_a5a5 r9
+	test_gr_a5a5 r10
+	test_gr_a5a5 r11
+	test_gr_a5a5 r12
+	test_gr_a5a5 r13
+	test_gr_a5a5 r14
+
+divs_3:	! divide by three
+	set_grs_a5a5
+	mov	#3, r0
+	divs	r0, r1
+	assertreg0   3
+	assertreg 0xe1e1e1e2, r1
+	test_gr_a5a5 r2
+	test_gr_a5a5 r3
+	test_gr_a5a5 r4
+	test_gr_a5a5 r5
+	test_gr_a5a5 r6
+	test_gr_a5a5 r7
+	test_gr_a5a5 r8
+	test_gr_a5a5 r9
+	test_gr_a5a5 r10
+	test_gr_a5a5 r11
+	test_gr_a5a5 r12
+	test_gr_a5a5 r13
+	test_gr_a5a5 r14
+
+divs_0:	! divide by zero
+	set_grs_a5a5
+	mov	#0, r0
+	divs	r0, r1
+	assertreg0   0
+	assertreg 0x7fffffff, r1
+	test_gr_a5a5 r2
+	test_gr_a5a5 r3
+	test_gr_a5a5 r4
+	test_gr_a5a5 r5
+	test_gr_a5a5 r6
+	test_gr_a5a5 r7
+	test_gr_a5a5 r8
+	test_gr_a5a5 r9
+	test_gr_a5a5 r10
+	test_gr_a5a5 r11
+	test_gr_a5a5 r12
+	test_gr_a5a5 r13
+	test_gr_a5a5 r14
+
+divs_o:	! divide signed overflow
+	set_grs_a5a5
+	mov	#16, r0
+	movi20	#0x8000, r1
+	shad	r0, r1	! r1 == 0x80000000
+	mov	#-1, r0
+	divs	r0, r1
+	assertreg0   -1
+	assertreg 0x7fffffff, r1
+	test_gr_a5a5 r2
+	test_gr_a5a5 r3
+	test_gr_a5a5 r4
+	test_gr_a5a5 r5
+	test_gr_a5a5 r6
+	test_gr_a5a5 r7
+	test_gr_a5a5 r8
+	test_gr_a5a5 r9
+	test_gr_a5a5 r10
+	test_gr_a5a5 r11
+	test_gr_a5a5 r12
+	test_gr_a5a5 r13
+	test_gr_a5a5 r14
+
+
+divu_1:	! divide by one, unsigned
+	set_grs_a5a5
+	mov	#1, r0
+	divu	r0, r1
+	assertreg0   1
+	test_gr_a5a5 r1
+	test_gr_a5a5 r2
+	test_gr_a5a5 r3
+	test_gr_a5a5 r4
+	test_gr_a5a5 r5
+	test_gr_a5a5 r6
+	test_gr_a5a5 r7
+	test_gr_a5a5 r8
+	test_gr_a5a5 r9
+	test_gr_a5a5 r10
+	test_gr_a5a5 r11
+	test_gr_a5a5 r12
+	test_gr_a5a5 r13
+	test_gr_a5a5 r14
+
+divu_2:	! divide by two, unsigned
+	set_grs_a5a5
+	mov	#2, r0
+	divu	r0, r1
+	assertreg0   2
+	assertreg 0x52d2d2d2, r1
+	test_gr_a5a5 r2
+	test_gr_a5a5 r3
+	test_gr_a5a5 r4
+	test_gr_a5a5 r5
+	test_gr_a5a5 r6
+	test_gr_a5a5 r7
+	test_gr_a5a5 r8
+	test_gr_a5a5 r9
+	test_gr_a5a5 r10
+	test_gr_a5a5 r11
+	test_gr_a5a5 r12
+	test_gr_a5a5 r13
+	test_gr_a5a5 r14
+
+divu_3:	! divide by three, unsigned
+	set_grs_a5a5
+	mov	#3, r0
+	divu	r0, r1
+	assertreg0   3
+	assertreg 0x37373737, r1
+	test_gr_a5a5 r2
+	test_gr_a5a5 r3
+	test_gr_a5a5 r4
+	test_gr_a5a5 r5
+	test_gr_a5a5 r6
+	test_gr_a5a5 r7
+	test_gr_a5a5 r8
+	test_gr_a5a5 r9
+	test_gr_a5a5 r10
+	test_gr_a5a5 r11
+	test_gr_a5a5 r12
+	test_gr_a5a5 r13
+	test_gr_a5a5 r14
+
+divu_0:	! divide by zero, unsigned
+	set_grs_a5a5
+	mov	#0, r0
+	divu	r0, r1
+	assertreg0   0
+	assertreg 0xffffffff, r1
+	test_gr_a5a5 r2
+	test_gr_a5a5 r3
+	test_gr_a5a5 r4
+	test_gr_a5a5 r5
+	test_gr_a5a5 r6
+	test_gr_a5a5 r7
+	test_gr_a5a5 r8
+	test_gr_a5a5 r9
+	test_gr_a5a5 r10
+	test_gr_a5a5 r11
+	test_gr_a5a5 r12
+	test_gr_a5a5 r13
+	test_gr_a5a5 r14
+
+
+	pass
+
+	exit 0
+
+	
\ No newline at end of file
diff --git a/sim/testsuite/sim/sh/fail.s b/sim/testsuite/sim/sh/fail.s
new file mode 100644
index 0000000..0ffb0b2
--- /dev/null
+++ b/sim/testsuite/sim/sh/fail.s
@@ -0,0 +1,13 @@
+# sh testcase, fail
+# mach:	 all
+# as(sh):	-defsym sim_cpu=0
+# as(shdsp):	-defsym sim_cpu=1 -dsp 
+
+	.include "testutils.inc"
+
+	start
+	
+	fail
+
+	exit 0
+
diff --git a/sim/testsuite/sim/sh/fsca.s b/sim/testsuite/sim/sh/fsca.s
new file mode 100644
index 0000000..90df6c9
--- /dev/null
+++ b/sim/testsuite/sim/sh/fsca.s
@@ -0,0 +1,97 @@
+# sh testcase for fsca
+# mach: sh
+# as(sh):	-defsym sim_cpu=0
+
+	.include "testutils.inc"
+
+	start
+fsca:
+	set_grs_a5a5
+	set_fprs_a5a5
+	# Start with angle zero
+	mov.l	zero, r0
+	lds	r0, fpul
+	fsca	fpul, dr2
+	assert_fpreg_i 0, fr2
+	assert_fpreg_i 1, fr3
+	
+	mov.l	plus_90, r0
+	lds	r0, fpul
+	fsca	fpul, dr2
+	assert_fpreg_i 1, fr2
+	assert_fpreg_i 0, fr3
+	
+	mov.l	plus_180, r0
+	lds	r0, fpul
+	fsca	fpul, dr2
+	assert_fpreg_i 0, fr2
+	assert_fpreg_i -1, fr3
+	
+	mov.l	plus_270, r0
+	lds	r0, fpul
+	fsca	fpul, dr2
+	assert_fpreg_i -1, fr2
+	assert_fpreg_i 0, fr3
+	
+	mov.l	plus_360, r0
+	lds	r0, fpul
+	fsca	fpul, dr2
+	assert_fpreg_i 0, fr2
+	assert_fpreg_i 1, fr3
+
+	mov.l	minus_90, r0
+	lds	r0, fpul
+	fsca	fpul, dr2
+	assert_fpreg_i -1, fr2
+	assert_fpreg_i 0, fr3
+	
+	mov.l	minus_180, r0
+	lds	r0, fpul
+	fsca	fpul, dr2
+	assert_fpreg_i 0, fr2
+	assert_fpreg_i -1, fr3
+	
+	mov.l	minus_270, r0
+	lds	r0, fpul
+	fsca	fpul, dr2
+	assert_fpreg_i 1, fr2
+	assert_fpreg_i 0, fr3
+	
+	mov.l	minus_360, r0
+	lds	r0, fpul
+	fsca	fpul, dr2
+	assert_fpreg_i 0, fr2
+	assert_fpreg_i 1, fr3
+
+	assertreg0      0xffff0000
+	set_greg        0xa5a5a5a5, r0
+	test_grs_a5a5
+	test_fpr_a5a5	fr0
+	test_fpr_a5a5	fr1
+	test_fpr_a5a5	fr4
+	test_fpr_a5a5	fr5
+	test_fpr_a5a5	fr6
+	test_fpr_a5a5	fr7
+	test_fpr_a5a5	fr8
+	test_fpr_a5a5	fr9
+	test_fpr_a5a5	fr10
+	test_fpr_a5a5	fr11
+	test_fpr_a5a5	fr12
+	test_fpr_a5a5	fr13
+	test_fpr_a5a5	fr14
+	test_fpr_a5a5	fr15
+	pass
+	exit 0
+
+		.align 2
+zero:		.long	0
+one_bitty:	.long	1
+plus_90:	.long	0x04000
+plus_180:	.long	0x08000
+plus_270:	.long	0x0c000
+plus_360:	.long	0x10000
+minus_90:	.long	0xffffc000
+minus_180:	.long	0xffff8000
+minus_270:	.long	0xffff4000
+minus_360:	.long	0xffff0000
+minus_1_bitty:	.long	0xffffffff
diff --git a/sim/testsuite/sim/sh/fsrra.s b/sim/testsuite/sim/sh/fsrra.s
new file mode 100644
index 0000000..fdd2235
--- /dev/null
+++ b/sim/testsuite/sim/sh/fsrra.s
@@ -0,0 +1,62 @@
+# sh testcase for fsrra
+# mach: sh
+# as(sh):	-defsym sim_cpu=0
+
+	.include "testutils.inc"
+
+	start
+fsrra_single:
+	set_grs_a5a5
+	set_fprs_a5a5
+	# 1/sqrt(0.0) = +infinity.
+	fldi0	fr0
+	fsrra	fr0
+	assert_fpreg_x	0x7f800000, fr0
+
+	# 1/sqrt(1.0) = 1.0.
+	fldi1	fr0
+	fsrra	fr0
+	assert_fpreg_i	1, fr0
+
+	# 1/sqrt(4.0) = 1/2.0
+	fldi1	fr0
+	# Double it.
+	fadd	fr0, fr0
+	# Double it again.
+	fadd	fr0, fr0
+	fsrra	fr0
+	fldi1	fr2
+	# Double it.
+	fadd	fr2, fr2
+	fldi1	fr1
+	# Divide
+	fdiv	fr2, fr1
+	fcmp/eq	fr0, fr1
+	bt	.L2
+	fail
+.L2:
+	# Double-check (pun intended)
+	fadd	fr0, fr0
+	assert_fpreg_i	1, fr0
+	fadd	fr1, fr1
+	assert_fpreg_i	1, fr1
+
+	# And make sure the rest of the regs are un-affected.
+	assert_fpreg_i	2, fr2
+	test_fpr_a5a5	fr3
+	test_fpr_a5a5	fr4
+	test_fpr_a5a5	fr5
+	test_fpr_a5a5	fr6
+	test_fpr_a5a5	fr7
+	test_fpr_a5a5	fr8
+	test_fpr_a5a5	fr9
+	test_fpr_a5a5	fr10
+	test_fpr_a5a5	fr11
+	test_fpr_a5a5	fr12
+	test_fpr_a5a5	fr13
+	test_fpr_a5a5	fr14
+	test_fpr_a5a5	fr15
+	test_grs_a5a5
+
+	pass
+	exit 0
diff --git a/sim/testsuite/sim/sh/mov.s b/sim/testsuite/sim/sh/mov.s
new file mode 100644
index 0000000..37fef51
--- /dev/null
+++ b/sim/testsuite/sim/sh/mov.s
@@ -0,0 +1,118 @@
+# sh testcase for all mov.[bwl] instructions
+# mach: sh
+# as(sh):	-defsym sim_cpu=0
+
+	.include "testutils.inc"
+
+	.align 2
+_lsrc:	.long	0x55555555
+_wsrc:	.long	0x55550000
+_bsrc:	.long	0x55000000
+
+	.align 2
+_ldst:	.long	0
+_wdst:	.long	0
+_bdst:	.long	0
+
+
+	start
+
+movb_disp12_reg:	# Test 8-bit @(disp12,gr) -> gr
+	set_grs_a5a5
+	mov.l	bsrc, r1
+	add	#-111, r1
+	add	#-111, r1
+	add	#-111, r1
+	add	#-111, r1
+	mov.b	@(444,r1), r2
+
+	assertreg _bsrc-444, r1
+	assertreg 0x55, r2
+
+movb_reg_disp12:	# Test 8-bit gr -> @(disp12,gr)
+	set_grs_a5a5
+	mov.l	bdst, r1
+	add	#-111, r1
+	add	#-111, r1
+	add	#-111, r1
+	add	#-111, r1
+	mov.b	r2, @(444,r1)
+
+	assertreg _bdst-444, r1
+	assertmem _bdst, 0xa5000000
+
+movw_disp12_reg:	# Test 16-bit @(disp12,gr) -> gr
+	set_grs_a5a5
+	mov.l	wsrc, r1
+	add	#-111, r1
+	add	#-111, r1
+	add	#-111, r1
+	add	#-111, r1
+	mov.w	@(444,r1), r2
+
+	assertreg _wsrc-444, r1
+	assertreg 0x5555, r2
+
+movw_reg_disp12:	# Test 16-bit gr -> @(disp12,gr)
+	set_grs_a5a5
+	mov.l	wdst, r1
+	add	#-111, r1
+	add	#-111, r1
+	add	#-111, r1
+	add	#-111, r1
+	mov.w	r2, @(444,r1)
+
+	assertreg _wdst-444, r1
+	assertmem _wdst, 0xa5a50000
+
+movl_disp12_reg:	# Test 32-bit @(disp12,gr) -> gr
+	set_grs_a5a5
+	mov.l	lsrc, r1
+	add	#-111, r1
+	add	#-111, r1
+	add	#-111, r1
+	add	#-111, r1
+	mov.l	@(444,r1), r2
+
+	assertreg _lsrc-444, r1
+	assertreg 0x55555555, r2
+
+movl_reg_disp12:	# Test 32-bit gr -> @(disp12,gr)
+	set_grs_a5a5
+	mov.l	ldst, r1
+	add	#-111, r1
+	add	#-111, r1
+	add	#-111, r1
+	add	#-111, r1
+	mov.l	r2, @(444,r1)
+
+	assertreg _ldst-444, r1
+	assertmem _ldst, 0xa5a5a5a5
+
+	test_gr_a5a5 r0
+	test_gr_a5a5 r2
+	test_gr_a5a5 r3
+	test_gr_a5a5 r4
+	test_gr_a5a5 r5
+	test_gr_a5a5 r6
+	test_gr_a5a5 r7
+	test_gr_a5a5 r8
+	test_gr_a5a5 r9
+	test_gr_a5a5 r10
+	test_gr_a5a5 r11
+	test_gr_a5a5 r12
+	test_gr_a5a5 r13
+	test_gr_a5a5 r14
+
+	pass
+
+	exit 0
+
+lsrc:	.long _lsrc
+wsrc:	.long _wsrc
+bsrc:	.long _bsrc
+
+ldst:	.long _ldst
+wdst:	.long _wdst
+bdst:	.long _bdst
+
diff --git a/sim/testsuite/sim/sh/movi.s b/sim/testsuite/sim/sh/movi.s
index b79f8d2..e54f4f6 100644
--- a/sim/testsuite/sim/sh/movi.s
+++ b/sim/testsuite/sim/sh/movi.s
@@ -1,7 +1,6 @@
-# sh testcase for mov <#imm> 
-# mach: all
+# sh testcase for all mov <#imm> instructions
+# mach: sh
 # as(sh):	-defsym sim_cpu=0
-# as(shdsp):	-defsym sim_cpu=1 -dsp 
 
 	.include "testutils.inc"
 
@@ -28,6 +27,48 @@ mov_i_reg:	# Test <imm8>
 	test_gr_a5a5 r13
 	test_gr_a5a5 r14
 
+movi20_reg:	# Test <imm20>
+	set_grs_a5a5
+	movi20	#-0x55555,r1
+
+	assertreg 0xfffaaaab, r1
+
+	test_gr_a5a5 r0
+	test_gr_a5a5 r2
+	test_gr_a5a5 r3
+	test_gr_a5a5 r4
+	test_gr_a5a5 r5
+	test_gr_a5a5 r6
+	test_gr_a5a5 r7
+	test_gr_a5a5 r8
+	test_gr_a5a5 r9
+	test_gr_a5a5 r10
+	test_gr_a5a5 r11
+	test_gr_a5a5 r12
+	test_gr_a5a5 r13
+	test_gr_a5a5 r14
+
+movi20s_reg:	# Test <imm20> << 8
+	set_grs_a5a5
+	movi20s	#-0x5555500,r1
+
+	assertreg 0xfaaaab00, r1
+
+	test_gr_a5a5 r0
+	test_gr_a5a5 r2
+	test_gr_a5a5 r3
+	test_gr_a5a5 r4
+	test_gr_a5a5 r5
+	test_gr_a5a5 r6
+	test_gr_a5a5 r7
+	test_gr_a5a5 r8
+	test_gr_a5a5 r9
+	test_gr_a5a5 r10
+	test_gr_a5a5 r11
+	test_gr_a5a5 r12
+	test_gr_a5a5 r13
+	test_gr_a5a5 r14
+
 	pass
 
 	exit 0
diff --git a/sim/testsuite/sim/sh/mulr.s b/sim/testsuite/sim/sh/mulr.s
new file mode 100644
index 0000000..1e755ab
--- /dev/null
+++ b/sim/testsuite/sim/sh/mulr.s
@@ -0,0 +1,162 @@
+# sh testcase for mulr
+# mach:	 all
+# as(sh):	-defsym sim_cpu=0
+# as(shdsp):	-defsym sim_cpu=1 -dsp 
+
+	.include "testutils.inc"
+
+	start
+
+mulr_1:	! multiply by one
+	set_grs_a5a5
+	mov	#1, r0
+	mulr	r0, r1
+	assertreg0   1
+	test_gr_a5a5 r1
+	test_gr_a5a5 r2
+	test_gr_a5a5 r3
+	test_gr_a5a5 r4
+	test_gr_a5a5 r5
+	test_gr_a5a5 r6
+	test_gr_a5a5 r7
+	test_gr_a5a5 r8
+	test_gr_a5a5 r9
+	test_gr_a5a5 r10
+	test_gr_a5a5 r11
+	test_gr_a5a5 r12
+	test_gr_a5a5 r13
+	test_gr_a5a5 r14
+
+mulr_2:	! multiply by two
+	set_grs_a5a5
+	mov	#2, r0
+	mov	#12, r1
+	mulr	r0, r1
+	assertreg0   2
+	assertreg 24, r1
+	test_gr_a5a5 r2
+	test_gr_a5a5 r3
+	test_gr_a5a5 r4
+	test_gr_a5a5 r5
+	test_gr_a5a5 r6
+	test_gr_a5a5 r7
+	test_gr_a5a5 r8
+	test_gr_a5a5 r9
+	test_gr_a5a5 r10
+	test_gr_a5a5 r11
+	test_gr_a5a5 r12
+	test_gr_a5a5 r13
+	test_gr_a5a5 r14
+
+mulr_3:	! multiply five by five
+	set_grs_a5a5
+	mov	#5, r0
+	mov	#5, r1
+	mulr	r0, r1
+	assertreg0   5
+	assertreg 25, r1
+	test_gr_a5a5 r2
+	test_gr_a5a5 r3
+	test_gr_a5a5 r4
+	test_gr_a5a5 r5
+	test_gr_a5a5 r6
+	test_gr_a5a5 r7
+	test_gr_a5a5 r8
+	test_gr_a5a5 r9
+	test_gr_a5a5 r10
+	test_gr_a5a5 r11
+	test_gr_a5a5 r12
+	test_gr_a5a5 r13
+	test_gr_a5a5 r14
+
+
+mulr_4:	! multiply 127 by 127
+	set_grs_a5a5
+	mov	#127, r0
+	mov	#127, r1
+	mulr	r0, r1
+	assertreg0   127
+	assertreg 0x3f01, r1
+	test_gr_a5a5 r2
+	test_gr_a5a5 r3
+	test_gr_a5a5 r4
+	test_gr_a5a5 r5
+	test_gr_a5a5 r6
+	test_gr_a5a5 r7
+	test_gr_a5a5 r8
+	test_gr_a5a5 r9
+	test_gr_a5a5 r10
+	test_gr_a5a5 r11
+	test_gr_a5a5 r12
+	test_gr_a5a5 r13
+	test_gr_a5a5 r14
+
+mulr_5:	! multiply -1 by -1
+	set_grs_a5a5
+	mov	#-1, r0
+	mov	#-1, r1
+	mulr	r0, r1
+	assertreg0   -1
+	assertreg 1, r1
+	test_gr_a5a5 r2
+	test_gr_a5a5 r3
+	test_gr_a5a5 r4
+	test_gr_a5a5 r5
+	test_gr_a5a5 r6
+	test_gr_a5a5 r7
+	test_gr_a5a5 r8
+	test_gr_a5a5 r9
+	test_gr_a5a5 r10
+	test_gr_a5a5 r11
+	test_gr_a5a5 r12
+	test_gr_a5a5 r13
+	test_gr_a5a5 r14
+
+mulr_6:	! multiply 46340 by 46340
+	set_grs_a5a5
+	movi20	#46340, r0
+	movi20	#46340, r1
+	mulr	r0, r1
+	assertreg0   46340
+	assertreg 0x7ffea810, r1
+	test_gr_a5a5 r2
+	test_gr_a5a5 r3
+	test_gr_a5a5 r4
+	test_gr_a5a5 r5
+	test_gr_a5a5 r6
+	test_gr_a5a5 r7
+	test_gr_a5a5 r8
+	test_gr_a5a5 r9
+	test_gr_a5a5 r10
+	test_gr_a5a5 r11
+	test_gr_a5a5 r12
+	test_gr_a5a5 r13
+	test_gr_a5a5 r14
+
+mulr_7:	! multiply 7ffff by 7ffff (overflow)
+	set_grs_a5a5
+	movi20	#0x7ffff, r0
+	movi20	#0x7ffff, r1
+	mulr	r0, r1
+	assertreg0   0x7ffff
+	assertreg 0xfff00001, r1
+	test_gr_a5a5 r2
+	test_gr_a5a5 r3
+	test_gr_a5a5 r4
+	test_gr_a5a5 r5
+	test_gr_a5a5 r6
+	test_gr_a5a5 r7
+	test_gr_a5a5 r8
+	test_gr_a5a5 r9
+	test_gr_a5a5 r10
+	test_gr_a5a5 r11
+	test_gr_a5a5 r12
+	test_gr_a5a5 r13
+	test_gr_a5a5 r14
+
+
+	pass
+
+	exit 0
+
+	
\ No newline at end of file
diff --git a/sim/testsuite/sim/sh/pass.s b/sim/testsuite/sim/sh/pass.s
new file mode 100644
index 0000000..cc3bbcc
--- /dev/null
+++ b/sim/testsuite/sim/sh/pass.s
@@ -0,0 +1,14 @@
+# sh testcase, pass
+# mach:	 all
+# as(sh):	-defsym sim_cpu=0
+# as(shdsp):	-defsym sim_cpu=1 -dsp 
+
+	.include "testutils.inc"
+
+	start
+	set_grs_a5a5
+	test_grs_a5a5
+	pass
+
+	exit 0
+
diff --git a/sim/testsuite/sim/sh/pushpop.s b/sim/testsuite/sim/sh/pushpop.s
new file mode 100644
index 0000000..9ee5bfd
--- /dev/null
+++ b/sim/testsuite/sim/sh/pushpop.s
@@ -0,0 +1,146 @@
+# sh testcase for push/pop (mov,movml,movmu...) insns.
+# mach:	 all
+# as(sh):	-defsym sim_cpu=0
+# as(shdsp):	-defsym sim_cpu=1 -dsp 
+
+	.include "testutils.inc"
+
+	start
+movml_1:
+	set_greg 0, r0
+	set_greg 1, r1
+	set_greg 2, r2
+	set_greg 3, r3
+	set_greg 4, r4
+	set_greg 5, r5
+	set_greg 6, r6
+	set_greg 7, r7
+	set_greg 8, r8
+	set_greg 9, r9
+	set_greg 10, r10
+	set_greg 11, r11
+	set_greg 12, r12
+	set_greg 13, r13
+	set_greg 14, r14
+	set_sreg 15, pr
+
+	movml.l		r15,@-r15
+
+	assertmem	stackt-4,  15
+	assertmem	stackt-8,  14
+	assertmem	stackt-12, 13
+	assertmem	stackt-16, 12
+	assertmem	stackt-20, 11
+	assertmem	stackt-24, 10
+	assertmem	stackt-28, 9
+	assertmem	stackt-32, 8
+	assertmem	stackt-36, 7
+	assertmem	stackt-40, 6
+	assertmem	stackt-44, 5
+	assertmem	stackt-48, 4
+	assertmem	stackt-52, 3
+	assertmem	stackt-56, 2
+	assertmem	stackt-60, 1
+	assertmem	stackt-64, 0
+
+	assertreg0	0
+	assertreg	1, r1
+	assertreg	2, r2
+	assertreg	3, r3
+	assertreg	4, r4
+	assertreg	5, r5
+	assertreg	6, r6
+	assertreg	7, r7
+	assertreg	8, r8
+	assertreg	9, r9
+	assertreg	10, r10
+	assertreg	11, r11
+	assertreg	12, r12
+	assertreg	13, r13
+	assertreg	14, r14
+	mov		r15, r0
+	assertreg0	stackt-64
+
+movml_2:
+	set_grs_a5a5
+	movml.l		@r15+, r15
+	assert_sreg	15, pr
+	assertreg0	0
+	assertreg	1, r1
+	assertreg	2, r2
+	assertreg	3, r3
+	assertreg	4, r4
+	assertreg	5, r5
+	assertreg	6, r6
+	assertreg	7, r7
+	assertreg	8, r8
+	assertreg	9, r9
+	assertreg	10, r10
+	assertreg	11, r11
+	assertreg	12, r12
+	assertreg	13, r13
+	assertreg	14, r14
+	mov		r15, r0
+	assertreg0	stackt
+
+movmu_1:
+	set_grs_a5a5
+	add	#1,r14
+	add	#2,r13
+	add	#3,r12
+	set_sreg 0xa5a5,pr
+
+	movmu.l	r12,@-r15
+
+	assert_sreg	0xa5a5,pr
+	assertreg	0xa5a5a5a6, r14
+	assertreg	0xa5a5a5a7, r13
+	assertreg	0xa5a5a5a8, r12
+	test_gr_a5a5	r11
+	test_gr_a5a5	r10
+	test_gr_a5a5	r9
+	test_gr_a5a5	r8
+	test_gr_a5a5	r7
+	test_gr_a5a5	r6
+	test_gr_a5a5	r5
+	test_gr_a5a5	r4
+	test_gr_a5a5	r3
+	test_gr_a5a5	r2
+	test_gr_a5a5	r1
+	test_gr_a5a5	r0
+	mov	r15, r0
+	assertreg	stackt-16, r0
+
+	assertmem	stackt-4, 0xa5a5
+	assertmem	stackt-8, 0xa5a5a5a6
+	assertmem	stackt-12, 0xa5a5a5a7
+	assertmem	stackt-16, 0xa5a5a5a8
+
+movmu_2:
+	set_grs_a5a5
+	movmu.l		@r15+,r12
+
+	assert_sreg	0xa5a5, pr
+	assertreg	0xa5a5a5a6, r14
+	assertreg	0xa5a5a5a7, r13
+	assertreg	0xa5a5a5a8, r12
+	test_gr_a5a5	r11
+	test_gr_a5a5	r10
+	test_gr_a5a5	r9
+	test_gr_a5a5	r8
+	test_gr_a5a5	r7
+	test_gr_a5a5	r6
+	test_gr_a5a5	r5
+	test_gr_a5a5	r4
+	test_gr_a5a5	r3
+	test_gr_a5a5	r2
+	test_gr_a5a5	r1
+	test_gr_a5a5	r0
+	mov	r15, r0
+	assertreg	stackt, r0
+
+	pass
+
+	exit 0
+
+	
\ No newline at end of file
diff --git a/sim/testsuite/sim/sh/resbank.s b/sim/testsuite/sim/sh/resbank.s
new file mode 100644
index 0000000..33801b8
--- /dev/null
+++ b/sim/testsuite/sim/sh/resbank.s
@@ -0,0 +1,268 @@
+# sh testcase for ldbank stbank resbank
+# mach:	 all
+# as(sh):	-defsym sim_cpu=0
+# as(shdsp):	-defsym sim_cpu=1 -dsp 
+
+	.include "testutils.inc"
+
+	.macro	SEND reg bankno regno
+	set_greg ((\bankno << 7) + (\regno << 2)), \reg
+	.endm
+
+	start
+
+stbank_1:
+	set_grs_a5a5
+	mov	#0, r0
+	SEND	r1, 0, 0
+	stbank	r0, @r1
+	mov	#1, r0
+	SEND	r1, 0, 1
+	stbank	r0, @r1
+	mov	#2, r0
+	SEND	r1, 0, 2
+	stbank	r0, @r1
+	mov	#3, r0
+	SEND	r1, 0, 3
+	stbank	r0, @r1
+	mov	#4, r0
+	SEND	r1, 0, 4
+	stbank	r0, @r1
+	mov	#5, r0
+	SEND	r1, 0, 5
+	stbank	r0, @r1
+	mov	#6, r0
+	SEND	r1, 0, 6
+	stbank	r0, @r1
+	mov	#7, r0
+	SEND	r1, 0, 7
+	stbank	r0, @r1
+	mov	#8, r0
+	SEND	r1, 0, 8
+	stbank	r0, @r1
+	mov	#9, r0
+	SEND	r1, 0, 9
+	stbank	r0, @r1
+	mov	#10, r0
+	SEND	r1, 0, 10
+	stbank	r0, @r1
+	mov	#11, r0
+	SEND	r1, 0, 11
+	stbank	r0, @r1
+	mov	#12, r0
+	SEND	r1, 0, 12
+	stbank	r0, @r1
+	mov	#13, r0
+	SEND	r1, 0, 13
+	stbank	r0, @r1
+	mov	#14, r0
+	SEND	r1, 0, 14
+	stbank	r0, @r1
+	mov	#15, r0
+	SEND	r1, 0, 15
+	stbank	r0, @r1
+	mov	#16, r0
+	SEND	r1, 0, 16
+	stbank	r0, @r1
+	mov	#17, r0
+	SEND	r1, 0, 17
+	stbank	r0, @r1
+	mov	#18, r0
+	SEND	r1, 0, 18
+	stbank	r0, @r1
+	mov	#19, r0
+	SEND	r1, 0, 19
+	stbank	r0, @r1
+
+	assertreg0	19
+	assertreg	19 << 2, r1
+	test_gr_a5a5	r2
+	test_gr_a5a5	r3
+	test_gr_a5a5	r4
+	test_gr_a5a5	r5
+	test_gr_a5a5	r6
+	test_gr_a5a5	r7
+	test_gr_a5a5	r8
+	test_gr_a5a5	r9
+	test_gr_a5a5	r10
+	test_gr_a5a5	r11
+	test_gr_a5a5	r12
+	test_gr_a5a5	r13
+	test_gr_a5a5	r14
+
+ldbank_1:
+	set_grs_a5a5
+	SEND	r1, 0, 0
+	ldbank	@r1, r0
+	assertreg0 0
+	SEND	r1, 0, 1
+	ldbank	@r1, r0
+	assertreg0 1
+	SEND	r1, 0, 2
+	ldbank	@r1, r0
+	assertreg0 2
+	SEND	r1, 0, 3
+	ldbank	@r1, r0
+	assertreg0 3
+	SEND	r1, 0, 4
+	ldbank	@r1, r0
+	assertreg0 4
+	SEND	r1, 0, 5
+	ldbank	@r1, r0
+	assertreg0 5
+	SEND	r1, 0, 6
+	ldbank	@r1, r0
+	assertreg0 6
+	SEND	r1, 0, 7
+	ldbank	@r1, r0
+	assertreg0 7
+	SEND	r1, 0, 8
+	ldbank	@r1, r0
+	assertreg0 8
+	SEND	r1, 0, 9
+	ldbank	@r1, r0
+	assertreg0 9
+	SEND	r1, 0, 10
+	ldbank	@r1, r0
+	assertreg0 10
+	SEND	r1, 0, 11
+	ldbank	@r1, r0
+	assertreg0 11
+	SEND	r1, 0, 12
+	ldbank	@r1, r0
+	assertreg0 12
+	SEND	r1, 0, 13
+	ldbank	@r1, r0
+	assertreg0 13
+	SEND	r1, 0, 14
+	ldbank	@r1, r0
+	assertreg0 14
+	SEND	r1, 0, 15
+	ldbank	@r1, r0
+	assertreg0 15
+	SEND	r1, 0, 16
+	ldbank	@r1, r0
+	assertreg0 16
+	SEND	r1, 0, 17
+	ldbank	@r1, r0
+	assertreg0 17
+	SEND	r1, 0, 18
+	ldbank	@r1, r0
+	assertreg0 18
+	SEND	r1, 0, 19
+	ldbank	@r1, r0
+	assertreg0 19
+
+	assertreg (19 << 2), r1
+	test_gr_a5a5 r2
+	test_gr_a5a5 r3
+	test_gr_a5a5 r4
+	test_gr_a5a5 r5
+	test_gr_a5a5 r6
+	test_gr_a5a5 r7
+	test_gr_a5a5 r8
+	test_gr_a5a5 r9
+	test_gr_a5a5 r10
+	test_gr_a5a5 r11
+	test_gr_a5a5 r12
+	test_gr_a5a5 r13
+	test_gr_a5a5 r14
+
+resbank_1:
+	set_grs_a5a5
+	mov	#1, r0
+	trapa	#13	! magic trap, sets ibnr
+
+	resbank
+
+	assertreg0	0
+	assertreg	1, r1
+	assertreg	2, r2
+	assertreg	3, r3
+	assertreg	4, r4
+	assertreg	5, r5
+	assertreg	6, r6
+	assertreg	7, r7
+	assertreg	8, r8
+	assertreg	9, r9
+	assertreg	10, r10
+	assertreg	11, r11
+	assertreg	12, r12
+	assertreg	13, r13
+	assertreg	14, r14
+	assert_sreg	15, mach
+	assert_sreg	17, pr
+	assert_creg	18, gbr
+	assert_sreg	19, macl
+
+resbank_2:
+	set_grs_a5a5
+	movi20	#555, r0
+	mov.l	r0, @-r15
+	add	#-1, r0
+	mov.l	r0, @-r15
+	add	#-1, r0
+	mov.l	r0, @-r15
+	add	#-1, r0
+	mov.l	r0, @-r15
+	add	#-1, r0
+	mov.l	r0, @-r15
+	add	#-1, r0
+	mov.l	r0, @-r15
+	add	#-1, r0
+	mov.l	r0, @-r15
+	add	#-1, r0
+	mov.l	r0, @-r15
+	add	#-1, r0
+	mov.l	r0, @-r15
+	add	#-1, r0
+	mov.l	r0, @-r15
+	add	#-1, r0
+	mov.l	r0, @-r15
+	add	#-1, r0
+	mov.l	r0, @-r15
+	add	#-1, r0
+	mov.l	r0, @-r15
+	add	#-1, r0
+	mov.l	r0, @-r15
+	add	#-1, r0
+	mov.l	r0, @-r15
+	add	#-1, r0
+	mov.l	r0, @-r15
+	add	#-1, r0
+	mov.l	r0, @-r15
+	add	#-1, r0
+	mov.l	r0, @-r15
+	add	#-1, r0
+	mov.l	r0, @-r15
+
+	set_sr_bit	(1 << 14)	! set BO
+
+	resbank
+
+	assert_sreg	555, macl
+	assert_sreg	554, mach
+	assert_creg	553, gbr
+	assert_sreg	552, pr
+	assertreg	551, r14
+	assertreg	550, r13
+	assertreg	549, r12
+	assertreg	548, r11
+	assertreg	547, r10
+	assertreg	546, r9
+	assertreg	545, r8
+	assertreg	544, r7
+	assertreg	543, r6
+	assertreg	542, r5
+	assertreg	541, r4
+	assertreg	540, r3
+	assertreg	539, r2
+	assertreg	538, r1
+	assertreg0	537
+
+	mov		r15, r0
+	assertreg0	stackt
+
+	pass
+
+	exit 0
diff --git a/sim/testsuite/sim/sh/testutils.inc b/sim/testsuite/sim/sh/testutils.inc
index 8d3895e..c9644b4 100644
--- a/sim/testsuite/sim/sh/testutils.inc
+++ b/sim/testsuite/sim/sh/testutils.inc
@@ -205,6 +205,19 @@ main:
 	bra	mfail
 	nop
 	.endm
+	# Branch if false -- 8k range
+	.macro bf8k label
+	bt	.Lbf8k\@
+	bra	\label
+.Lbf8k\@:
+	.endm
+
+	# Branch if true -- 8k range
+	.macro bt8k label
+	bf	.Lbt8k\@
+	bra	\label
+.Lbt8k\@:
+	.endm
 
 	# Assert value of register (any general register but r0)
 	# Preserves r0 on stack, restores it on success.
@@ -589,3 +602,16 @@ set_greg\@:
 	lds	r0, dsr
 	pop	r0
 	.endm
+
+	.macro	assertmem addr val
+	push	r0
+	mov.l	.Laddr\@, r0
+	mov.l	@r0, r0
+	assertreg0 \val
+	bra	.Lam\@
+	nop
+	.align	2
+.Laddr\@:
+	.long	\addr
+.Lam\@:	pop	r0
+	.endm