diff options
| author | Doug Evans <dje@google.com> | 1998-07-01 22:57:07 +0000 |
|---|---|---|
| committer | Doug Evans <dje@google.com> | 1998-07-01 22:57:07 +0000 |
| commit | 8686807e307f09e535db905e19a4ad57c03111ff (patch) | |
| tree | a9a536d63d4c9323ecb6d798f8f74616e6b82ad9 /sim | |
| parent | 54760676b27c14434092325459a644d25df25fcf (diff) | |
| download | gdb-8686807e307f09e535db905e19a4ad57c03111ff.zip gdb-8686807e307f09e535db905e19a4ad57c03111ff.tar.gz gdb-8686807e307f09e535db905e19a4ad57c03111ff.tar.bz2 | |
* sim/m32r/hw-trap.ms: New testcase.
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | sim/testsuite/sim/m32r/.Sanitize | 2 | ||||
| -rw-r--r-- | sim/testsuite/sim/m32r/hw-trap.ms | 31 |
3 files changed, 36 insertions, 1 deletions
diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog index f958a23..1683456 100644 --- a/sim/testsuite/ChangeLog +++ b/sim/testsuite/ChangeLog @@ -1,3 +1,7 @@ +Wed Jul 1 15:57:54 1998 Doug Evans <devans@seba.cygnus.com> + + * sim/m32r/hw-trap.ms: New testcase. + start-sanitize-sky Wed Jun 24 19:09:03 1998 Frank Ch. Eigler <fche@cygnus.com> diff --git a/sim/testsuite/sim/m32r/.Sanitize b/sim/testsuite/sim/m32r/.Sanitize index 53a2266..3f4cd86 100644 --- a/sim/testsuite/sim/m32r/.Sanitize +++ b/sim/testsuite/sim/m32r/.Sanitize @@ -163,7 +163,7 @@ xor.cgs xor3.cgs hello.ms - +hw-trap.ms Things-to-lose: diff --git a/sim/testsuite/sim/m32r/hw-trap.ms b/sim/testsuite/sim/m32r/hw-trap.ms new file mode 100644 index 0000000..6961e4f --- /dev/null +++ b/sim/testsuite/sim/m32r/hw-trap.ms @@ -0,0 +1,31 @@ +# output: pass +# mach(): m32r m32rx + + .include "testutils.inc" + + start + +; construct bra trap2_handler in trap 2 slot + ld24 r0,#bra_insn + ld r0,@r0 + ld24 r1,#trap2_handler + addi r1,#-0x48 ; pc relative address from trap 2 slot to handler + srai r1,#2 + or r0,r1 + ld24 r2,#0x48 ; address of trap 2 slot + st r0,@r2 + +; perform trap + ldi r4,#0 + trap #2 + test_h_gr r4,42 + + pass + +; trap 2 handler +trap2_handler: + ldi r4,#42 + rte + +bra_insn: + bra.l 0 |