Re-do load/store operations so that they work for both 32 and 64 bit

ISAs.
Enable tx39 as igen again.

5 files changed, 72 insertions, 19 deletions

diff --git a/sim/mips/.Sanitize b/sim/mips/.Sanitize
index 4253472..b8ed1af 100644
--- a/sim/mips/.Sanitize
+++ b/sim/mips/.Sanitize
@@ -78,7 +78,7 @@ Things-to-lose:
 
 Do-last:
 
-r5900_files="ChangeLog configure configure.in sim-main.h interp.c gencode.c mips.igen mips.dc m16.igen r5900.igen"
+r5900_files="ChangeLog configure configure.in sim-main.h interp.c gencode.c mips.igen mips.dc m16.igen r5900.igen tx.igen"
 
 if ( echo $* | grep keep\-r5900 > /dev/null ) ; then
 	for i in $r5900_files ; do
diff --git a/sim/mips/configure.in b/sim/mips/configure.in
index 07ad9ff..9772553 100644
--- a/sim/mips/configure.in
+++ b/sim/mips/configure.in
@@ -140,7 +140,7 @@ case "${target}" in
 			;;
 # end-sanitize-tx19
   mipstx39*-*-*)	sim_default_gen=IGEN
-			sim_use_gen=NO
+			sim_use_gen=IGEN
 			sim_igen_filter="32,f"
 			sim_igen_machine="-M r3900"
 			;;
diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index 7be7ac6..4e69b57 100644
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -82,9 +82,7 @@ char* pr_uword64 PARAMS ((uword64 addr));
 
 
 /* Get the simulator engine description, without including the code: */
-#if (WITH_IGEN)
-#define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3)
-#else
+#if !(WITH_IGEN)
 #define SIM_MANIFESTS
 #include "oengine.c"
 #undef SIM_MANIFESTS
@@ -1626,7 +1624,7 @@ load_memory (SIM_DESC sd,
 	     uword64* memvalp,
 	     uword64* memval1p,
 	     int CCA,
-	     int AccessLength,
+	     unsigned int AccessLength,
 	     address_word pAddr,
 	     address_word vAddr,
 	     int IorD)
@@ -1653,9 +1651,9 @@ load_memory (SIM_DESC sd,
   if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
     {
       /* In reality this should be a Bus Error */
-      sim_io_error (sd, "AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",
+      sim_io_error (sd, "LOAD AccessLength of %d would extend over %d bit aligned boundary for physical address 0x%s\n",
 		    AccessLength,
-		    (LOADDRMASK + 1) << 2,
+		    (LOADDRMASK + 1) << 3,
 		    pr_addr (pAddr));
     }
 
@@ -1717,13 +1715,13 @@ load_memory (SIM_DESC sd,
 	 (int)(pAddr & LOADDRMASK),pr_uword64(value1),pr_uword64(value));
 #endif /* DEBUG */
   
-  /* See also store_memory. */
-  if (AccessLength <= AccessLength_DOUBLEWORD)
+  /* See also store_memory. Position data in correct byte lanes. */
+  if (AccessLength <= LOADDRMASK)
     {
       if (BigEndianMem)
 	/* for big endian target, byte (pAddr&LOADDRMASK == 0) is
 	   shifted to the most significant byte position.  */
-	value <<= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8);
+	value <<= (((LOADDRMASK - (pAddr & LOADDRMASK)) - AccessLength) * 8);
       else
 	/* For little endian target, byte (pAddr&LOADDRMASK == 0)
 	   is already in the correct postition. */
@@ -1758,7 +1756,7 @@ store_memory (SIM_DESC sd,
 	      sim_cpu *cpu,
 	      address_word cia,
 	      int CCA,
-	      int AccessLength,
+	      unsigned int AccessLength,
 	      uword64 MemElem,
 	      uword64 MemElem1,   /* High order 64 bits */
 	      address_word pAddr,
@@ -1774,7 +1772,10 @@ store_memory (SIM_DESC sd,
 #endif /* WARN_MEM */
   
   if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
-    sim_io_error(sd,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength,(LOADDRMASK + 1)<<2,pr_addr(pAddr));
+    sim_io_error (sd, "STORE AccessLength of %d would extend over %d bit aligned boundary for physical address 0x%s\n",
+		  AccessLength,
+		  (LOADDRMASK + 1) << 3,
+		  pr_addr(pAddr));
   
 #if defined(TRACE)
   dotrace (SD, CPU, tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store");
@@ -1784,13 +1785,13 @@ store_memory (SIM_DESC sd,
   printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem));
 #endif /* DEBUG */
   
-  /* See also load_memory */
-  if (AccessLength <= AccessLength_DOUBLEWORD)
+  /* See also load_memory. Position data in correct byte lanes. */
+  if (AccessLength <= LOADDRMASK)
     {
       if (BigEndianMem)
 	/* for big endian target, byte (pAddr&LOADDRMASK == 0) is
 	   shifted to the most significant byte position.  */
-	MemElem >>= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8);
+	MemElem >>= (((LOADDRMASK - (pAddr & LOADDRMASK)) - AccessLength) * 8);
       else
 	/* For little endian target, byte (pAddr&LOADDRMASK == 0)
 	   is already in the correct postition. */
@@ -1954,7 +1955,7 @@ signal_exception (SIM_DESC sd,
         code = (instruction >> 6) & 0xFFFFF;
         
         sim_io_eprintf(sd,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
-                    code, pr_addr(cia));
+		       code, pr_addr(cia));
       }
      break;
 
diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h
index acbb527..6cd51d9 100644
--- a/sim/mips/sim-main.h
+++ b/sim/mips/sim-main.h
@@ -824,15 +824,22 @@ decode_coproc (SD, CPU, cia, (instruction))
 #define AccessLength_DOUBLEWORD (7)
 #define AccessLength_QUADWORD   (15)
 
+#if (WITH_IGEN)
+#define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
+		    ? AccessLength_DOUBLEWORD /*7*/ \
+		    : AccessLength_WORD /*3*/)
+#define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
+#endif
+
 int address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
 address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
 
-void load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, int AccessLength, address_word pAddr, address_word vAddr, int IorD));
+void load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD));
 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
 load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
 
-void store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
+void store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
 store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
 
diff --git a/sim/mips/tx.igen b/sim/mips/tx.igen
new file mode 100644
index 0000000..7e4af39
--- /dev/null
+++ b/sim/mips/tx.igen
@@ -0,0 +1,45 @@
+// -*- C -*-
+//
+// toshiba specific instructions.
+//
+
+011100,5.RS,5.RT,5.RD,00000000000:MMINORM:::MADD
+"madd r<RS>, r<RT>":RD == 0
+"madd r<RD>, r<RS>, r<RT>"
+*r3900
+// start-sanitize-r5900
+*r5900:
+// end-sanitize-r5900
+{
+  signed64 prod = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+		   + ((signed64) EXTEND32 (GPR[RT])
+		      * (signed64) EXTEND32 (GPR[RS])));
+  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+  LO = EXTEND32 (prod);
+  HI = EXTEND32 (VH4_8 (prod));
+  TRACE_ALU_RESULT2 (HI, LO);
+  if(RD != 0 )
+    GPR[RD] = LO;
+}
+
+
+011100,5.RS,5.RT,5.RD,00000000001:MMINORM:::MADDU
+"maddu r<RS>, r<RT>":RD == 0
+"maddu r<RD>, r<RS>, r<RT>"
+*r3900
+// start-sanitize-r5900
+*r5900:
+// end-sanitize-r5900
+{
+  unsigned64 prod = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+		     + ((unsigned64) VL4_8 (GPR[RS])
+			* (unsigned64) VL4_8 (GPR[RT])));
+  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+  LO = EXTEND32 (prod);
+  HI = EXTEND32 (VH4_8 (prod));
+  TRACE_ALU_RESULT2 (HI, LO);
+  if(RD != 0)
+    GPR[RD] = LO;
+}
+
+