Add multi-sim support to v850/v850e/v850eq simulators.

8 files changed, 1625 insertions, 483 deletions

diff --git a/sim/v850/.Sanitize b/sim/v850/.Sanitize
index 5d25732..e3c9718 100644
--- a/sim/v850/.Sanitize
+++ b/sim/v850/.Sanitize
@@ -29,6 +29,8 @@ config.in
 configure
 configure.in
 v850_sim.h
+v850.igen
+v850-dc
 gencode.c
 interp.c
 simops.c
diff --git a/sim/v850/ChangeLog b/sim/v850/ChangeLog
index e4d922e..a023237 100644
--- a/sim/v850/ChangeLog
+++ b/sim/v850/ChangeLog
@@ -1,3 +1,65 @@
+Tue Sep  9 01:29:50 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* simops.c (trace_input, trace_output): Use sim_io_printf.
+	(OP_620): Pass correct argument to trace.
+	(OP_E607E0): Ditto.
+	(trace_input): Obtain prog_bfd, text_start et.al from simulator
+ 	struct.
+
+Mon Sep  8 21:03:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* v850.igen: New file.
+	* v850-dc: New file.
+
+Mon Sep  8 18:33:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+
+	* sim-main.h (SEXT16): Delete, use EXTEND16.
+	(SEXT8): Delete, use EXTEND8.
+	(SEXT32): Delete, used?
+	(SEXT40, SEXT44, SEXT64): Use UNSIGNED64 for constants, not ...LL.
+	(WITH_TARGET_WORD_MSB): Define as 31. v850 little bit endian.
+	
+	* simops.c: Use EXTEND15 from sim-bits instead of SEXT16.
+
+	* sim-main.h (DEBUG_TRACE, DEBUG_VALUES, v850_debug): Delete,
+ 	replace with TRACE_INSN_P and TRACE_ALU_P.
+
+	* simops.c (trace_input, trace_output): Update.
+
+	* interp.c (sim_engine_run): Delete.
+	(lookup_hash): Delete.
+	(sim_open): Do not fill hash table.
+	(sim_trace): Delete.
+
+Fri Sep  5 17:04:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* simops.c (OP_FFFF): Use sim_engine_halt.
+	(OP_12007E0): Ditto.
+	(OP_10007E0): Ditto.
+
+	* sim-main.h (struct sim_cpu): Delete member exception. Using
+ 	sim-engine et.al.
+
+	* interp.c (sim_info): Do not do anything in sim-info.
+	(sim_stop): Delete, replace with sim-stop.
+	(sim_stop_reason): Delete, replace with sim-reason.
+
+	* sim-main.h (WITH_WATCHPOINTS): Define.
+	(WITH_MODULO_MEMORY): Define
+	
+	* Makefile.in (SIM_OBJS): Add sim-resume, sim-watch, sim-stop,
+ 	sim-reason.
+
+	* interp.c (enum interrupt_cond_type): Delete.
+	(struct interrupt_generator): Delete.
+	(enum interrupt_type): Drop int_none.
+	(sim_open): Initialize WATCHPOINT module.
+	(sim_resume, sim_run): Rename sim_resume to sim_run.
+	(sim_engine_run): Replace interrupt code with call to sim-events.
+	(sim_set_interrupt): Delete.
+	(sim_parse_number): Delete.
+
 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
 
 	* configure: Regenerated to track ../common/aclocal.m4 changes.
diff --git a/sim/v850/Makefile.in b/sim/v850/Makefile.in
index f067eb6..f0c5521 100644
--- a/sim/v850/Makefile.in
+++ b/sim/v850/Makefile.in
@@ -18,7 +18,10 @@
 
 ## COMMON_PRE_CONFIG_FRAG
 
-SIM_OBJS = interp.o table.o simops.o \
+SIM_OBJS = \
+	simops.o interp.o \
+	itable.o semantics.o idecode.o icache.o engine.o irun.o support.o \
+	sim-bits.o \
 	sim-config.o \
 	sim-core.o \
 	sim-engine.o \
@@ -32,42 +35,121 @@ SIM_OBJS = interp.o table.o simops.o \
 	sim-module.o \
 	sim-options.o \
 	sim-profile.o \
+	sim-resume.o \
+	sim-reason.o \
+	sim-stop.o \
 	sim-trace.o \
+	sim-watch.o \
 	sim-utils.o
 SIM_RUN_OBJS = nrun.o
 
+# List of extra dependencies.
+# Generally this consists of simulator specific files included by sim-main.h.
+SIM_EXTRA_DEPS = v850_sim.h sim-main.h simops.h
+
 # List of flags to always pass to $(CC)
 SIM_WARNINGS=@sim_warnings@
 SIM_ENDIAN=@sim_endian@
 SIM_HOSTENDIAN=@sim_hostendian@
-SIM_EXTRA_CFLAGS = -I$(srcdir)/../../newlib/libc/sys/sysnecv850 \
+SIM_EXTRA_CFLAGS = \
+	-DDEBUG \
+	-I$(srcdir)/../../newlib/libc/sys/sysnecv850 \
 	$(SIM_WARNINGS) \
 	$(SIM_ENDIAN) \
 	$(SIM_HOSTENDIAN)
 SIM_EXTRA_CLEAN = clean-extra
 
-INCLUDE = v850_sim.h sim-main.h $(srcdir)/../../include/callback.h
+INCLUDE = simops.h v850_sim.h sim-main.h $(srcdir)/../../include/callback.h
 
 ## COMMON_POST_CONFIG_FRAG
 
-simops.h: gencode
-	./gencode -h >$@
-
-table.c: gencode simops.h
-	./gencode >$@
-
+simops.h table.c: tmp-gencode
+tmp-gencode: gencode simops.h
+	./gencode >tmp-table.c
+	mv tmp-table.c table.c
+	./gencode -h >tmp-simops.h
+	mv tmp-simops.h simops.h
+	touch tmp-gencode
 gencode.o: gencode.c $(INCLUDE)
 	$(CC_FOR_BUILD) $(BUILD_CFLAGS) -c $(srcdir)/gencode.c
-
 v850-opc.o: $(srcdir)/../../opcodes/v850-opc.c
 	$(CC_FOR_BUILD) $(BUILD_CFLAGS) -c $<
-
 gencode: gencode.o v850-opc.o
 	$(CC_FOR_BUILD) $(BUILD_CFLAGS) -o gencode gencode.o v850-opc.o
 
-clean-extra:
+
+
+BUILT_SRC_FROM_IGEN = \
+	icache.h \
+	icache.c \
+	idecode.h \
+	idecode.c \
+	semantics.h \
+	semantics.c \
+	model.h \
+	model.c \
+	support.h \
+	support.c \
+	itable.h \
+	itable.c \
+	engine.h \
+	engine.c \
+	irun.c
+$(BUILT_SRC_FROM_IGEN): tmp-igen simops.h
+#
+
+.PHONY: clean-igen
+clean-igen:
+	rm -f $(BUILT_SRC_FROM_IGEN)
+	rm -f tmp-igen tmp-insns
+
+../igen/igen:
+	cd ../igen && $(MAKE)
+
+IGEN_INSN=$(srcdir)/v850.igen
+IGEN_DC=$(srcdir)/v850-dc
+tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen
+	cd ../igen && $(MAKE)
+	../igen/igen \
+		-G gen-direct-access \
+		-i $(IGEN_INSN) \
+		-o $(IGEN_DC) \
+		-x \
+		-n icache.h    -hc tmp-icache.h \
+		-n icache.c    -c  tmp-icache.c \
+		-n semantics.h -hs tmp-semantics.h \
+		-n semantics.c -s  tmp-semantics.c \
+		-n idecode.h   -hd tmp-idecode.h \
+		-n idecode.c   -d  tmp-idecode.c \
+		-n model.h     -hm tmp-model.h \
+		-n model.c     -m  tmp-model.c \
+		-n support.h   -hf tmp-support.h \
+		-n support.c   -f  tmp-support.c \
+		-n itable.h    -ht tmp-itable.h \
+		-n itable.c    -t  tmp-itable.c \
+		-n engine.h    -he tmp-engine.h \
+		-n engine.c    -e  tmp-engine.c \
+		-n irun.c      -r  tmp-irun.c
+	$(srcdir)/../../move-if-change tmp-icache.h icache.h
+	$(srcdir)/../../move-if-change tmp-icache.c icache.c
+	$(srcdir)/../../move-if-change tmp-idecode.h idecode.h
+	$(srcdir)/../../move-if-change tmp-idecode.c idecode.c
+	$(srcdir)/../../move-if-change tmp-semantics.h semantics.h
+	$(srcdir)/../../move-if-change tmp-semantics.c semantics.c
+	$(srcdir)/../../move-if-change tmp-model.h model.h
+	$(srcdir)/../../move-if-change tmp-model.c model.c
+	$(srcdir)/../../move-if-change tmp-support.h support.h
+	$(srcdir)/../../move-if-change tmp-support.c support.c
+	$(srcdir)/../../move-if-change tmp-itable.h itable.h
+	$(srcdir)/../../move-if-change tmp-itable.c itable.c
+	$(srcdir)/../../move-if-change tmp-engine.h engine.h
+	$(srcdir)/../../move-if-change tmp-engine.c engine.c
+	$(srcdir)/../../move-if-change tmp-irun.c irun.c
+	touch tmp-igen
+
+clean-extra: clean-igen
 	rm -f table.c simops.h gencode
 
-interp.o: interp.c table.c $(INCLUDE)
-simops.o: simops.c $(INCLUDE)
-table.o: table.c
+#interp.o: interp.c table.c $(INCLUDE)
+simops.o: simops.c simops.h
+#table.o: table.c
diff --git a/sim/v850/interp.c b/sim/v850/interp.c
index 49b2996..e77cb48 100644
--- a/sim/v850/interp.c
+++ b/sim/v850/interp.c
@@ -17,13 +17,24 @@
 
 #include "bfd.h"
 
+#ifndef INLINE
+#ifdef __GNUC__
+#define INLINE inline
+#else
+#define INLINE
+#endif
+#endif
+
 
 /* For compatibility */
 SIM_DESC simulator;
 
+
+
+/* v850 interrupt model */
+
 enum interrupt_type
 {
-  int_none,
   int_reset,
   int_nmi,
   int_intov1,
@@ -35,26 +46,7 @@ enum interrupt_type
   num_int_types
 };
 
-enum interrupt_cond_type
-{
-  int_cond_none,
-  int_cond_pc,
-  int_cond_time
-};
-
-struct interrupt_generator
-{
-  enum interrupt_type type;
-  enum interrupt_cond_type cond_type;
-  int number;
-  SIM_ADDR address;
-  unsigned long time;
-  int enabled;
-  struct interrupt_generator *next;
-};
-
 char *interrupt_names[] = {
-  "",
   "reset",
   "nmi",
   "intov1",
@@ -66,20 +58,82 @@ char *interrupt_names[] = {
   NULL
 };
 
-struct interrupt_generator *intgen_list;
-
-/* True if a non-maskable (such as NMI or reset) interrupt generator
-   is present.  */
-
-static int have_nm_generator;
-
-#ifndef INLINE
-#ifdef __GNUC__
-#define INLINE inline
-#else
-#define INLINE
-#endif
-#endif
+static void
+do_interrupt (sd, data)
+     SIM_DESC sd;
+     void *data;
+{
+  enum interrupt_type inttype = *(int*)data;
+  /* Disable further interrupts.  */
+  PSW |= PSW_ID;
+  /* Indicate that we're doing interrupt not exception processing.  */
+  PSW &= ~PSW_EP;
+  if (inttype == int_reset)
+    {
+      PC = 0;
+      PSW = 0x20;
+      ECR = 0;
+      /* (Might be useful to init other regs with random values.) */
+    }
+  else if (inttype == int_nmi)
+    {
+      if (PSW & PSW_NP)
+	{
+	  /* We're already working on an NMI, so this one must wait
+	     around until the previous one is done.  The processor
+	     ignores subsequent NMIs, so we don't need to count them.  */
+	  State.pending_nmi = 1;
+	}
+      else
+	{
+	  FEPC = PC;
+	  FEPSW = PSW;
+	  /* Set the FECC part of the ECR. */
+	  ECR &= 0x0000ffff;
+	  ECR |= 0x10;
+	  PSW |= PSW_NP;
+	  PC = 0x10;
+	}
+    }
+  else
+    {
+      EIPC = PC;
+      EIPSW = PSW;
+      /* Clear the EICC part of the ECR, will set below. */
+      ECR &= 0xffff0000;
+      switch (inttype)
+	{
+	case int_intov1:
+	  PC = 0x80;
+	  ECR |= 0x80;
+	  break;
+	case int_intp10:
+	  PC = 0x90;
+	  ECR |= 0x90;
+	  break;
+	case int_intp11:
+	  PC = 0xa0;
+	  ECR |= 0xa0;
+	  break;
+	case int_intp12:
+	  PC = 0xb0;
+	  ECR |= 0xb0;
+	  break;
+	case int_intp13:
+	  PC = 0xc0;
+	  ECR |= 0xc0;
+	  break;
+	case int_intcm4:
+	  PC = 0xd0;
+	  ECR |= 0xd0;
+	  break;
+	default:
+	  /* Should never be possible.  */
+	  abort ();
+	  break;
+	}
+    }
+}
 
 /* These default values correspond to expected usage for the chip.  */
 
@@ -87,7 +141,6 @@ int v850_debug;
 
 uint32 OP[4];
 
-static struct hash_entry *lookup_hash PARAMS ((SIM_DESC sd, uint32 ins));
 static long hash PARAMS ((long));
 #if 0
 static void do_format_1_2 PARAMS ((uint32));
@@ -134,6 +187,7 @@ hash(insn)
   return (insn & 0x07e0) >> 5;
 }
 
+#if 0
 static struct hash_entry *
 lookup_hash (sd, ins)
      SIM_DESC sd;
@@ -154,6 +208,7 @@ lookup_hash (sd, ins)
     }
   return (h);
 }
+#endif
 
 SIM_DESC
 sim_open (kind, cb, abfd, argv)
@@ -164,12 +219,20 @@ sim_open (kind, cb, abfd, argv)
 {
   char *buf;
   SIM_DESC sd = sim_state_alloc (kind, cb);
+#if 0
   struct simops *s;
   struct hash_entry *h;
+#endif
 
   /* for compatibility */
   simulator = sd;
 
+  /* FIXME: should be better way of setting up interrupts */
+  STATE_WATCHPOINTS (sd)->pc = &(PC);
+  STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
+  STATE_WATCHPOINTS (sd)->interrupt_handler = do_interrupt;
+  STATE_WATCHPOINTS (sd)->interrupt_names = interrupt_names;
+
   if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
     return 0;
 
@@ -224,6 +287,7 @@ sim_open (kind, cb, abfd, argv)
       return 0;
     }
 
+#if 0
   /* put all the opcodes in the hash table */
   for (s = Simops; s->func; s++)
     {
@@ -242,6 +306,7 @@ sim_open (kind, cb, abfd, argv)
       h->mask = s->mask;
       h->opcode = s->opcode;
     }
+#endif
 
   return sd;
 }
@@ -255,8 +320,6 @@ sim_close (sd, quitting)
   sim_module_uninstall (sd);
 }
 
-static void do_interrupt PARAMS ((SIM_DESC sd, enum interrupt_type));
-
 int
 sim_stop (sd)
      SIM_DESC sd;
@@ -264,25 +327,17 @@ sim_stop (sd)
   return 0;
 }
 
+#if 0
 void
-sim_resume (sd, step, siggnal)
+sim_engine_run (sd, next_cpu_nr, siggnal)
      SIM_DESC sd;
-     int step, siggnal;
+     int next_cpu_nr;
+     int siggnal;
 {
-  SIM_ELAPSED_TIME start_time;
   uint32 inst;
   SIM_ADDR oldpc;
-  struct interrupt_generator *intgen;
-
-  if (step)
-    State.exception = SIGTRAP;
-  else
-    State.exception = 0;
-
 
-  start_time = sim_elapsed_time_get ();
-
-  do
+  while (1)
     {
       struct hash_entry * h;
       /* Fetch the current instruction.  */
@@ -311,118 +366,15 @@ sim_resume (sd, step, siggnal)
 	  break;
 	}
       
-      /* Check for and handle pending interrupts.  */
-      if (intgen_list && (have_nm_generator || !(PSW & PSW_ID)))
-	{
-	  intgen = NULL;
-	  for (intgen = intgen_list; intgen != NULL; intgen = intgen->next)
-	    {
-	      if (intgen->cond_type == int_cond_pc
-		  && oldpc == intgen->address
-		  && intgen->enabled)
-		{
-		  break;
-		}
-	      else if (intgen->cond_type == int_cond_time
-		       && intgen->enabled)
-		{
-		  SIM_ELAPSED_TIME delta;
-		  delta = sim_elapsed_time_since (start_time);
-		  if (delta > intgen->time)
-		    {
-		      intgen->enabled = 0;
-		      break;
-		    }
-		}
-	    }
-	  if (intgen)
-	    do_interrupt (sd, intgen->type);
-	}
-      else if (State.pending_nmi)
-	{
-	  State.pending_nmi = 0;
-	  do_interrupt (sd, int_nmi);
-	}
-    }
-  while (!State.exception);
-}
-
-static void
-do_interrupt (sd, inttype)
-     SIM_DESC sd;
-     enum interrupt_type inttype;
-{
-  /* Disable further interrupts.  */
-  PSW |= PSW_ID;
-  /* Indicate that we're doing interrupt not exception processing.  */
-  PSW &= ~PSW_EP;
-  if (inttype == int_reset)
-    {
-      PC = 0;
-      PSW = 0x20;
-      ECR = 0;
-      /* (Might be useful to init other regs with random values.) */
-    }
-  else if (inttype == int_nmi)
-    {
-      if (PSW & PSW_NP)
-	{
-	  /* We're already working on an NMI, so this one must wait
-	     around until the previous one is done.  The processor
-	     ignores subsequent NMIs, so we don't need to count them.  */
-	  State.pending_nmi = 1;
-	}
-      else
-	{
-	  FEPC = PC;
-	  FEPSW = PSW;
-	  /* Set the FECC part of the ECR. */
-	  ECR &= 0x0000ffff;
-	  ECR |= 0x10;
-	  PSW |= PSW_NP;
-	  PC = 0x10;
-	}
-    }
-  else
-    {
-      EIPC = PC;
-      EIPSW = PSW;
-      /* Clear the EICC part of the ECR, will set below. */
-      ECR &= 0xffff0000;
-      switch (inttype)
+      if (sim_events_tick (sd))
 	{
-	case int_intov1:
-	  PC = 0x80;
-	  ECR |= 0x80;
-	  break;
-	case int_intp10:
-	  PC = 0x90;
-	  ECR |= 0x90;
-	  break;
-	case int_intp11:
-	  PC = 0xa0;
-	  ECR |= 0xa0;
-	  break;
-	case int_intp12:
-	  PC = 0xb0;
-	  ECR |= 0xb0;
-	  break;
-	case int_intp13:
-	  PC = 0xc0;
-	  ECR |= 0xc0;
-	  break;
-	case int_intcm4:
-	  PC = 0xd0;
-	  ECR |= 0xd0;
-	  break;
-	default:
-	  /* Should never be possible.  */
-	  abort ();
-	  break;
+	  sim_events_process (sd);
 	}
     }
 }
+#endif
 
+#if 0
 int
 sim_trace (sd)
      SIM_DESC sd;
@@ -433,13 +385,14 @@ sim_trace (sd)
   sim_resume (sd, 0, 0);
   return 1;
 }
+#endif
 
 void
 sim_info (sd, verbose)
      SIM_DESC sd;
      int verbose;
 {
-  sim_io_printf (sd, "sim_info\n");
+  /* do nothing */
 }
 
 SIM_RC
@@ -455,28 +408,6 @@ sim_create_inferior (sd, prog_bfd, argv, env)
   return SIM_RC_OK;
 }
 
-/* All the code for exiting, signals, etc needs to be revamped.
-
-   This is enough to get c-torture limping though.  */
-
-void
-sim_stop_reason (sd, reason, sigrc)
-     SIM_DESC sd;
-     enum sim_stop *reason;
-     int *sigrc;
-{
-  if (State.exception == SIG_V850_EXIT)
-    {
-      *reason = sim_exited;
-      *sigrc = State.regs[7];
-    }
-  else
-    {
-      *reason = sim_stopped;
-      *sigrc = State.exception;
-    }
-}
-
 void
 sim_fetch_register (sd, rn, memory)
      SIM_DESC sd;
@@ -495,156 +426,6 @@ sim_store_register (sd, rn, memory)
   State.regs[rn] = T2H_4 (*(unsigned32*)memory);
 }
 
-static int
-sim_parse_number (str, rest)
-     char *str, **rest;
-{
-  if (str[0] == '0' && str[1] == 'x')
-    return strtoul (str, rest, 16);
-  else if (str[0] == '0')
-    return strtoul (str, rest, 16);
-  else
-    return strtoul (str, rest, 10);
-}
-
-int current_intgen_number = 1;
-
-static void
-sim_set_interrupt (sd, spec)
-     SIM_DESC sd;
-     char *spec;
-{
-  int i, num;
-  char **argv;
-  struct interrupt_generator *intgen, *tmpgen;
-  extern char **buildargv ();
-
-  argv = buildargv (spec);
-
-  if (*argv && ! strcmp (*argv, "add"))
-    {
-      /* Create a new interrupt generator object.  */
-      intgen = (struct interrupt_generator *)
-	malloc (sizeof(struct interrupt_generator));
-      intgen->type = int_none;
-      intgen->cond_type = int_cond_none;
-      intgen->address = 0;
-      intgen->time = 0;
-      intgen->enabled = 0;
-      ++argv;
-      /* Match on interrupt type name.  */
-      for (i = 0; i < num_int_types; ++i)
-	{
-	  if (*argv && ! strcmp (*argv, interrupt_names[i]))
-	    {
-	      intgen->type = i;
-	      break;
-	    }
-	}
-      if (intgen->type == int_none)
-	{
-	  sim_io_printf (sd, "Interrupt type unknown; known types are\n");
-	  for (i = 0; i < num_int_types; ++i)
-	    {
-	      sim_io_printf (sd, " %s", interrupt_names[i]);
-	    }
-	  sim_io_printf (sd, "\n");
-	  free (intgen);
-	  return;
-	}
-      ++argv;
-      intgen->address = 0;
-      intgen->time = 0;
-      if (*argv && ! strcmp (*argv, "pc"))
-	{
-	  intgen->cond_type = int_cond_pc;
-	  ++argv;
-	  intgen->address = sim_parse_number (*argv, NULL);
-	}
-      else if (*argv && ! strcmp (*argv, "time"))
-	{
-	  intgen->cond_type = int_cond_time;
-	  ++argv;
-	  intgen->time = sim_parse_number (*argv, NULL);
-	}
-      else
-	{
-	  sim_io_printf (sd, "Condition type must be `pc' or `time'.\n");
-	  free (intgen);
-	  return;
-	}
-      /* We now have a valid interrupt generator.  Number it and add
-	 to the list of generators.  */
-      intgen->number = current_intgen_number++;
-      intgen->enabled = 1;
-      intgen->next = intgen_list;
-      intgen_list = intgen;
-      sim_io_printf (sd, "Interrupt generator %d (NMI) at pc=0x%x, time=%ld.\n", intgen_list->number, intgen_list->address, intgen_list->time);
-    }
-  else if (*argv && !strcmp (*argv, "remove"))
-    {
-      ++argv;
-      num = sim_parse_number (*argv, NULL);
-      tmpgen = NULL;
-      if (intgen_list)
-	{
-	  if (intgen_list->number == num)
-	    {
-	      tmpgen = intgen_list;
-	      intgen_list = intgen_list->next;
-	    }
-	  else
-	    {
-	      for (intgen = intgen_list; intgen != NULL; intgen = intgen->next)
-		{
-		  if (intgen->next != NULL && intgen->next->number == num)
-		    {
-		      tmpgen = intgen->next;
-		      intgen->next = intgen->next->next;
-		      break;
-		    }
-		}
-	    }
-	  if (tmpgen)
-	    free (tmpgen);
-	  else
-	    sim_io_printf (sd, "No interrupt generator numbered %d, ignoring.\n", num);
-	}
-    }
-  else if (*argv && !strcmp (*argv, "info"))
-    {
-      if (intgen_list)
-	{
-	  for (intgen = intgen_list; intgen != NULL; intgen = intgen->next)
-	    sim_io_printf (sd, "Interrupt generator %d (%s) at pc=0x%lx/time=%ld%s.\n",
-			   intgen->number,
-			   interrupt_names[intgen->type],
-			   (long) intgen->address,
-			   intgen->time,
-			   (intgen->enabled ? "" : " (disabled)"));
-	}
-      else
-	{
-	  sim_io_printf (sd, "No interrupt generators defined.\n"); 
-	}
-
-    }
-  else
-    {
-      sim_io_printf (sd, "Invalid interrupt command, must be one of `add', `remove', or `info'.\n");
-    }
-  /* Cache the presence of a non-maskable generator.  */
-  have_nm_generator = 0;
-  for (intgen = intgen_list; intgen != NULL; intgen = intgen->next)
-    {
-      if (intgen->type == int_nmi || intgen->type == int_reset)
-	{
-	  have_nm_generator = 1;
-	  break;
-	}
-    }
-}
-
 void
 sim_do_command (sd, cmd)
      SIM_DESC sd;
@@ -653,13 +434,13 @@ sim_do_command (sd, cmd)
   char *mm_cmd = "memory-map";
   char *int_cmd = "interrupt";
 
-  if (strncmp (cmd, mm_cmd, strlen (mm_cmd) == 0))
-    sim_io_eprintf (sd, "`memory-map' command replaced by `sim memory'\n");
-
-  else if (! strncmp (cmd, int_cmd, strlen (int_cmd))
-      && strchr (" 	", cmd[strlen(int_cmd)]))
-    sim_set_interrupt (sd, cmd + strlen(int_cmd) + 1);
-
-  else if (sim_args_command (sd, cmd) != SIM_RC_OK)
-    sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
+  if (sim_args_command (sd, cmd) != SIM_RC_OK)
+    {
+      if (strncmp (cmd, mm_cmd, strlen (mm_cmd) == 0))
+	sim_io_eprintf (sd, "`memory-map' command replaced by `sim memory'\n");
+      else if (strncmp (cmd, int_cmd, strlen (int_cmd)) == 0)
+	sim_io_eprintf (sd, "`interrupt' command replaced by `sim watch'\n");
+      else
+	sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
+    }
 }
diff --git a/sim/v850/sim-main.h b/sim/v850/sim-main.h
index f38ef1c..52f3086 100644
--- a/sim/v850/sim-main.h
+++ b/sim/v850/sim-main.h
@@ -1,3 +1,7 @@
+#define WITH_MODULO_MEMORY 1
+#define WITH_WATCHPOINTS 1
+#define WITH_TARGET_WORD_MSB 31
+
 #include "sim-basics.h"
 
 typedef address_word sim_cia;
@@ -24,7 +28,6 @@ typedef struct _v850_regs {
   reg_t sregs[32];		/* system registers, including psw */
   reg_t pc;
   int dummy_mem;		/* where invalid accesses go */
-  int exception;
   int pending_nmi;
 } v850_regs;
 
@@ -36,6 +39,8 @@ struct _sim_cpu
   sim_cpu_base base;
 };
 
+#define CPU_CIA(CPU) ((CPU)->reg.pc)
+
 struct sim_state {
   sim_cpu cpu[MAX_NR_PROCESSORS];
 #if (WITH_SMP)
@@ -63,15 +68,43 @@ extern SIM_DESC simulator;
 #define V850_HIGH_START 0xffe000
 
 
-#define DEBUG_TRACE		0x00000001
-#define DEBUG_VALUES		0x00000002
-
-extern int v850_debug;
-
 #define SIG_V850_EXIT	-1	/* indication of a normal exit */
 
 extern uint32 OP[4];
+
+/* Because we are still using the old semantic table, provide compat
+   macro's that store the instruction where the old simops expects
+   it. */
+
+#if 0
+OP[0] = inst & 0x1f;
+OP[1] = (inst >> 11) & 0x1f;
+OP[2] = (inst >> 16) & 0xffff;
+OP[3] = inst;
+#endif
+
+#define COMPAT_1(CALL) \
+PC = cia; \
+OP[0] = instruction_0 & 0x1f; \
+OP[1] = (instruction_0 >> 11) & 0x1f; \
+OP[2] = 0; \
+OP[3] = instruction_0 ; \
+PC += (CALL); \
+nia = PC
+
+#define COMPAT_2(CALL) \
+PC = cia; \
+OP[0] = instruction_0 & 0x1f; \
+OP[1] = (instruction_0 >> 11) & 0x1f; \
+OP[2] = instruction_1; \
+OP[3] = (instruction_1 << 16) | instruction_0; \
+PC += (CALL); \
+nia = PC
+
+
+#if 0
 extern struct simops Simops[];
+#endif
 
 #define State    (STATE_CPU (simulator, 0)->reg)
 #define PC	(State.pc)
@@ -111,40 +144,30 @@ extern struct simops Simops[];
 /* sign-extend a 5-bit number */
 #define SEXT5(x)	((((x)&0x1f)^(~0xf))+0x10)	
 
-/* sign-extend an 8-bit number */
-#define SEXT8(x)	((((x)&0xff)^(~0x7f))+0x80)
-
 /* sign-extend a 9-bit number */
 #define SEXT9(x)	((((x)&0x1ff)^(~0xff))+0x100)
 
-/* sign-extend a 16-bit number */
-#define SEXT16(x)	((((x)&0xffff)^(~0x7fff))+0x8000)
-
 /* sign-extend a 22-bit number */
 #define SEXT22(x)	((((x)&0x3fffff)^(~0x1fffff))+0x200000)
 
-/* sign-extend a 32-bit number */
-#define SEXT32(x)	((((x)&0xffffffffLL)^(~0x7fffffffLL))+0x80000000LL)
-
 /* sign extend a 40 bit number */
-#define SEXT40(x)	((((x)&0xffffffffffLL)^(~0x7fffffffffLL))+0x8000000000LL)
+#define SEXT40(x)	((((x) & UNSIGNED64 (0xffffffffff)) \
+			  ^ (~UNSIGNED64 (0x7fffffffff))) \
+			 + UNSIGNED64 (0x8000000000))
 
 /* sign extend a 44 bit number */
-#define SEXT44(x)	((((x)&0xfffffffffffLL)^(~0x7ffffffffffLL))+0x80000000000LL)
+#define SEXT44(x)	((((x) & UNSIGNED64 (0xfffffffffff)) \
+			  ^ (~ UNSIGNED64 (0x7ffffffffff))) \
+			 + UNSIGNED64 (0x80000000000))
 
 /* sign extend a 60 bit number */
-#define SEXT60(x)	((((x)&0xfffffffffffffffLL)^(~0x7ffffffffffffffLL))+0x800000000000000LL)
+#define SEXT60(x)	((((x) & UNSIGNED64 (0xfffffffffffffff)) \
+			  ^ (~ UNSIGNED64 (0x7ffffffffffffff))) \
+			 + UNSIGNED64 (0x800000000000000))
 
 /* No sign extension */
 #define NOP(x)		(x)
 
-#if 0
-#define MAX32	0x7fffffffLL
-#define MIN32	0xff80000000LL
-#define MASK32	0xffffffffLL
-#define MASK40	0xffffffffffLL
-#endif
-
 #define INC_ADDR(x,i)	x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
 
 #define RLW(x) load_mem (x, 4)
@@ -166,7 +189,7 @@ sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
 
 #define IMEM_IMMED(EA,N) \
 sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
-			 PC, sim_core_execute_map, (EA) + (N) * 4)
+			 PC, sim_core_execute_map, (EA) + (N) * 2)
 
 #define load_mem(ADDR,LEN) \
 sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \
@@ -175,3 +198,5 @@ sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \
 #define store_mem(ADDR,LEN,DATA) \
 sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
 				PC, sim_core_write_map, (ADDR), (DATA))
+
+#include "simops.h"
diff --git a/sim/v850/simops.c b/sim/v850/simops.c
index 4926910..463e4a3 100644
--- a/sim/v850/simops.c
+++ b/sim/v850/simops.c
@@ -15,6 +15,18 @@
 #include <unistd.h>
 #endif
 
+#ifdef HAVE_STRING_H
+#include <string.h>
+#else
+#ifdef HAVE_STRINGS_H
+#include <strings.h>
+#endif
+#endif
+
+
+
+
+
  /* FIXME - should be including a version of syscall.h that does not
     pollute the name space */
 #include "../../libgloss/v850/sys/syscall.h"
@@ -81,11 +93,6 @@ static int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 2
 #ifdef DEBUG
 static void trace_input PARAMS ((char *name, enum op_types type, int size));
 static void trace_output PARAMS ((enum op_types result));
-static int init_text_p = 0;
-static asection *text;
-static bfd_vma text_start;
-static bfd_vma text_end;
-extern bfd *prog_bfd;
 
 #ifndef SIZE_INSTRUCTION
 #define SIZE_INSTRUCTION 6
@@ -115,34 +122,26 @@ trace_input (name, type, size)
   uint32 values[3];
   int num_values, i;
   char *cond;
-  asection *s;
   const char *filename;
   const char *functionname;
   unsigned int linenumber;
 
-  if ((v850_debug & DEBUG_TRACE) == 0)
+  if (!TRACE_INSN_P (STATE_CPU (simulator, 0)))
     return;
 
   buf[0] = '\0';
-  if (!init_text_p)
-    {
-      init_text_p = 1;
-      for (s = prog_bfd->sections; s; s = s->next)
-	if (strcmp (bfd_get_section_name (prog_bfd, s), ".text") == 0)
-	  {
-	    text = s;
-	    text_start = bfd_get_section_vma (prog_bfd, s);
-	    text_end = text_start + bfd_section_size (prog_bfd, s);
-	    break;
-	  }
-    }
 
-  if (text && PC >= text_start && PC < text_end)
+  if (STATE_TEXT_SECTION (simulator)
+      && PC >= STATE_TEXT_START (simulator)
+      && PC < STATE_TEXT_END (simulator))
     {
       filename = (const char *)0;
       functionname = (const char *)0;
       linenumber = 0;
-      if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, PC - text_start,
+      if (bfd_find_nearest_line (STATE_PROG_BFD (simulator),
+				 STATE_TEXT_SECTION (simulator),
+				 (struct symbol_cache_entry **)0,
+				 PC - STATE_TEXT_START (simulator),
 				 &filename, &functionname, &linenumber))
 	{
 	  p = buf;
@@ -169,10 +168,10 @@ trace_input (name, type, size)
 	}
     }
 
-  (*v850_callback->printf_filtered) (v850_callback, "0x%.8x: %-*.*s %-*s",
-				     (unsigned)PC,
-				     SIZE_LOCATION, SIZE_LOCATION, buf,
-				     SIZE_INSTRUCTION, name);
+  sim_io_printf (simulator, "0x%.8x: %-*.*s %-*s",
+		 (unsigned)PC,
+		 SIZE_LOCATION, SIZE_LOCATION, buf,
+		 SIZE_INSTRUCTION, name);
 
   switch (type)
     {
@@ -183,59 +182,59 @@ trace_input (name, type, size)
       break;
 
     case OP_TRAP:
-      sprintf (buf, "%d", OP[0]);
+      sprintf (buf, "%ld", OP[0]);
       break;
 
     case OP_REG:
-      sprintf (buf, "r%d", OP[0]);
+      sprintf (buf, "r%ld", OP[0]);
       break;
 
     case OP_REG_REG:
     case OP_REG_REG_CMP:
     case OP_REG_REG_MOVE:
-      sprintf (buf, "r%d,r%d", OP[0], OP[1]);
+      sprintf (buf, "r%ld,r%ld", OP[0], OP[1]);
       break;
 
     case OP_IMM_REG:
     case OP_IMM_REG_CMP:
     case OP_IMM_REG_MOVE:
-      sprintf (buf, "%d,r%d", OP[0], OP[1]);
+      sprintf (buf, "%ld,r%ld", OP[0], OP[1]);
       break;
 
     case OP_COND_BR:
-      sprintf (buf, "%d", SEXT9 (OP[0]));
+      sprintf (buf, "%ld", SEXT9 (OP[0]));
       break;
 
     case OP_LOAD16:
-      sprintf (buf, "%d[r30],r%d", OP[1] * size, OP[0]);
+      sprintf (buf, "%ld[r30],r%ld", OP[1] * size, OP[0]);
       break;
 
     case OP_STORE16:
-      sprintf (buf, "r%d,%d[r30]", OP[0], OP[1] * size);
+      sprintf (buf, "r%ld,%ld[r30]", OP[0], OP[1] * size);
       break;
 
     case OP_LOAD32:
-      sprintf (buf, "%d[r%d],r%d", SEXT16 (OP[2]) & ~0x1, OP[0], OP[1]);
+      sprintf (buf, "%ld[r%ld],r%ld", EXTEND16 (OP[2]) & ~0x1, OP[0], OP[1]);
       break;
 
     case OP_STORE32:
-      sprintf (buf, "r%d,%d[r%d]", OP[1], SEXT16 (OP[2] & ~0x1), OP[0]);
+      sprintf (buf, "r%ld,%ld[r%ld]", OP[1], EXTEND16 (OP[2] & ~0x1), OP[0]);
       break;
 
     case OP_JUMP:
-      sprintf (buf, "%d,r%d", SEXT22 (OP[0]), OP[1]);
+      sprintf (buf, "%ld,r%ld", SEXT22 (OP[0]), OP[1]);
       break;
 
     case OP_IMM_REG_REG:
-      sprintf (buf, "%d,r%d,r%d", SEXT16 (OP[0]), OP[1], OP[2]);
+      sprintf (buf, "%ld,r%ld,r%ld", EXTEND16 (OP[0]), OP[1], OP[2]);
       break;
 
     case OP_UIMM_REG_REG:
-      sprintf (buf, "%d,r%d,r%d", OP[0] & 0xffff, OP[1], OP[2]);
+      sprintf (buf, "%ld,r%ld,r%ld", OP[0] & 0xffff, OP[1], OP[2]);
       break;
 
     case OP_BIT:
-      sprintf (buf, "%d,%d[r%d]", OP[1] & 0x7, SEXT16 (OP[2]), OP[0]);
+      sprintf (buf, "%ld,%ld[r%ld]", OP[1] & 0x7, EXTEND16 (OP[2]), OP[0]);
       break;
 
     case OP_EX1:
@@ -260,7 +259,7 @@ trace_input (name, type, size)
 	case 0xf: cond = "gt";	break;
 	}
 
-      sprintf (buf, "%s,r%d", cond, OP[1]);
+      sprintf (buf, "%s,r%ld", cond, OP[1]);
       break;
 
     case OP_EX2:
@@ -269,19 +268,19 @@ trace_input (name, type, size)
 
     case OP_LDSR:
     case OP_STSR:
-      sprintf (buf, "r%d,s%d", OP[0], OP[1]);
+      sprintf (buf, "r%ld,s%ld", OP[0], OP[1]);
       break;
 
     case OP_PUSHPOP1:
       for (i = 0; i < 12; i++)
 	if (OP[3] & (1 << type1_regs[i]))
-	  strcat (buf, "r%d ", i + 20);
+	  sprintf (strchr (buf, 0), "r%d ", i + 20);
       break;
 
     case OP_PUSHPOP2:
       for (i = 0; i < 16; i++)
 	if (OP[3] & (1 << type2_regs[i]))
-	  strcat (buf, "r%d ", i + 16);
+	  sprintf (strchr (buf, 0), "r%d ", i + 16);
       if (OP[3] & (1 << 19))
 	strcat (buf, "F/EIPC, F/EIPSW " );
       break;
@@ -289,7 +288,7 @@ trace_input (name, type, size)
     case OP_PUSHPOP3:
       for (i = 0; i < 15; i++)
 	if (OP[3] & (1 << type3_regs[i]))
-	  strcat (buf, "r%d ", i + 1);
+	  sprintf (strchr (buf, 0), "r%d ", i + 1);
       if (OP[3] & (1 << 3))
 	strcat (buf, "PSW " );
       if (OP[3] & (1 << 19))
@@ -297,17 +296,17 @@ trace_input (name, type, size)
       break;
 
     case OP_BIT_CHANGE:
-      sprintf (buf, "r%d, [r%d]", OP[1], OP[0] );
+      sprintf (buf, "r%ld, [r%ld]", OP[1], OP[0] );
       break;
     }
 
-  if ((v850_debug & DEBUG_VALUES) == 0)
+  if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
     {
-      (*v850_callback->printf_filtered) (v850_callback, "%s\n", buf);
+      sim_io_printf (simulator, "%s\n", buf);
     }
   else
     {
-      (*v850_callback->printf_filtered) (v850_callback, "%-*s", SIZE_OPERANDS, buf);
+      sim_io_printf (simulator, "%-*s", SIZE_OPERANDS, buf);
       switch (type)
 	{
 	default:
@@ -364,14 +363,14 @@ trace_input (name, type, size)
 	  break;
 
 	case OP_LOAD32:
-	  values[0] = SEXT16 (OP[2]);
+	  values[0] = EXTEND16 (OP[2]);
 	  values[1] = State.regs[OP[0]];
 	  num_values = 2;
 	  break;
 
 	case OP_STORE32:
 	  values[0] = State.regs[OP[1]];
-	  values[1] = SEXT16 (OP[2]);
+	  values[1] = EXTEND16 (OP[2]);
 	  values[2] = State.regs[OP[0]];
 	  num_values = 3;
 	  break;
@@ -383,7 +382,7 @@ trace_input (name, type, size)
 	  break;
 
 	case OP_IMM_REG_REG:
-	  values[0] = SEXT16 (OP[0]) << size;
+	  values[0] = EXTEND16 (OP[0]) << size;
 	  values[1] = State.regs[OP[1]];
 	  num_values = 2;
 	  break;
@@ -418,10 +417,10 @@ trace_input (name, type, size)
 	}
 
       for (i = 0; i < num_values; i++)
-	(*v850_callback->printf_filtered) (v850_callback, "%*s0x%.8lx", SIZE_VALUES - 10, "", values[i]);
+	sim_io_printf (simulator, "%*s0x%.8lx", SIZE_VALUES - 10, "", values[i]);
 
       while (i++ < 3)
-	(*v850_callback->printf_filtered) (v850_callback, "%*s", SIZE_VALUES, "");
+	sim_io_printf (simulator, "%*s", SIZE_VALUES, "");
     }
 }
 
@@ -429,7 +428,8 @@ static void
 trace_output (result)
      enum op_types result;
 {
-  if ((v850_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
+  if (TRACE_INSN_P (STATE_CPU (simulator, 0))
+      && TRACE_ALU_P (STATE_CPU (simulator, 0)))
     {
       switch (result)
 	{
@@ -449,7 +449,7 @@ trace_output (result)
 
 	case OP_LOAD16:
 	case OP_STSR:
-	  (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
+	  sim_io_printf (simulator, " :: 0x%.8lx",
 					     (unsigned long)State.regs[OP[0]]);
 	  break;
 
@@ -459,29 +459,29 @@ trace_output (result)
 	case OP_IMM_REG_MOVE:
 	case OP_LOAD32:
 	case OP_EX1:
-	  (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
+	  sim_io_printf (simulator, " :: 0x%.8lx",
 					     (unsigned long)State.regs[OP[1]]);
 	  break;
 
 	case OP_IMM_REG_REG:
 	case OP_UIMM_REG_REG:
-	  (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
+	  sim_io_printf (simulator, " :: 0x%.8lx",
 					     (unsigned long)State.regs[OP[2]]);
 	  break;
 
 	case OP_JUMP:
 	  if (OP[1] != 0)
-	    (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
+	    sim_io_printf (simulator, " :: 0x%.8lx",
 					       (unsigned long)State.regs[OP[1]]);
 	  break;
 
 	case OP_LDSR:
-	  (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
+	  sim_io_printf (simulator, " :: 0x%.8lx",
 					     (unsigned long)State.sregs[OP[1]]);
 	  break;
 	}
 
-      (*v850_callback->printf_filtered) (v850_callback, "\n");
+      sim_io_printf (simulator, "\n");
     }
 }
 
@@ -657,7 +657,7 @@ OP_300 ()
 /* end-sanitize-v850eq */
   trace_input ("sld.b", OP_LOAD16, 1);
   
-  State.regs[ OP[1] ] = SEXT8 (result);
+  State.regs[ OP[1] ] = EXTEND8 (result);
 /* start-sanitize-v850eq */
 #endif
 /* end-sanitize-v850eq */
@@ -684,7 +684,7 @@ OP_400 ()
 /* end-sanitize-v850eq */
   trace_input ("sld.h", OP_LOAD16, 2);
   
-  State.regs[ OP[1] ] = SEXT16 (result);
+  State.regs[ OP[1] ] = EXTEND16 (result);
 /* start-sanitize-v850eq */
 #endif
 /* end-sanitize-v850eq */
@@ -754,9 +754,9 @@ OP_700 ()
 
   trace_input ("ld.b", OP_LOAD32, 1);
 
-  adr = State.regs[ OP[0] ] + SEXT16 (OP[2]);
+  adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
 
-  State.regs[ OP[1] ] = SEXT8 (load_mem (adr, 1));
+  State.regs[ OP[1] ] = EXTEND8 (load_mem (adr, 1));
   
   trace_output (OP_LOAD32);
 
@@ -771,10 +771,10 @@ OP_720 ()
 
   trace_input ("ld.h", OP_LOAD32, 2);
 
-  adr = State.regs[ OP[0] ] + SEXT16 (OP[2]);
+  adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
   adr &= ~0x1;
   
-  State.regs[ OP[1] ] = SEXT16 (load_mem (adr, 2));
+  State.regs[ OP[1] ] = EXTEND16 (load_mem (adr, 2));
   
   trace_output (OP_LOAD32);
 
@@ -789,7 +789,7 @@ OP_10720 ()
 
   trace_input ("ld.w", OP_LOAD32, 4);
 
-  adr = State.regs[ OP[0] ] + SEXT16 (OP[2] & ~1);
+  adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
   adr &= ~0x3;
   
   State.regs[ OP[1] ] = load_mem (adr, 4);
@@ -805,7 +805,7 @@ OP_740 ()
 {
   trace_input ("st.b", OP_STORE32, 1);
 
-  store_mem (State.regs[ OP[0] ] + SEXT16 (OP[2]), 1, State.regs[ OP[1] ]);
+  store_mem (State.regs[ OP[0] ] + EXTEND16 (OP[2]), 1, State.regs[ OP[1] ]);
   
   trace_output (OP_STORE32);
 
@@ -820,7 +820,7 @@ OP_760 ()
   
   trace_input ("st.h", OP_STORE32, 2);
 
-  adr = State.regs[ OP[0] ] + SEXT16 (OP[2]);
+  adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
   adr &= ~1;
   
   store_mem (adr, 2, State.regs[ OP[1] ]);
@@ -838,7 +838,7 @@ OP_10760 ()
   
   trace_input ("st.w", OP_STORE32, 4);
 
-  adr = State.regs[ OP[0] ] + SEXT16 (OP[2] & ~1);
+  adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
   adr &= ~3;
   
   store_mem (adr, 4, State.regs[ OP[1] ]);
@@ -998,7 +998,7 @@ OP_60 ()
 #ifdef ARCH_v850eq
       trace_input ("sld.b", OP_LOAD16, 1);
       
-      State.regs[ OP[1] ] = SEXT8 (result);
+      State.regs[ OP[1] ] = EXTEND8 (result);
 #else
 /* end-sanitize-v850eq */
       trace_input ("sld.bu", OP_LOAD16, 1);
@@ -1103,7 +1103,7 @@ OP_600 ()
 
   /* Compute the result.  */
 
-  op0 = SEXT16 (OP[2]);
+  op0 = EXTEND16 (OP[2]);
   op1 = State.regs[ OP[0] ];
   result = op0 + op1;
   
@@ -1192,7 +1192,7 @@ OP_E0 ()
     {
       trace_input ("sxh", OP_REG, 0);
       
-      State.regs[ OP[0] ] = SEXT16 (State.regs[ OP[0] ]);
+      State.regs[ OP[0] ] = EXTEND16 (State.regs[ OP[0] ]);
 
       trace_output (OP_REG);
     }
@@ -1201,7 +1201,7 @@ OP_E0 ()
     {
       trace_input ("mulh", OP_REG_REG, 0);
       
-      State.regs[ OP[1] ] = (SEXT16 (State.regs[ OP[1] ]) * SEXT16 (State.regs[ OP[0] ]));
+      State.regs[ OP[1] ] = (EXTEND16 (State.regs[ OP[1] ]) * EXTEND16 (State.regs[ OP[0] ]));
       
       trace_output (OP_REG_REG);
     }
@@ -1215,7 +1215,7 @@ OP_2E0 ()
 {
   trace_input ("mulh", OP_IMM_REG, 0);
   
-  State.regs[ OP[1] ] = SEXT16 (State.regs[ OP[1] ]) * SEXT5 (OP[0]);
+  State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[1] ]) * SEXT5 (OP[0]);
   
   trace_output (OP_IMM_REG);
 
@@ -1233,7 +1233,7 @@ OP_6E0 ()
     {
       trace_input ("mulhi", OP_IMM_REG_REG, 0);
   
-      State.regs[ OP[1] ] = SEXT16 (State.regs[ OP[0] ]) * SEXT16 (OP[2]);
+      State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[0] ]) * EXTEND16 (OP[2]);
       
       trace_output (OP_IMM_REG_REG);
     }
@@ -1254,7 +1254,7 @@ OP_40 ()
       trace_input ("switch", OP_REG, 0);
       
       adr      = State.pc + 2 + (State.regs[ OP[0] ] << 1);
-      State.pc = State.pc + 2 + (SEXT16 (load_mem (adr, 2)) << 1);
+      State.pc = State.pc + 2 + (EXTEND16 (load_mem (adr, 2)) << 1);
 
       trace_output (OP_REG);
     }
@@ -1267,7 +1267,7 @@ OP_40 ()
       trace_input ("divh", OP_REG_REG, 0);
 
       /* Compute the result.  */
-      temp = SEXT16 (State.regs[ OP[0] ]);
+      temp = EXTEND16 (State.regs[ OP[0] ]);
       op0 = temp;
       op1 = State.regs[OP[1]];
       
@@ -1475,7 +1475,7 @@ OP_A0 ()
     {
       trace_input ("sxb", OP_REG, 0);
 
-      State.regs[ OP[0] ] = SEXT8 (State.regs[ OP[0] ]);
+      State.regs[ OP[0] ] = EXTEND8 (State.regs[ OP[0] ]);
 
       trace_output (OP_REG);
     }
@@ -1527,7 +1527,7 @@ OP_660 ()
   trace_input ("satsubi", OP_IMM_REG, 0);
 
   /* Compute the result.  */
-  temp = SEXT16 (OP[2]);
+  temp = EXTEND16 (OP[2]);
   op0 = temp;
   op1 = State.regs[ OP[0] ];
   result = op1 - op0;
@@ -1693,11 +1693,11 @@ OP_620 ()
 /* start-sanitize-v850e */
   if (OP[1] == 0)
     {
-      trace_input ("mov", OP_IMM32_REG, 4);
+      trace_input ("mov", OP_IMM_REG, 4);
 
       State.regs[ OP[0] ] = load_mem (PC + 2, 4);
       
-      trace_output (OP_IMM32_REG);
+      trace_output (OP_IMM_REG);
 
       return 6;
     }
@@ -1706,7 +1706,7 @@ OP_620 ()
     {
       trace_input ("movea", OP_IMM_REG_REG, 0);
   
-      State.regs[ OP[1] ] = State.regs[ OP[0] ] + SEXT16 (OP[2]);
+      State.regs[ OP[1] ] = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
   
       trace_output (OP_IMM_REG_REG);
 
@@ -2099,7 +2099,7 @@ OP_7C0 ()
   trace_input ("set1", OP_BIT, 0);
   op0 = State.regs[ OP[0] ];
   op1 = OP[1] & 0x7;
-  temp = SEXT16 (OP[2]);
+  temp = EXTEND16 (OP[2]);
   op2 = temp;
   temp = load_mem (op0 + op2, 1);
   PSW &= ~PSW_Z;
@@ -2122,7 +2122,7 @@ OP_47C0 ()
   trace_input ("not1", OP_BIT, 0);
   op0 = State.regs[ OP[0] ];
   op1 = OP[1] & 0x7;
-  temp = SEXT16 (OP[2]);
+  temp = EXTEND16 (OP[2]);
   op2 = temp;
   temp = load_mem (op0 + op2, 1);
   PSW &= ~PSW_Z;
@@ -2145,7 +2145,7 @@ OP_87C0 ()
   trace_input ("clr1", OP_BIT, 0);
   op0 = State.regs[ OP[0] ];
   op1 = OP[1] & 0x7;
-  temp = SEXT16 (OP[2]);
+  temp = EXTEND16 (OP[2]);
   op2 = temp;
   temp = load_mem (op0 + op2, 1);
   PSW &= ~PSW_Z;
@@ -2168,7 +2168,7 @@ OP_C7C0 ()
   trace_input ("tst1", OP_BIT, 0);
   op0 = State.regs[ OP[0] ];
   op1 = OP[1] & 0x7;
-  temp = SEXT16 (OP[2]);
+  temp = EXTEND16 (OP[2]);
   op2 = temp;
   temp = load_mem (op0 + op2, 1);
   PSW &= ~PSW_Z;
@@ -2183,8 +2183,9 @@ OP_C7C0 ()
 int
 OP_FFFF ()
 {
-  State.exception = SIGTRAP;
-  return  -4;
+  sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
+		   sim_stopped, SIGTRAP);
+  return 0;
 }
 
 /* di */
@@ -2215,10 +2216,10 @@ OP_12007E0 ()
 {
   trace_input ("halt", OP_NONE, 0);
   /* FIXME this should put processor into a mode where NMI still handled */
-  State.exception = SIGQUIT;
   trace_output (OP_NONE);
-
-  return 4;
+  sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
+		   sim_stopped, SIGTRAP);
+  return 0;
 }
 
 /* reti */
@@ -2394,11 +2395,17 @@ OP_10007E0 ()
 #ifdef SYS_exit
 	case SYS_exit:
 	  if ((PARM1 & 0xffff0000) == 0xdead0000 && (PARM1 & 0xffff) != 0)
-	    State.exception = PARM1 & 0xffff;	/* get signal encoded by kill */
+	    /* get signal encoded by kill */
+	    sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
+			     sim_signalled, PARM1 & 0xffff);
 	  else if (PARM1 == 0xdead)
-	    State.exception = SIGABRT;		/* old libraries */
+	    /* old libraries */
+	    sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
+			     sim_exited, SIGABRT);
 	  else
-	    State.exception = SIG_V850_EXIT;	/* PARM1 has exit status encoded */
+	    /* PARM1 has exit status */
+	    sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
+			     sim_exited, PARM1);
 	  break;
 #endif
 
@@ -2568,7 +2575,7 @@ OP_E607E0 (void)
 {
   int temp;
 
-  trace_input ("tst1", OP_BIT_LOAD, 1);
+  trace_input ("tst1", OP_BIT, 1);
 
   temp = load_mem (State.regs[ OP[0] ], 1);
   
@@ -2576,7 +2583,7 @@ OP_E607E0 (void)
   if ((temp & (1 << State.regs[ OP[1] & 0x7 ])) == 0)
     PSW |= PSW_Z;
   
-  trace_output (OP_BIT_LOAD);
+  trace_output (OP_BIT);
 
   return 4;
 }
@@ -2946,7 +2953,7 @@ OP_18007E0 (void)
 
   imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
 
-  divide_by   = SEXT16 (State.regs[ OP[0] ]);
+  divide_by   = EXTEND16 (State.regs[ OP[0] ]);
   divide_this = State.regs[ OP[1] ] << imm5;
 
   divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
@@ -3192,7 +3199,7 @@ OP_28007E0 (void)
       /* Compute the result.  */
 
       divide_by  = State.regs[ OP[0] ];
-      divide_this = SEXT16 (State.regs[ OP[1] ]);
+      divide_this = EXTEND16 (State.regs[ OP[1] ]);
 
       if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
 	{
@@ -3222,7 +3229,7 @@ OP_28007E0 (void)
 
       imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
 
-      divide_by   = SEXT16 (State.regs[ OP[0] ]);
+      divide_by   = EXTEND16 (State.regs[ OP[0] ]);
       divide_this = State.regs[ OP[1] ];
 
       divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
@@ -3428,7 +3435,7 @@ OP_107E0 (void)
 
       trace_input ("ld.hu", OP_LOAD32, 2);
 
-      adr = State.regs[ OP[0] ] + SEXT16 (OP[2] & ~1);
+      adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
       adr &= ~0x1;
       
       State.regs[ OP[1] ] = load_mem (adr, 2);
@@ -3469,7 +3476,7 @@ OP_10780 (void)
       trace_input ("ld.bu", OP_LOAD32, 1);
 
       adr = (State.regs[ OP[0] ]
-	     + (SEXT16 (OP[2] & ~1) | ((OP[3] >> 5) & 1)));
+	     + (EXTEND16 (OP[2] & ~1) | ((OP[3] >> 5) & 1)));
       
       State.regs[ OP[1] ] = load_mem (adr, 1);
   
@@ -3547,7 +3554,7 @@ OP_B0780 (void)
   
   SP -= (OP[3] & 0x3e) << 1;
 
-  EP = SEXT16 (load_mem (PC + 4, 2));
+  EP = EXTEND16 (load_mem (PC + 4, 2));
   
   trace_output (OP_PUSHPOP1);
 
@@ -3591,7 +3598,7 @@ OP_70 (void)
 #ifdef ARCH_v850eq
   trace_input ("sld.h", OP_LOAD16, 2);
   
-  State.regs[ OP[1] ] = SEXT16 (result);
+  State.regs[ OP[1] ] = EXTEND16 (result);
 #else
 /* end-sanitize-v850eq */
   trace_input ("sld.hu", OP_LOAD16, 2);
diff --git a/sim/v850/v850-dc b/sim/v850/v850-dc
new file mode 100644
index 0000000..91b0898
--- /dev/null
+++ b/sim/v850/v850-dc
@@ -0,0 +1,32 @@
+# most instructions
+# ------ options ------ : Fst : Lst : ff : fl : fe : word : --- fmt --- : model ...
+# { : mask : value : word }
+
+# Top level - create a very big switch statement.
+
+  padded-switch,combine :  15 :   5 :    :    :    :    0 :             :
+
+
+# for opcode 60,124
+
+  switch,combine        :   4 :   0 :    :    :    :    1 : V,VII       :
+# start-sanitize-v850e
+  switch,combine        :   4 :   0 :    :    :    :    1 : V,XIII      : v850e
+# end-sanitize-v850e
+# start-sanitize-v850eq
+  switch,combine        :   4 :   0 :    :    :    :    1 : V,XIII      : v850eq
+# end-sanitize-v850eq
+
+
+# for opcode 63, 127, 1087 et.al.
+
+  switch,combine        :   9 :   5 :    :    :    :    1 :             :
+  switch,combine        :   4 :   0 :    :    :    :    1 :             :
+
+
+# for opcode 40 et.al.
+
+  switch,combine        :   4 :   0 :    :    :    :    0 : III,IV      :
+# start-sanitize-v850eq
+  switch,combine        :   4 :   0 :    :    :    :    0 : III,IV,XIV  : v850eq
+# end-sanitize-v850eq
diff --git a/sim/v850/v850.igen b/sim/v850/v850.igen
new file mode 100644
index 0000000..f5976c7
--- /dev/null
+++ b/sim/v850/v850.igen
@@ -0,0 +1,1151 @@
+:option::insn-bit-size:16
+:option::hi-bit-nr:15
+
+
+:option::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
+# start-sanitize-v850e
+:option::format-names:XI,XII,XIII
+# end-sanitize-v850e
+# start-sanitize-v850eq
+:option::format-names:XIV,XV
+# end-sanitize-v850eq
+:option::format-names:Z
+
+
+:model::v850:v850:
+
+# start-sanitize-v850e
+:option::multi-sim:true
+:model::v850e:v850e:
+# end-sanitize-v850e
+
+# start-sanitize-v850eq
+:option::multi-sim:true
+:model::v850eq:v850eq:
+# end-sanitize-v850eq
+
+
+
+// Cache macros
+
+:cache::unsigned:reg1:RRRRR:(RRRRR)
+:cache::unsigned:reg2:rrrrr:(rrrrr)
+:cache::unsigned:reg3:wwwww:(wwwww)
+:cache::unsigned:regID:rrrrr:(rrrrr)
+
+:cache::unsigned:disp4:dddd:(dddd)
+# start-sanitize-v850e
+:cache::unsigned:disp5:dddd:(dddd << 1)
+# end-sanitize-v850e
+:cache::unsigned:disp7:ddddddd:ddddddd
+:cache::unsigned:disp8:ddddddd:(ddddddd << 1)
+:cache::unsigned:disp8:dddddd:(dddddd << 2)
+:cache::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
+:cache::unsigned:disp16:dddddddddddddddd:SEXT32 (dddddddddddddddd, 16 - 1)
+:cache::unsigned:disp16:ddddddddddddddd:SEXT32 (ddddddddddddddd << 1, 16 - 1)
+:cache::unsigned:disp22:dddddd,dddddddddddddddd:SEXT32 ((dddddd << 16) + (dddddddddddddddd << 1), 22 - 1)
+:cache::unsigned:disp22:dddddd,ddddddddddddddd:SEXT32 ((dddddd << 16) + (ddddddddddddddd << 2), 22 - 1)
+
+:cache::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
+:cache::unsigned:imm6:iiiiii:iiiiii
+:cache::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
+# start-sanitize-v850eq
+:cache::unsigned:imm5:iiii:(32 - (iiii << 1))
+# end-sanitize-v850eq
+:cache::unsigned:imm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
+:cache::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
+# start-sanitize-v850e
+:cache::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
+:cache::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
+# end-sanitize-v850e
+
+:cache::unsigned:vector:iiiii:iiiii
+
+# start-sanitize-v850e
+:cache::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
+:cache::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
+# end-sanitize-v850e
+
+:cache::unsigned:bit3:bbb:bbb
+
+
+// What do we do with an illegal instruction?
+:internal:::illegal
+{
+  abort ();
+}
+
+
+
+// Add
+
+rrrrr,001110,RRRRR:I:::add
+"add r<reg1>, r<reg2>"
+{
+  COMPAT_1 (OP_1C0 ());
+}
+
+rrrrr,010010,iiiii:II:::add
+"add <imm5>,r<reg2>"
+{
+  COMPAT_1 (OP_240 ());
+}
+
+
+
+// ADDI
+rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
+"addi <imm16>, r<reg1>, r<reg2>"
+{
+  COMPAT_2 (OP_600 ());
+}
+
+
+
+// AND
+rrrrr,001010,RRRRR:I:::and
+"and r<reg1>, r<reg2>"
+{
+  COMPAT_1 (OP_140 ());
+}
+
+
+
+// ANDI
+rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
+"andi <imm16>, r<reg1>, r<reg2>"
+{
+  COMPAT_2 (OP_6C0 ());
+}
+
+
+
+// Bcond
+// ddddd,1011,ddd,cccc:III:::Bcond
+// "b<cond> disp9"
+
+ddddd,1011,ddd,0000:III:::bv
+"bv <disp9>"
+{
+  COMPAT_1 (OP_580 ());
+}
+
+ddddd,1011,ddd,0001:III:::bl
+"bl <disp9>"
+{
+  COMPAT_1 (OP_581 ());
+}
+
+ddddd,1011,ddd,0010:III:::be
+"be <disp9>"
+{
+  COMPAT_1 (OP_582 ());
+}
+
+ddddd,1011,ddd,0011:III:::bnh
+"bnh <disp9>"
+{
+  COMPAT_1 (OP_583 ());
+}
+
+ddddd,1011,ddd,0100:III:::bn
+"bn <disp9>"
+{
+  COMPAT_1 (OP_584 ());
+}
+
+ddddd,1011,ddd,0101:III:::br
+"br <disp9>"
+{
+  COMPAT_1 (OP_585 ());
+}
+
+ddddd,1011,ddd,0110:III:::blt
+"blt <disp9>"
+{
+  COMPAT_1 (OP_586 ());
+}
+
+ddddd,1011,ddd,0111:III:::ble
+"ble <disp9>"
+{
+  COMPAT_1 (OP_587 ());
+}
+
+ddddd,1011,ddd,1000:III:::bnv
+"bnv <disp9>"
+{
+  COMPAT_1 (OP_588 ());
+}
+
+ddddd,1011,ddd,1001:III:::bnl
+"bnl <disp9>"
+{
+  COMPAT_1 (OP_589 ());
+}
+
+ddddd,1011,ddd,1010:III:::bne
+"bne <disp9>"
+{
+  COMPAT_1 (OP_58A ());
+}
+
+ddddd,1011,ddd,1011:III:::bh
+"bh <disp9>"
+{
+  COMPAT_1 (OP_58B ());
+}
+
+ddddd,1011,ddd,1100:III:::bp
+"bp <disp9>"
+{
+  COMPAT_1 (OP_58C ());
+}
+
+ddddd,1011,ddd,1101:III:::bsa
+"bsa <disp9>"
+{
+  COMPAT_1 (OP_58D ());
+}
+
+ddddd,1011,ddd,1110:III:::bge
+"bge <disp9>"
+{
+  COMPAT_1 (OP_58E ());
+}
+
+ddddd,1011,ddd,1111:III:::bgt
+"bgt <disp9>"
+{
+  COMPAT_1 (OP_58F ());
+}
+
+
+
+// start-sanitize-v850e
+// BSH
+rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
+*v850e
+"bsh r<reg2>, r<reg3>"
+{
+  COMPAT_2 (OP_34207E0 ());
+}
+
+
+
+// end-sanitize-v850e
+// start-sanitize-v850e
+// BSW
+rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
+*v850e
+"bsw r<reg2>, reg3>"
+{
+  COMPAT_2 (OP_34007E0 ());
+}
+
+
+
+// end-sanitize-v850e
+// CALLT
+0000001000,iiiiii:II:::callt
+"callt <imm6>"
+{
+  COMPAT_1 (OP_200 ());
+}
+
+
+
+// CLR1
+10,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1
+"clr1 <bit3>, <disp16>[r<reg1>]"
+{
+  COMPAT_2 (OP_87C0 ());
+}
+
+rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
+"clr1 r<reg2>, [r<reg1>]"
+{
+  COMPAT_2 (OP_E407E0 ());
+}
+
+
+
+// CTRET
+0000011111100000 + 0000000101000100:X:::ctret
+"ctret"
+{
+  COMPAT_2 (OP_14407E0 ());
+}
+
+
+
+// start-sanitize-v850e
+// CMOV
+rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
+*v850e
+"cmov <cccc>, r<reg1>, r<reg2>, r<reg3>"
+{
+  COMPAT_2 (OP_32007E0 ());
+}
+
+rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
+*v850e
+"cmov <cccc>, <imm5>, r<reg2>, r<reg3>"
+{
+  COMPAT_2 (OP_30007E0 ());
+}
+
+
+
+// end-sanitize-v850e
+// CMP
+rrrrr,001111,RRRRR:I:::cmp
+"cmp r<reg1>, r<reg2>"
+{
+  COMPAT_1 (OP_1E0 ());
+}
+
+rrrrr,010011,iiiii:II:::cmp
+"cmp <imm5>, r<reg2>"
+{
+  COMPAT_1 (OP_260 ());
+}
+
+
+
+// DI
+0000011111100000 + 0000000101100000:X:::di
+"di"
+{
+  COMPAT_2 (OP_16007E0 ());
+}
+
+
+
+// start-sanitize-v850e
+// DISPOSE
+// 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose
+// "dispose <imm5>, <list12>"
+0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
+*v850e
+"dispose <imm5>, <list12>":RRRRR == 0
+"dispose <imm5>, <list12>, [reg1]"
+{
+  COMPAT_2 (OP_640 ());
+}
+
+
+
+// end-sanitize-v850e
+// start-sanitize-v850e
+// DIV
+rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
+*v850e
+"div r<reg1>, r<reg2>, r<reg3>"
+{
+  COMPAT_2 (OP_2C007E0 ());
+}
+
+
+
+
+// end-sanitize-v850e
+// DIVH
+rrrrr!0,000010,RRRRR!0:I:::divh
+"divh r<reg1>, r<reg2>"
+{
+  COMPAT_1 (OP_40 ());
+}
+
+// start-sanitize-v850e
+rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
+*v850e
+"divh r<reg1>, r<reg2>, r<reg3>"
+{
+  COMPAT_2 (OP_28007E0 ());
+}
+
+// end-sanitize-v850e
+
+
+// start-sanitize-v850e
+// DIVHU
+rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
+*v850e
+"divhu r<reg1>, r<reg2>, r<reg3>"
+{
+  COMPAT_2 (OP_28207E0 ());
+}
+
+
+
+// end-sanitize-v850e
+// start-sanitize-v850e
+// DIVU
+rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
+*v850e
+"divu r<reg1>, r<reg2>, r<reg3>"
+{
+  COMPAT_2 (OP_2C207E0 ());
+}
+
+
+
+// end-sanitize-v850e
+// EI
+1000011111100000 + 0000000101100000:X:::ei
+"ei"
+{
+  COMPAT_2 (OP_16087E0 ());
+}
+
+
+
+// HALT
+0000011111100000 + 0000000100100000:X:::halt
+"halt"
+{
+  COMPAT_2 (OP_12007E0 ());
+}
+
+
+
+// HSW
+// start-sanitize-v850e
+rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
+*v850e
+"hsw r<reg2>, r<reg3>"
+{
+  COMPAT_2 (OP_34407E0 ());
+}
+
+
+
+// end-sanitize-v850e
+// JARL
+rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
+"jarl <disp22>, r<reg2>"
+{
+  COMPAT_2 (OP_780 ());
+}
+
+
+
+// JMP
+00000000011,RRRRR:I:::jmp
+"jmp [r<reg1>]"
+{
+  COMPAT_1 (OP_60 ());
+}
+
+
+
+// JR
+0000011110,dddddd + ddddddddddddddd,0:V:::jr
+"jr <disp22>"
+{
+  COMPAT_2 (OP_780 ());
+}
+
+
+
+// LD
+rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
+"ld.b <disp16>[r<reg1>, r<reg2>"
+{
+  COMPAT_2 (OP_700 ());
+}
+
+rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
+"ld.h <disp16>[r<reg1>], r<reg2>"
+{
+  COMPAT_2 (OP_720 ());
+}
+
+rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
+"ld.w <disp16>[r<reg1>], r<reg2>"
+{
+  COMPAT_2 (OP_10720 ());
+}
+
+rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
+"ld.bu <disp16>[r<reg1>], r<reg2>"
+{
+  COMPAT_2 (OP_10780 ());
+}
+
+rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
+"ld.hu <disp16>[r<reg1>], r<reg2>"
+{
+  COMPAT_2 (OP_107E0 ());
+}
+
+
+
+// LDSR
+//rrrrr,111111,RRRRR + 0000000000100000:IX:::ldsr
+//"ldsr r<reg2>, r<regID>"
+//{
+//  COMPAT_2 (OP_2007E0 ());
+//}
+rrrrr,111111,RRRRR + 0000000000100000:IX:::ldsr
+"ldsr r<reg1>, r<regID>"
+{
+  COMPAT_2 (OP_2007E0 ());
+}
+
+
+
+// MOV
+rrrrr!0,000000,RRRRR:I:::mov
+"mov r<reg1>, r<reg2>"
+{
+  COMPAT_1 (OP_0 ());
+}
+
+rrrrr!0,010000,iiiii:II:::mov
+"mov <imm5>, r<reg2>"
+{
+  COMPAT_1 (OP_200 ());
+}
+
+00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
+"mov <imm32>, r<reg1>"
+{
+  COMPAT_2 (OP_620 ());
+}
+
+
+
+// MOVEA
+rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
+"movea <imm16>, r<reg1>, r<reg2>"
+{
+  COMPAT_2 (OP_620 ());
+}
+
+
+
+// MOVHI
+rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
+"movhi <imm16>, r<reg1>, r<reg2>"
+{
+  COMPAT_2 (OP_640 ());
+}
+
+
+
+// start-sanitize-v850e
+// MUL
+rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
+*v850e
+"mul r<reg1>, r<reg2>, r<reg3>"
+{
+  COMPAT_2 (OP_22007E0 ());
+}
+
+rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
+*v850e
+"mul <imm9>, r<reg2>, r<reg3>"
+{
+  COMPAT_2 (OP_24007E0 ());
+}
+
+
+
+// end-sanitize-v850e
+// MULH
+rrrrr!0,000111,RRRRR:I:::mulh
+"mulh r<reg1>, r<reg2>"
+{
+  COMPAT_1 (OP_E0 ());
+}
+
+rrrrr!0,010111,iiiii:II:::mulh
+"mulh <imm5>, r<reg2>"
+{
+  COMPAT_1 (OP_2E0 ());
+}
+
+
+
+// MULHI
+rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
+"mulhi <imm16>, r<reg1>, r<reg2>"
+{
+  COMPAT_2 (OP_6E0 ());
+}
+
+
+
+// start-sanitize-v850e
+// MULU
+rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
+*v850e
+"mulu r<reg1>, r<reg2>, r<reg3>"
+{
+  COMPAT_2 (OP_22207E0 ());
+}
+
+rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
+*v850e
+"mulu <imm9>, r<reg2>, r<reg3>"
+{
+  COMPAT_2 (OP_24207E0 ());
+}
+
+
+
+// end-sanitize-v850e
+// NOP
+0000000000000000:I:::nop
+"nop"
+{
+  COMPAT_1 (OP_0 ());
+}
+
+
+
+// NOT
+rrrrr,000001,RRRRR:I:::not
+"not r<reg1>, r<reg2>"
+{
+  COMPAT_1 (OP_20 ());
+}
+
+
+
+// NOT1
+01,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1
+"not1 <bit3>, <disp16>[r<reg1>]"
+{
+  COMPAT_2 (OP_47C0 ());
+}
+
+rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
+"not1 r<reg2>, r<reg1>"
+{
+  COMPAT_2 (OP_E207E0 ());
+}
+
+
+
+// OR
+rrrrr,001000,RRRRR:I:::or
+"or r<reg1>, r<reg2>"
+{
+  COMPAT_1 (OP_100 ());
+}
+
+
+
+// ORI 
+rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
+"ori <imm16>, r<reg1>, r<reg2>"
+{
+  COMPAT_2 (OP_680 ());
+}
+
+
+
+// start-sanitize-v850e
+// PREPARE
+0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
+*v850e
+"prepare <list12>, <imm5>"
+{
+  COMPAT_2 (OP_10780 ());
+}
+
+0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
+*v850e
+"prepare <list12>, <imm5>, sp"
+{
+  COMPAT_2 (OP_30780 ());
+}
+
+0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
+*v850e
+"prepare <list12>, <imm5>, <uimm16>"
+{
+  COMPAT_2 (OP_B0780 ());
+}
+
+0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
+*v850e
+"prepare <list12>, <imm5>, <uimm16>"
+{
+  COMPAT_2 (OP_130780 ());
+}
+
+0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
+*v850e
+"prepare <list12>, <imm5>, <uimm32>"
+{
+  COMPAT_2 (OP_1B0780 ());
+}
+
+
+
+// end-sanitize-v850e
+// RETI
+0000011111100000 + 0000000101000000:X:::reti
+"reti"
+{
+  COMPAT_2 (OP_14007E0 ());
+}
+
+
+
+// SAR
+rrrrr,111111,RRRRR + 0000000010100000:IX:::sar
+"sar r<reg1>, r<reg2>"
+{
+  COMPAT_2 (OP_A007E0 ());
+}
+
+rrrrr,010101,iiiii:II:::sar
+"sar <imm5>, r<reg2>"
+{
+  COMPAT_1 (OP_2A0 ());
+}
+
+
+
+// SASF
+rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
+"sasf <cccc>, r<reg2>"
+{
+  COMPAT_2 (OP_20007E0 ());
+}
+
+
+
+
+// SATADD
+rrrrr!0,000110,RRRRR:I:::satadd
+"satadd r<reg1>, r<reg2>"
+{
+  COMPAT_1 (OP_C0 ());
+}
+
+rrrrr!0,010001,iiiii:II:::satadd
+"satadd <imm5>, r<reg2>"
+{
+  COMPAT_1 (OP_220 ());
+}
+
+
+
+// SATSUB
+rrrrr!0,000101,RRRRR:I:::satsub
+"satsub r<reg1>, r<reg2>"
+{
+  COMPAT_1 (OP_A0 ());
+}
+
+
+
+// SATSUBI
+rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi
+"satsubi <imm16>, r<reg1>, r<reg2>"
+{
+  COMPAT_2 (OP_660 ());
+}
+
+
+
+// SATSUBR
+rrrrr!0,000100,RRRRR:I:::satsubr
+"satsubr r<reg1>, r<reg2>"
+{
+  COMPAT_1 (OP_80 ());
+}
+
+
+
+// SETF
+rrrrr,1111110,cccc + 0000000000000000:IX:::setf
+"setf <cccc>, r<reg2>"
+{
+  COMPAT_2 (OP_7E0 ());
+}
+
+
+
+// SET1
+00,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1
+"set1 <bit3>, <disp16>[r<reg1>]"
+{
+  COMPAT_2 (OP_7C0 ());
+}
+
+rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
+"set1 r<reg2>, [r<reg1>]"
+{
+  COMPAT_2 (OP_E007E0 ());
+}
+
+
+
+// SHL
+rrrrr,111111,RRRRR + 0000000011000000:IX:::shl
+"shl r<reg1>, r<reg2>"
+{
+  COMPAT_2 (OP_C007E0 ());
+}
+
+rrrrr,010110,iiiii:II:::shl
+"shl <imm5>, r<reg2>"
+{
+  COMPAT_1 (OP_2C0 ());
+}
+
+
+
+// SHR
+rrrrr,111111,RRRRR + 0000000010000000:IX:::shr
+"shr r<reg1>, r<reg2>"
+{
+  COMPAT_2 (OP_8007E0 ());
+}
+
+rrrrr,010100,iiiii:II:::shr
+"shr <imm5>, r<reg2>"
+{
+  COMPAT_1 (OP_280 ());
+}
+
+
+
+// SLD
+rrrrr,0110,ddddddd:IV:::sld.b
+"sld.b <disp7>[ep], r<reg2>"
+{
+  COMPAT_1 (OP_300 ());
+}
+
+rrrrr,1000,ddddddd:IV:::sld.h
+"sld.h <disp8>[ep], r<reg2>"
+{
+  COMPAT_1 (OP_400 ());
+}
+
+rrrrr,1010,dddddd,0:IV:::sld.w
+"sld.w <disp8>[ep], r<reg2>"
+{
+  COMPAT_1 (OP_500 ());
+}
+
+rrrrr!0,0000110,dddd:IV:::sld.bu
+"sld.bu <disp4>[ep], r<reg2>"
+{
+  COMPAT_1 (OP_60 ());
+}
+
+rrrrr!0,0000111,dddd:IV:::sld.hu
+"sld.hu <disp5>[ep], r<reg2>"
+{
+  COMPAT_1 (OP_70 ());
+}
+
+
+
+// SST
+rrrrr,0111,ddddddd:IV:::sst.b
+"sst.b r<reg2>, <disp7>[ep]"
+{
+  COMPAT_1 (OP_380 ());
+}
+
+rrrrr,1001,ddddddd:IV:::sst.h
+"sst.h r<reg2>, <disp8>[ep]"
+{
+  COMPAT_1 (OP_480 ());
+}
+
+rrrrr,1010,dddddd,1:IV:::sst.w
+"sst.w r<reg2>, <disp8>[ep]"
+{
+  COMPAT_1 (OP_501 ());
+}
+
+
+
+// ST
+rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
+"st.b r<reg2>, <disp16>[r<reg1>]"
+{
+  COMPAT_2 (OP_740 ());
+}
+
+rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
+"st.h r<reg2>, <disp16>[r<reg1>]"
+{
+  COMPAT_2 (OP_760 ());
+}
+
+rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
+"st.w r<reg2>, <disp16>[r<reg1>]"
+{
+  COMPAT_2 (OP_10760 ());
+}
+
+
+
+// STSR
+//rrrrr,111111,RRRRR + 0000000001000000:IX:::stsr
+//"stsr r<regID>, r<reg2>"
+//{
+//  COMPAT_2 (OP_4007E0 ());
+//}
+rrrrr,111111,RRRRR + 0000000001000000:IX:::stsr
+"stsr r<regID>, r<reg1>"
+{
+  COMPAT_2 (OP_4007E0 ());
+}
+
+
+
+// SUB
+rrrrr,001101,RRRRR:I:::sub
+"sub r<reg1>, r<reg2>"
+{
+  COMPAT_1 (OP_1A0 ());
+}
+
+
+
+// SUBR
+rrrrr,001100,RRRRR:I:::subr
+"subr r<reg1>, r<reg2>"
+{
+  COMPAT_1 (OP_180 ());
+}
+
+
+
+// SWITCH
+00000000010,RRRRR:I:::switch
+"switch r<reg1>"
+{
+  COMPAT_1 (OP_40 ());
+}
+
+
+
+// SXB
+00000000101,RRRRR:I:::sxb
+"sxb r<reg1>"
+{
+  COMPAT_1 (OP_A0 ());
+}
+
+
+
+// SXH
+00000000111,RRRRR:I:::sxh
+"sxh r<reg1>"
+{
+  COMPAT_1 (OP_E0 ());
+}
+
+
+
+// TRAP
+00000111111,iiiii + 0000000100000000:X:::trap
+"trap <vector>"
+{
+  COMPAT_2 (OP_10007E0 ());
+}
+
+
+
+// TST
+rrrrr,001011,RRRRR:I:::tst
+"tst r<reg1>, r<reg2>"
+{
+  COMPAT_1 (OP_160 ());
+}
+
+
+
+// TST1
+11,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1
+"tst1 <bit3>, <disp16>[r<reg1>]"
+{
+  COMPAT_2 (OP_C7C0 ());
+}
+
+rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
+"tst1 r<reg2>, [r<reg1>]"
+{
+  COMPAT_2 (OP_E607E0 ());
+}
+
+
+
+// XOR
+rrrrr,001001,RRRRR:I:::xor
+"xor r<reg1>, r<reg2>"
+{
+  COMPAT_1 (OP_120 ());
+}
+
+
+
+// XORI
+rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
+"xori <imm16>, r<reg1>, r<reg2>"
+{
+  COMPAT_2 (OP_6A0 ());
+}
+
+
+
+// ZXB
+00000000100,RRRRR:I:::zxb
+"zxb r<reg1>"
+{
+  COMPAT_1 (OP_80 ());
+}
+
+
+
+// ZXH
+00000000110,RRRRR:I:::zxh
+"zxh r<reg1>"
+{
+  COMPAT_1 (OP_C0 ());
+}
+
+
+
+// Special - breakpoint
+// 1111111111111111:Z:::breakpoint
+// {
+//   COMPAT_2 (OP_FFFF ());
+// }
+
+
+// start-sanitize-v850eq
+// DIVHN
+rrrrr,111111,RRRRR + wwwww,01010,iiii,00:XI:::divhn
+*v850eq
+"divhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
+{
+  COMPAT_2 (OP_28007E0 ());
+}
+
+
+
+// DIVHUN
+rrrrr,111111,RRRRR + wwwww,01010,iiii,10:XI:::divhun
+*v850eq
+"divhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
+{
+  COMPAT_2 (OP_28207E0 ());
+}
+
+
+
+// DIVN
+rrrrr,111111,RRRRR + wwwww,01011,iiii,00:XI:::divn
+*v850eq
+"divn <imm5>, r<reg1>, r<reg2>, r<reg3>"
+{
+  COMPAT_2 (OP_2C007E0 ());
+}
+
+
+
+// DIVUN
+rrrrr,111111,RRRRR + wwwww,01011,iiii,10:XI:::divun
+*v850eq
+"divun <imm5>, r<reg1>, r<reg2>, r<reg3>"
+{
+  COMPAT_2 (OP_2C207E0 ());
+}
+
+
+
+// SDIVHN
+rrrrr,111111,RRRRR + wwwww,00110,iiii,00:XI:::sdivhn
+*v850eq
+"sdivhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
+{
+  COMPAT_2 (OP_18007E0 ());
+}
+
+
+
+// SDIVHUN
+rrrrr,111111,RRRRR + wwwww,00110,iiii,10:XI:::sdivhun
+*v850eq
+"sdivhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
+{
+  COMPAT_2 (OP_18207E0 ());
+}
+
+
+
+// SDIVN
+rrrrr,111111,RRRRR + wwwww,00111,iiii,00:XI:::sdivn
+*v850eq
+"sdivn <imm5>, r<reg1>, r<reg2>, r<reg3>"
+{
+  COMPAT_2 (OP_1C007E0 ());
+}
+
+
+
+// SDIVUN
+rrrrr,111111,RRRRR + wwwww,00111,iiii,10:XI:::sdivun
+*v850eq
+"sdivun <imm5>, r<reg1>, r<reg2>, r<reg3>"
+{
+  COMPAT_2 (OP_1C207E0 ());
+}
+
+
+
+// PUSHML
+000001111110,LLLL + LLLLLLLLLLLL,S,001:XIV:::pushml
+*v850eq
+"pushml <list18>"
+{
+  COMPAT_2 (OP_107E0 ());
+}
+
+
+
+// PUSHHML
+000001111110,LLLL + LLLLLLLLLLLL,S,011:XIV:::pushmh
+*v850eq
+"pushhml <list18>"
+{
+  COMPAT_2 (OP_307E0 ());
+}
+
+
+
+// POPML
+000001111111,LLLL + LLLLLLLLLLLL,S,001:XIV:::popml
+*v850eq
+"popml <list18>"
+{
+  COMPAT_2 (OP_107F0 ());
+}
+
+
+
+// POPMH
+000001111111,LLLL + LLLLLLLLLLLL,S,011:XIV:::popmh
+*v850eq
+"popmh <list18>"
+{
+  COMPAT_2 (OP_307F0 ());
+}
+
+
+// end-sanitize-v850eq