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authorNick Clifton <nickc@redhat.com>2001-05-11 21:51:07 +0000
committerNick Clifton <nickc@redhat.com>2001-05-11 21:51:07 +0000
commitfb7a8ef0dfe79497e9bb51a8daeec2e70f1186d5 (patch)
treec80716ee7c8f5999cdd9f261fb53b7c05a93e3f0 /sim
parent6112b8746ae25d65f8cf77e786a87cd6723e72ce (diff)
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Fix handling of XScale LDRD and STRD instructions with post indexed addressing modes.
Diffstat (limited to 'sim')
-rw-r--r--sim/arm/ChangeLog5
-rw-r--r--sim/arm/armemu.c12
2 files changed, 11 insertions, 6 deletions
diff --git a/sim/arm/ChangeLog b/sim/arm/ChangeLog
index ee7b652..181f6f4 100644
--- a/sim/arm/ChangeLog
+++ b/sim/arm/ChangeLog
@@ -1,3 +1,8 @@
+2001-05-11 Nick Clifton <nickc@cambridge.redhat.com>
+
+ * armemu.c (ARMul_Emulate32): Fix handling of XScale LDRD and STRD
+ instructions with post indexed addressing modes.
+
2001-05-08 Jens-Christian Lache <lache@tu-harburg.de>
* armsupp.c (ARMul_FixCPSR): Check Mode not Bank in order to
diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c
index 0947470..4edac6f 100644
--- a/sim/arm/armemu.c
+++ b/sim/arm/armemu.c
@@ -619,7 +619,7 @@ check_PMUintr:
/* XScale Load Consecutive insn. */
ARMword temp = GetLS7RHS (state, instr);
ARMword temp2 = BIT (23) ? LHS + temp : LHS - temp;
- ARMword addr = BIT (24) ? temp2 : temp;
+ ARMword addr = BIT (24) ? temp2 : LHS;
if (BIT (12))
ARMul_UndefInstr (state, instr);
@@ -628,14 +628,14 @@ check_PMUintr:
ARMul_Abort (state, ARMul_DataAbortV);
else
{
- int wb = BIT (24) && BIT (21);
+ int wb = BIT (21) || (! BIT (24));
state->Reg[BITS (12, 15)] =
ARMul_LoadWordN (state, addr);
state->Reg[BITS (12, 15) + 1] =
ARMul_LoadWordN (state, addr + 4);
if (wb)
- LSBase = addr;
+ LSBase = temp2;
}
goto donext;
@@ -645,7 +645,7 @@ check_PMUintr:
/* XScale Store Consecutive insn. */
ARMword temp = GetLS7RHS (state, instr);
ARMword temp2 = BIT (23) ? LHS + temp : LHS - temp;
- ARMword addr = BIT (24) ? temp2 : temp;
+ ARMword addr = BIT (24) ? temp2 : LHS;
if (BIT (12))
ARMul_UndefInstr (state, instr);
@@ -659,8 +659,8 @@ check_PMUintr:
ARMul_StoreWordN (state, addr + 4,
state->Reg[BITS (12, 15) + 1]);
- if (BIT (21))
- LSBase = addr;
+ if (BIT (21)|| ! BIT (24))
+ LSBase = temp2;
}
goto donext;