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authorAlexandre Oliva <aoliva@redhat.com>2000-07-04 05:30:43 +0000
committerAlexandre Oliva <aoliva@redhat.com>2000-07-04 05:30:43 +0000
commite62263b8ecdd0439a7220068e5ae734ce1459149 (patch)
tree287839e3180d4bc40f62f0c60ffbea72d647a2f6 /sim
parentb0eae074ca6977683bf979afd6a98ab663431a47 (diff)
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* armemu.c (ARMul_Emulate): Compute writeback value before
loading, since the offset register may be the destination register.
Diffstat (limited to 'sim')
-rw-r--r--sim/arm/ChangeLog4
-rw-r--r--sim/arm/armemu.c24
2 files changed, 20 insertions, 8 deletions
diff --git a/sim/arm/ChangeLog b/sim/arm/ChangeLog
index 0e96893..139256d 100644
--- a/sim/arm/ChangeLog
+++ b/sim/arm/ChangeLog
@@ -1,5 +1,9 @@
2000-07-04 Alexandre Oliva <aoliva@redhat.com>
+ * armemu.c (ARMul_Emulate): Compute writeback value before
+ loading, since the offset register may be the destination
+ register.
+
* armdefs.h (SYSTEMBANK): Define as USERBANK.
* armsupp.c (ARMul_SwitchMode): Remove SYSTEMBANK cases.
diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c
index e4e963b..ffdcaa7 100644
--- a/sim/arm/armemu.c
+++ b/sim/arm/armemu.c
@@ -1998,8 +1998,9 @@ ARMul_Emulate26 (register ARMul_State * state)
UNDEF_LSRPCBaseWb;
UNDEF_LSRPCOffWb;
lhs = LHS;
+ temp = lhs - LSRegRHS;
if (LoadWord (state, instr, lhs))
- LSBase = lhs - LSRegRHS;
+ LSBase = temp;
break;
case 0x62: /* Store Word, WriteBack, Post Dec, Reg */
@@ -2030,9 +2031,10 @@ ARMul_Emulate26 (register ARMul_State * state)
UNDEF_LSRPCBaseWb;
UNDEF_LSRPCOffWb;
lhs = LHS;
+ temp = lhs - LSRegRHS;
state->NtransSig = LOW;
if (LoadWord (state, instr, lhs))
- LSBase = lhs - LSRegRHS;
+ LSBase = temp;
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
break;
@@ -2062,8 +2064,9 @@ ARMul_Emulate26 (register ARMul_State * state)
UNDEF_LSRPCBaseWb;
UNDEF_LSRPCOffWb;
lhs = LHS;
+ temp = lhs - LSRegRHS;
if (LoadByte (state, instr, lhs, LUNSIGNED))
- LSBase = lhs - LSRegRHS;
+ LSBase = temp;
break;
case 0x66: /* Store Byte, WriteBack, Post Dec, Reg */
@@ -2094,9 +2097,10 @@ ARMul_Emulate26 (register ARMul_State * state)
UNDEF_LSRPCBaseWb;
UNDEF_LSRPCOffWb;
lhs = LHS;
+ temp = lhs - LSRegRHS;
state->NtransSig = LOW;
if (LoadByte (state, instr, lhs, LUNSIGNED))
- LSBase = lhs - LSRegRHS;
+ LSBase = temp;
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
break;
@@ -2126,8 +2130,9 @@ ARMul_Emulate26 (register ARMul_State * state)
UNDEF_LSRPCBaseWb;
UNDEF_LSRPCOffWb;
lhs = LHS;
+ temp = lhs + LSRegRHS;
if (LoadWord (state, instr, lhs))
- LSBase = lhs + LSRegRHS;
+ LSBase = temp;
break;
case 0x6a: /* Store Word, WriteBack, Post Inc, Reg */
@@ -2158,9 +2163,10 @@ ARMul_Emulate26 (register ARMul_State * state)
UNDEF_LSRPCBaseWb;
UNDEF_LSRPCOffWb;
lhs = LHS;
+ temp = lhs + LSRegRHS;
state->NtransSig = LOW;
if (LoadWord (state, instr, lhs))
- LSBase = lhs + LSRegRHS;
+ LSBase = temp;
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
break;
@@ -2190,8 +2196,9 @@ ARMul_Emulate26 (register ARMul_State * state)
UNDEF_LSRPCBaseWb;
UNDEF_LSRPCOffWb;
lhs = LHS;
+ temp = lhs + LSRegRHS;
if (LoadByte (state, instr, lhs, LUNSIGNED))
- LSBase = lhs + LSRegRHS;
+ LSBase = temp;
break;
case 0x6e: /* Store Byte, WriteBack, Post Inc, Reg */
@@ -2222,9 +2229,10 @@ ARMul_Emulate26 (register ARMul_State * state)
UNDEF_LSRPCBaseWb;
UNDEF_LSRPCOffWb;
lhs = LHS;
+ temp = lhs + LSRegRHS;
state->NtransSig = LOW;
if (LoadByte (state, instr, lhs, LUNSIGNED))
- LSBase = lhs + LSRegRHS;
+ LSBase = temp;
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
break;