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| author | Andrew Cagney <cagney@redhat.com> | 1997-12-02 07:18:53 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1997-12-02 07:18:53 +0000 |
| commit | d294a657d50a41f1dcfe8c82f35f5eab27182731 (patch) | |
| tree | 19142a2edd651e8aa54e9ca843aee494c5a17d81 /sim | |
| parent | 9420287ed25a0cc7ef77fcc95ccab3f13d4614e3 (diff) | |
| download | gdb-d294a657d50a41f1dcfe8c82f35f5eab27182731.zip gdb-d294a657d50a41f1dcfe8c82f35f5eab27182731.tar.gz gdb-d294a657d50a41f1dcfe8c82f35f5eab27182731.tar.bz2 | |
For "msbu", subtract unsigned product from ACC,
Test.
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/d10v/ChangeLog | 1 | ||||
| -rw-r--r-- | sim/d10v/simops.c | 12 | ||||
| -rw-r--r-- | sim/testsuite/d10v-elf/.Sanitize | 1 | ||||
| -rw-r--r-- | sim/testsuite/d10v-elf/ChangeLog | 2 | ||||
| -rw-r--r-- | sim/testsuite/d10v-elf/Makefile.in | 1 | ||||
| -rw-r--r-- | sim/testsuite/d10v-elf/t-msbu.s | 28 |
6 files changed, 40 insertions, 5 deletions
diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog index b1a9568..013b93d 100644 --- a/sim/d10v/ChangeLog +++ b/sim/d10v/ChangeLog @@ -3,6 +3,7 @@ Tue Dec 2 15:01:08 1997 Andrew Cagney <cagney@b1.cygnus.com> * simops.c (OP_3A00): For "macu", perform multiply stage using 32 bit rather than 16 bit precision. (OP_3C00): For "mulxu", store unsigned product in ACC. + (OP_3800): For "msbu", subtract unsigned product from ACC, Tue Dec 2 11:04:37 1997 Andrew Cagney <cagney@b1.cygnus.com> diff --git a/sim/d10v/simops.c b/sim/d10v/simops.c index e5a0825..64c8a33 100644 --- a/sim/d10v/simops.c +++ b/sim/d10v/simops.c @@ -1518,14 +1518,18 @@ OP_1800 () void OP_3800 () { - int64 tmp; + uint64 tmp; + uint32 src1; + uint32 src2; trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG); - tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]); + src1 = (uint16) State.regs[OP[1]]; + src2 = (uint16) State.regs[OP[2]]; + tmp = src1 * src2; if (State.FX) - tmp = SEXT40( (tmp << 1) & MASK40); + tmp = (tmp << 1); - State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40; + State.a[OP[0]] = (State.a[OP[0]] - tmp) & MASK40; trace_output (OP_ACCUM); } diff --git a/sim/testsuite/d10v-elf/.Sanitize b/sim/testsuite/d10v-elf/.Sanitize index f5b7cc6..5ca3dd4 100644 --- a/sim/testsuite/d10v-elf/.Sanitize +++ b/sim/testsuite/d10v-elf/.Sanitize @@ -11,6 +11,7 @@ hello.s loop.s t-macros.i t-mac.s +t-msbu.s t-rachi.s t-rep.s t-mulxu.s diff --git a/sim/testsuite/d10v-elf/ChangeLog b/sim/testsuite/d10v-elf/ChangeLog index fc34fc1..a6f0854 100644 --- a/sim/testsuite/d10v-elf/ChangeLog +++ b/sim/testsuite/d10v-elf/ChangeLog @@ -1,6 +1,6 @@ Tue Dec 2 11:01:36 1997 Andrew Cagney <cagney@b1.cygnus.com> - * t-sub2w.s, t-mulxu.s, t-mac.s t-mvtac.s : New files. + * t-sub2w.s, t-mulxu.s, t-mac.s, t-mvtac.s, t-msbu.s: New files. * Makefile.in: Update. diff --git a/sim/testsuite/d10v-elf/Makefile.in b/sim/testsuite/d10v-elf/Makefile.in index d358327..c89ffb2 100644 --- a/sim/testsuite/d10v-elf/Makefile.in +++ b/sim/testsuite/d10v-elf/Makefile.in @@ -42,6 +42,7 @@ TESTS = \ hello.hi \ t-mac.ok \ t-mvtac.ok \ + t-msbu.ok \ t-mulxu.ok \ t-rachi.ok \ t-rep.ok \ diff --git a/sim/testsuite/d10v-elf/t-msbu.s b/sim/testsuite/d10v-elf/t-msbu.s new file mode 100644 index 0000000..04276cc --- /dev/null +++ b/sim/testsuite/d10v-elf/t-msbu.s @@ -0,0 +1,28 @@ +.include "t-macros.i" + + start + + ;; clear FX + ldi r2, #0x8005 + mvtc r2, cr0 + + loadacc2 a1 0x7f 0xffff 0xffff + ldi r8, 0xffff + ldi r9, 0x8001 +test_msbu1: + MSBU a1, r9, r8 + checkacc2 1 a1 0X7F 0x7FFF 0x8000 + + + ;; set FX + ldi r2, #0x8085 + mvtc r2, cr0 + + loadacc2 a1 0x7f 0xffff 0xffff + ldi r8, 0xffff + ldi r9, 0x8001 +test_msbu2: + MSBU a1, r9, r8 + checkacc2 2 a1 0X7E 0xFFFF 0x0001 + + exit0 |