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authorAndrew Cagney <cagney@redhat.com>1997-12-02 06:37:09 +0000
committerAndrew Cagney <cagney@redhat.com>1997-12-02 06:37:09 +0000
commit9420287ed25a0cc7ef77fcc95ccab3f13d4614e3 (patch)
tree5d79b9a18fecd4bad2d176e47e153fa34abf9b98 /sim
parente8b925f1fd9364cb0b6ba485afe2ccdda86f271f (diff)
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For "mulxu", store unsigned product in ACC.
Test.
Diffstat (limited to 'sim')
-rw-r--r--sim/d10v/ChangeLog1
-rw-r--r--sim/d10v/simops.c9
-rw-r--r--sim/testsuite/d10v-elf/.Sanitize1
-rw-r--r--sim/testsuite/d10v-elf/ChangeLog3
-rw-r--r--sim/testsuite/d10v-elf/Makefile.in8
-rw-r--r--sim/testsuite/d10v-elf/t-mulxu.s28
6 files changed, 43 insertions, 7 deletions
diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog
index d801cb2..b1a9568 100644
--- a/sim/d10v/ChangeLog
+++ b/sim/d10v/ChangeLog
@@ -2,6 +2,7 @@ Tue Dec 2 15:01:08 1997 Andrew Cagney <cagney@b1.cygnus.com>
* simops.c (OP_3A00): For "macu", perform multiply stage using 32
bit rather than 16 bit precision.
+ (OP_3C00): For "mulxu", store unsigned product in ACC.
Tue Dec 2 11:04:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
diff --git a/sim/d10v/simops.c b/sim/d10v/simops.c
index 6f12e5a..e5a0825 100644
--- a/sim/d10v/simops.c
+++ b/sim/d10v/simops.c
@@ -1577,11 +1577,14 @@ OP_1C00 ()
void
OP_3C00 ()
{
- int64 tmp;
+ uint64 tmp;
+ uint32 src1;
+ uint32 src2;
trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
- tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
-
+ src1 = (uint16) State.regs[OP[1]];
+ src2 = (uint16) State.regs[OP[2]];
+ tmp = src1 * src2;
if (State.FX)
tmp <<= 1;
diff --git a/sim/testsuite/d10v-elf/.Sanitize b/sim/testsuite/d10v-elf/.Sanitize
index c93cba1..f5b7cc6 100644
--- a/sim/testsuite/d10v-elf/.Sanitize
+++ b/sim/testsuite/d10v-elf/.Sanitize
@@ -13,6 +13,7 @@ t-macros.i
t-mac.s
t-rachi.s
t-rep.s
+t-mulxu.s
t-subi.s
t-sub2w.s
t-mvtac.s
diff --git a/sim/testsuite/d10v-elf/ChangeLog b/sim/testsuite/d10v-elf/ChangeLog
index 773737c..fc34fc1 100644
--- a/sim/testsuite/d10v-elf/ChangeLog
+++ b/sim/testsuite/d10v-elf/ChangeLog
@@ -1,6 +1,7 @@
Tue Dec 2 11:01:36 1997 Andrew Cagney <cagney@b1.cygnus.com>
- * t-sub2w.s: New file.
+ * t-sub2w.s, t-mulxu.s, t-mac.s t-mvtac.s : New files.
+
* Makefile.in: Update.
Mon Nov 17 20:14:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
diff --git a/sim/testsuite/d10v-elf/Makefile.in b/sim/testsuite/d10v-elf/Makefile.in
index d7fc130..d358327 100644
--- a/sim/testsuite/d10v-elf/Makefile.in
+++ b/sim/testsuite/d10v-elf/Makefile.in
@@ -40,12 +40,14 @@ RPATH_ENVVAR = @RPATH_ENVVAR@
TESTS = \
exit47.ko \
hello.hi \
+ t-mac.ok \
+ t-mvtac.ok \
+ t-mulxu.ok \
t-rachi.ok \
t-rep.ok \
- t-subi.ok \
t-sub2w.ok \
- t-mvtac.ok \
- t-mac.ok
+ t-subi.ok \
+#
AS_FOR_TARGET = `\
if [ -x ../../../gas/as-new ]; then \
diff --git a/sim/testsuite/d10v-elf/t-mulxu.s b/sim/testsuite/d10v-elf/t-mulxu.s
new file mode 100644
index 0000000..a8e6ffc
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-mulxu.s
@@ -0,0 +1,28 @@
+.include "t-macros.i"
+
+ start
+
+ ;; clear FX
+ ldi r2, #0x8005
+ mvtc r2, cr0
+
+ loadacc2 a1 0x7f 0xffff 0xffff
+ ldi r8, 0xffff
+ ldi r9, 0x8001
+test_mulxu1:
+ MULXU a1, r9, r8
+ checkacc2 1 a1 0x00 0x8000 0x7FFF
+
+
+ ;; set FX
+ ldi r2, #0x8085
+ mvtc r2, cr0
+
+ loadacc2 a1 0x7f 0xffff 0xffff
+ ldi r8, 0xffff
+ ldi r9, 0x8001
+test_mulxu2:
+ MULXU a1, r9, r8
+ checkacc2 2 a1 0x01 0x0000 0xFFFE
+
+ exit0