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authorDoug Evans <dje@google.com>1998-07-21 23:54:10 +0000
committerDoug Evans <dje@google.com>1998-07-21 23:54:10 +0000
commit7422fa0cc8de61c9c76e2284273d7173f714fa7c (patch)
tree0ef663503515fd14edefc47ea2901d50e26a4917 /sim
parentb817384cca766906892a3d883ea9614071ee8e71 (diff)
downloadgdb-7422fa0cc8de61c9c76e2284273d7173f714fa7c.zip
gdb-7422fa0cc8de61c9c76e2284273d7173f714fa7c.tar.gz
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* cpu.h,extract.c: Regenerate. pc-rel calcs done on f_dispNN now.
* cpux.h,readx.c,semx.c: Ditto.
Diffstat (limited to 'sim')
-rw-r--r--sim/m32r/ChangeLog36
-rw-r--r--sim/m32r/cpux.h827
-rw-r--r--sim/m32r/extract.c17
-rw-r--r--sim/m32r/readx.c20
-rw-r--r--sim/m32r/semx.c119
5 files changed, 583 insertions, 436 deletions
diff --git a/sim/m32r/ChangeLog b/sim/m32r/ChangeLog
index 8ca97d1..672fc52 100644
--- a/sim/m32r/ChangeLog
+++ b/sim/m32r/ChangeLog
@@ -1,3 +1,39 @@
+Tue Jul 21 16:53:10 1998 Doug Evans <devans@seba.cygnus.com>
+
+ * cpu.h,extract.c: Regenerate. pc-rel calcs done on f_dispNN now.
+start-sanitize-m32rx
+ * cpux.h,readx.c,semx.c: Ditto.
+end-sanitize-m32rx
+
+Wed Jul 1 16:51:15 1998 Doug Evans <devans@seba.cygnus.com>
+
+ * Makefile.in: cgen_maint -> CGEN_MAINT.
+ * configure.in: AC_SUBST cgen,cgendir. No longer look for guile.
+ * configure: Regenerate.
+ * arch.c,arch.h,cpuall.h: Regenerate.
+ * cpu.c,cpu.h,decode.c,decode.h,extract.c,model.c: Regenerate.
+ * sem-switch.c,sem.c: Regenerate.
+start-sanitize-m32rx
+ * cpux.c,cpux.h,decodex.c,decodex.h,modelx.c,readx.c: Regenerate.
+ * semx.c: Regenerate.
+ * mloopx.in (icount): Moved here from genmloop.sh.
+end-sanitize-m32rx
+
+Sat Jun 13 07:49:23 1998 Doug Evans <devans@fallis.cygnus.com>
+
+ * m32r-sim.h (M32R_MISC_PROFILE): New members insn_cycles, cti_stall,
+ load_stall,biggest_cycles.
+ * m32r.c (m32r_model_mark_get_h_gr): Update.
+ (m32r_model_init_insn_cycles,m32r_model_update_insn_cycles): New fns.
+ (m32r_model_record_cti,m32r_model_record_cycles): New functions.
+ * mloop.in: Call cycle init/update fns.
+ * model.c: Regenerate.
+start-sanitize-m32rx
+ * m32rx.c (m32rx_model_mark_get_h_gr): Update.
+ * mloopx.in: Call cycle init/update fns.
+ * modelx.c: Regenerate.
+end-sanitize-m32rx
+
Thu Jun 11 23:39:53 1998 Doug Evans <devans@seba.cygnus.com>
* Makefile.in (stamp-{arch,cpu,decode}): Pass CGEN_FLAGS_TO_PASS
diff --git a/sim/m32r/cpux.h b/sim/m32r/cpux.h
index 8be022e..352868a 100644
--- a/sim/m32r/cpux.h
+++ b/sim/m32r/cpux.h
@@ -1,6 +1,6 @@
/* CPU family header for m32rx.
-This file is machine generated with CGEN.
+THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
@@ -45,7 +45,7 @@ typedef struct {
#define GET_H_GR(a1) CPU (h_gr)[a1]
#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
/* control registers */
- USI h_cr[7];
+ USI h_cr[16];
#define GET_H_CR(a1) CPU (h_cr)[a1]
#define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x))
/* accumulator */
@@ -58,12 +58,6 @@ typedef struct {
/* end-sanitize-m32rx */
#define GET_H_ACCUMS(a1) CPU (h_accums)[a1]
#define SET_H_ACCUMS(a1, x) (CPU (h_accums)[a1] = (x))
-/* start-sanitize-m32rx */
- /* abort flag */
- UBI h_abort;
-/* end-sanitize-m32rx */
-#define GET_H_ABORT() CPU (h_abort)
-#define SET_H_ABORT(x) (CPU (h_abort) = (x))
/* condition bit */
UBI h_cond;
#define GET_H_COND() CPU (h_cond)
@@ -116,8 +110,6 @@ DI m32rx_h_accum_get (SIM_CPU *);
void m32rx_h_accum_set (SIM_CPU *, DI);
DI m32rx_h_accums_get (SIM_CPU *, UINT);
void m32rx_h_accums_set (SIM_CPU *, UINT, DI);
-UBI m32rx_h_abort_get (SIM_CPU *);
-void m32rx_h_abort_set (SIM_CPU *, UBI);
UBI m32rx_h_cond_get (SIM_CPU *);
void m32rx_h_cond_set (SIM_CPU *, UBI);
UBI m32rx_h_sm_get (SIM_CPU *);
@@ -134,281 +126,282 @@ SI m32rx_h_bpc_get (SIM_CPU *);
void m32rx_h_bpc_set (SIM_CPU *, SI);
UBI m32rx_h_lock_get (SIM_CPU *);
void m32rx_h_lock_set (SIM_CPU *, UBI);
-extern DECODE *m32rx_decode (SIM_CPU *, PCADDR, insn_t);
+
+/* These must be hand-written. */
+extern CPUREG_FETCH_FN m32rx_fetch_register;
+extern CPUREG_STORE_FN m32rx_store_register;
/* The ARGBUF struct. */
struct argbuf {
/* These are the baseclass definitions. */
unsigned int length;
PCADDR addr;
- const struct cgen_insn *opcode;
-#if ! defined (SCACHE_P)
- insn_t insn;
-#endif
+ const IDESC *idesc;
/* cpu specific data follows */
+ insn_t insn;
union {
struct { /* e.g. add $dr,$sr */
UINT f_r1;
UINT f_r2;
- } fmt_0_add;
- struct { /* e.g. add3 $dr,$sr,#$slo16 */
+ } fmt_add;
+ struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
UINT f_r1;
UINT f_r2;
HI f_simm16;
- } fmt_1_add3;
- struct { /* e.g. and3 $dr,$sr,#$uimm16 */
+ } fmt_add3;
+ struct { /* e.g. and3 $dr,$sr,$uimm16 */
UINT f_r1;
UINT f_r2;
USI f_uimm16;
- } fmt_2_and3;
- struct { /* e.g. or3 $dr,$sr,#$ulo16 */
+ } fmt_and3;
+ struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
UINT f_r1;
UINT f_r2;
UHI f_uimm16;
- } fmt_3_or3;
- struct { /* e.g. addi $dr,#$simm8 */
+ } fmt_or3;
+ struct { /* e.g. addi $dr,$simm8 */
UINT f_r1;
SI f_simm8;
- } fmt_4_addi;
+ } fmt_addi;
struct { /* e.g. addv $dr,$sr */
UINT f_r1;
UINT f_r2;
- } fmt_5_addv;
- struct { /* e.g. addv3 $dr,$sr,#$simm16 */
+ } fmt_addv;
+ struct { /* e.g. addv3 $dr,$sr,$simm16 */
UINT f_r1;
UINT f_r2;
SI f_simm16;
- } fmt_6_addv3;
+ } fmt_addv3;
struct { /* e.g. addx $dr,$sr */
UINT f_r1;
UINT f_r2;
- } fmt_7_addx;
- struct { /* e.g. bc $disp8 */
+ } fmt_addx;
+ struct { /* e.g. bc.s $disp8 */
IADDR f_disp8;
- } fmt_8_bc8;
- struct { /* e.g. bc $disp24 */
+ } fmt_bc8;
+ struct { /* e.g. bc.l $disp24 */
IADDR f_disp24;
- } fmt_9_bc24;
+ } fmt_bc24;
struct { /* e.g. beq $src1,$src2,$disp16 */
UINT f_r1;
UINT f_r2;
IADDR f_disp16;
- } fmt_10_beq;
+ } fmt_beq;
struct { /* e.g. beqz $src2,$disp16 */
UINT f_r2;
IADDR f_disp16;
- } fmt_11_beqz;
- struct { /* e.g. bl $disp8 */
+ } fmt_beqz;
+ struct { /* e.g. bl.s $disp8 */
IADDR f_disp8;
- } fmt_12_bl8;
- struct { /* e.g. bl $disp24 */
+ } fmt_bl8;
+ struct { /* e.g. bl.l $disp24 */
IADDR f_disp24;
- } fmt_13_bl24;
- struct { /* e.g. bcl $disp8 */
+ } fmt_bl24;
+ struct { /* e.g. bcl.s $disp8 */
IADDR f_disp8;
- } fmt_14_bcl8;
- struct { /* e.g. bcl $disp24 */
+ } fmt_bcl8;
+ struct { /* e.g. bcl.l $disp24 */
IADDR f_disp24;
- } fmt_15_bcl24;
- struct { /* e.g. bra $disp8 */
+ } fmt_bcl24;
+ struct { /* e.g. bra.s $disp8 */
IADDR f_disp8;
- } fmt_16_bra8;
- struct { /* e.g. bra $disp24 */
+ } fmt_bra8;
+ struct { /* e.g. bra.l $disp24 */
IADDR f_disp24;
- } fmt_17_bra24;
+ } fmt_bra24;
struct { /* e.g. cmp $src1,$src2 */
UINT f_r1;
UINT f_r2;
- } fmt_18_cmp;
- struct { /* e.g. cmpi $src2,#$simm16 */
+ } fmt_cmp;
+ struct { /* e.g. cmpi $src2,$simm16 */
UINT f_r2;
SI f_simm16;
- } fmt_19_cmpi;
- struct { /* e.g. cmpui $src2,#$uimm16 */
- UINT f_r2;
- USI f_uimm16;
- } fmt_20_cmpui;
+ } fmt_cmpi;
struct { /* e.g. cmpz $src2 */
UINT f_r2;
- } fmt_21_cmpz;
+ } fmt_cmpz;
struct { /* e.g. div $dr,$sr */
UINT f_r1;
UINT f_r2;
- } fmt_22_div;
+ } fmt_div;
struct { /* e.g. jc $sr */
UINT f_r2;
- } fmt_23_jc;
+ } fmt_jc;
struct { /* e.g. jl $sr */
UINT f_r2;
- } fmt_24_jl;
+ } fmt_jl;
struct { /* e.g. jmp $sr */
UINT f_r2;
- } fmt_25_jmp;
+ } fmt_jmp;
struct { /* e.g. ld $dr,@$sr */
UINT f_r1;
UINT f_r2;
- } fmt_26_ld;
+ } fmt_ld;
struct { /* e.g. ld $dr,@($slo16,$sr) */
UINT f_r1;
UINT f_r2;
HI f_simm16;
- } fmt_27_ld_d;
+ } fmt_ld_d;
struct { /* e.g. ldb $dr,@$sr */
UINT f_r1;
UINT f_r2;
- } fmt_28_ldb;
+ } fmt_ldb;
struct { /* e.g. ldb $dr,@($slo16,$sr) */
UINT f_r1;
UINT f_r2;
HI f_simm16;
- } fmt_29_ldb_d;
+ } fmt_ldb_d;
struct { /* e.g. ldh $dr,@$sr */
UINT f_r1;
UINT f_r2;
- } fmt_30_ldh;
+ } fmt_ldh;
struct { /* e.g. ldh $dr,@($slo16,$sr) */
UINT f_r1;
UINT f_r2;
HI f_simm16;
- } fmt_31_ldh_d;
+ } fmt_ldh_d;
struct { /* e.g. ld $dr,@$sr+ */
UINT f_r1;
UINT f_r2;
- } fmt_32_ld_plus;
- struct { /* e.g. ld24 $dr,#$uimm24 */
+ } fmt_ld_plus;
+ struct { /* e.g. ld24 $dr,$uimm24 */
UINT f_r1;
ADDR f_uimm24;
- } fmt_33_ld24;
- struct { /* e.g. ldi $dr,#$simm8 */
+ } fmt_ld24;
+ struct { /* e.g. ldi8 $dr,$simm8 */
UINT f_r1;
SI f_simm8;
- } fmt_34_ldi8;
- struct { /* e.g. ldi $dr,$slo16 */
+ } fmt_ldi8;
+ struct { /* e.g. ldi16 $dr,$hash$slo16 */
UINT f_r1;
HI f_simm16;
- } fmt_35_ldi16;
+ } fmt_ldi16;
struct { /* e.g. lock $dr,@$sr */
UINT f_r1;
UINT f_r2;
- } fmt_36_lock;
+ } fmt_lock;
struct { /* e.g. machi $src1,$src2,$acc */
UINT f_r1;
UINT f_acc;
UINT f_r2;
- } fmt_37_machi_a;
+ } fmt_machi_a;
+ struct { /* e.g. macwhi $src1,$src2 */
+ UINT f_r1;
+ UINT f_r2;
+ } fmt_macwhi;
struct { /* e.g. mulhi $src1,$src2,$acc */
UINT f_r1;
UINT f_acc;
UINT f_r2;
- } fmt_38_mulhi_a;
+ } fmt_mulhi_a;
+ struct { /* e.g. mulwhi $src1,$src2 */
+ UINT f_r1;
+ UINT f_r2;
+ } fmt_mulwhi;
struct { /* e.g. mv $dr,$sr */
UINT f_r1;
UINT f_r2;
- } fmt_39_mv;
+ } fmt_mv;
struct { /* e.g. mvfachi $dr,$accs */
UINT f_r1;
UINT f_accs;
- } fmt_40_mvfachi_a;
+ } fmt_mvfachi_a;
struct { /* e.g. mvfc $dr,$scr */
UINT f_r1;
UINT f_r2;
- } fmt_41_mvfc;
+ } fmt_mvfc;
struct { /* e.g. mvtachi $src1,$accs */
UINT f_r1;
UINT f_accs;
- } fmt_42_mvtachi_a;
+ } fmt_mvtachi_a;
struct { /* e.g. mvtc $sr,$dcr */
UINT f_r1;
UINT f_r2;
- } fmt_43_mvtc;
+ } fmt_mvtc;
struct { /* e.g. nop */
int empty;
- } fmt_44_nop;
- struct { /* e.g. rac $accd,$accs,#$imm1 */
+ } fmt_nop;
+ struct { /* e.g. rac $accd,$accs,$imm1 */
UINT f_accd;
UINT f_accs;
USI f_imm1;
- } fmt_45_rac_dsi;
+ } fmt_rac_dsi;
struct { /* e.g. rte */
int empty;
- } fmt_46_rte;
- struct { /* e.g. seth $dr,#$hi16 */
+ } fmt_rte;
+ struct { /* e.g. seth $dr,$hash$hi16 */
UINT f_r1;
UHI f_hi16;
- } fmt_47_seth;
- struct { /* e.g. sll3 $dr,$sr,#$simm16 */
+ } fmt_seth;
+ struct { /* e.g. sll3 $dr,$sr,$simm16 */
UINT f_r1;
UINT f_r2;
SI f_simm16;
- } fmt_48_sll3;
- struct { /* e.g. slli $dr,#$uimm5 */
+ } fmt_sll3;
+ struct { /* e.g. slli $dr,$uimm5 */
UINT f_r1;
USI f_uimm5;
- } fmt_49_slli;
+ } fmt_slli;
struct { /* e.g. st $src1,@$src2 */
UINT f_r1;
UINT f_r2;
- } fmt_50_st;
+ } fmt_st;
struct { /* e.g. st $src1,@($slo16,$src2) */
UINT f_r1;
UINT f_r2;
HI f_simm16;
- } fmt_51_st_d;
+ } fmt_st_d;
struct { /* e.g. stb $src1,@$src2 */
UINT f_r1;
UINT f_r2;
- } fmt_52_stb;
+ } fmt_stb;
struct { /* e.g. stb $src1,@($slo16,$src2) */
UINT f_r1;
UINT f_r2;
HI f_simm16;
- } fmt_53_stb_d;
+ } fmt_stb_d;
struct { /* e.g. sth $src1,@$src2 */
UINT f_r1;
UINT f_r2;
- } fmt_54_sth;
+ } fmt_sth;
struct { /* e.g. sth $src1,@($slo16,$src2) */
UINT f_r1;
UINT f_r2;
HI f_simm16;
- } fmt_55_sth_d;
+ } fmt_sth_d;
struct { /* e.g. st $src1,@+$src2 */
UINT f_r1;
UINT f_r2;
- } fmt_56_st_plus;
- struct { /* e.g. trap #$uimm4 */
+ } fmt_st_plus;
+ struct { /* e.g. trap $uimm4 */
USI f_uimm4;
- } fmt_57_trap;
+ } fmt_trap;
struct { /* e.g. unlock $src1,@$src2 */
UINT f_r1;
UINT f_r2;
- } fmt_58_unlock;
+ } fmt_unlock;
struct { /* e.g. satb $dr,$sr */
UINT f_r1;
UINT f_r2;
- } fmt_59_satb;
+ } fmt_satb;
struct { /* e.g. sat $dr,$sr */
UINT f_r1;
UINT f_r2;
- } fmt_60_sat;
+ } fmt_sat;
struct { /* e.g. sadd */
int empty;
- } fmt_61_sadd;
+ } fmt_sadd;
struct { /* e.g. macwu1 $src1,$src2 */
UINT f_r1;
UINT f_r2;
- } fmt_62_macwu1;
- struct { /* e.g. msblo $src1,$src2 */
- UINT f_r1;
- UINT f_r2;
- } fmt_63_msblo;
+ } fmt_macwu1;
struct { /* e.g. mulwu1 $src1,$src2 */
UINT f_r1;
UINT f_r2;
- } fmt_64_mulwu1;
+ } fmt_mulwu1;
struct { /* e.g. sc */
int empty;
- } fmt_65_sc;
+ } fmt_sc;
} fields;
#if 1 || WITH_PROFILE_MODEL_P /*FIXME:wip*/
unsigned long h_gr_get;
@@ -425,10 +418,10 @@ struct scache {
IADDR next;
union {
#if ! WITH_SEM_SWITCH_FULL
- SEMANTIC_FN *sem_fn;
+ SEMANTIC_FN *sem_full;
#endif
#if ! WITH_SEM_SWITCH_FAST
- SEMANTIC_FN *sem_fast_fn;
+ SEMANTIC_FN *sem_fast;
#endif
#if WITH_SEM_SWITCH_FULL || WITH_SEM_SWITCH_FAST
#ifdef __GNUC__
@@ -444,21 +437,21 @@ struct scache {
/* Macros to simplify extraction, reading and semantic code.
These define and assign the local vars that contain the insn's fields. */
-#define EXTRACT_FMT_0_ADD_VARS \
+#define EXTRACT_FMT_ADD_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_0_ADD_CODE \
+#define EXTRACT_FMT_ADD_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_1_ADD3_VARS \
+#define EXTRACT_FMT_ADD3_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -466,7 +459,7 @@ struct scache {
UINT f_r2; \
int f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_1_ADD3_CODE \
+#define EXTRACT_FMT_ADD3_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -474,7 +467,7 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_2_AND3_VARS \
+#define EXTRACT_FMT_AND3_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -482,7 +475,7 @@ struct scache {
UINT f_r2; \
UINT f_uimm16; \
unsigned int length;
-#define EXTRACT_FMT_2_AND3_CODE \
+#define EXTRACT_FMT_AND3_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -490,7 +483,7 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_3_OR3_VARS \
+#define EXTRACT_FMT_OR3_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -498,7 +491,7 @@ struct scache {
UINT f_r2; \
UINT f_uimm16; \
unsigned int length;
-#define EXTRACT_FMT_3_OR3_CODE \
+#define EXTRACT_FMT_OR3_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -506,33 +499,33 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_4_ADDI_VARS \
+#define EXTRACT_FMT_ADDI_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
int f_simm8; \
unsigned int length;
-#define EXTRACT_FMT_4_ADDI_CODE \
+#define EXTRACT_FMT_ADDI_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
-#define EXTRACT_FMT_5_ADDV_VARS \
+#define EXTRACT_FMT_ADDV_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_5_ADDV_CODE \
+#define EXTRACT_FMT_ADDV_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_6_ADDV3_VARS \
+#define EXTRACT_FMT_ADDV3_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -540,7 +533,7 @@ struct scache {
UINT f_r2; \
int f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_6_ADDV3_CODE \
+#define EXTRACT_FMT_ADDV3_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -548,45 +541,45 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_7_ADDX_VARS \
+#define EXTRACT_FMT_ADDX_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_7_ADDX_CODE \
+#define EXTRACT_FMT_ADDX_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_8_BC8_VARS \
+#define EXTRACT_FMT_BC8_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
int f_disp8; \
unsigned int length;
-#define EXTRACT_FMT_8_BC8_CODE \
+#define EXTRACT_FMT_BC8_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_disp8 = ((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2)); \
+ f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
-#define EXTRACT_FMT_9_BC24_VARS \
+#define EXTRACT_FMT_BC24_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
int f_disp24; \
unsigned int length;
-#define EXTRACT_FMT_9_BC24_CODE \
+#define EXTRACT_FMT_BC24_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
- f_disp24 = ((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2)); \
+ f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
-#define EXTRACT_FMT_10_BEQ_VARS \
+#define EXTRACT_FMT_BEQ_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -594,15 +587,15 @@ struct scache {
UINT f_r2; \
int f_disp16; \
unsigned int length;
-#define EXTRACT_FMT_10_BEQ_CODE \
+#define EXTRACT_FMT_BEQ_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
- f_disp16 = ((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2)); \
+ f_disp16 = ((((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2))) + (pc)); \
-#define EXTRACT_FMT_11_BEQZ_VARS \
+#define EXTRACT_FMT_BEQZ_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -610,101 +603,101 @@ struct scache {
UINT f_r2; \
int f_disp16; \
unsigned int length;
-#define EXTRACT_FMT_11_BEQZ_CODE \
+#define EXTRACT_FMT_BEQZ_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
- f_disp16 = ((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2)); \
+ f_disp16 = ((((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2))) + (pc)); \
-#define EXTRACT_FMT_12_BL8_VARS \
+#define EXTRACT_FMT_BL8_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
int f_disp8; \
unsigned int length;
-#define EXTRACT_FMT_12_BL8_CODE \
+#define EXTRACT_FMT_BL8_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_disp8 = ((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2)); \
+ f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
-#define EXTRACT_FMT_13_BL24_VARS \
+#define EXTRACT_FMT_BL24_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
int f_disp24; \
unsigned int length;
-#define EXTRACT_FMT_13_BL24_CODE \
+#define EXTRACT_FMT_BL24_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
- f_disp24 = ((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2)); \
+ f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
-#define EXTRACT_FMT_14_BCL8_VARS \
+#define EXTRACT_FMT_BCL8_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
int f_disp8; \
unsigned int length;
-#define EXTRACT_FMT_14_BCL8_CODE \
+#define EXTRACT_FMT_BCL8_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_disp8 = ((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2)); \
+ f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
-#define EXTRACT_FMT_15_BCL24_VARS \
+#define EXTRACT_FMT_BCL24_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
int f_disp24; \
unsigned int length;
-#define EXTRACT_FMT_15_BCL24_CODE \
+#define EXTRACT_FMT_BCL24_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
- f_disp24 = ((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2)); \
+ f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
-#define EXTRACT_FMT_16_BRA8_VARS \
+#define EXTRACT_FMT_BRA8_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
int f_disp8; \
unsigned int length;
-#define EXTRACT_FMT_16_BRA8_CODE \
+#define EXTRACT_FMT_BRA8_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_disp8 = ((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2)); \
+ f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
-#define EXTRACT_FMT_17_BRA24_VARS \
+#define EXTRACT_FMT_BRA24_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
int f_disp24; \
unsigned int length;
-#define EXTRACT_FMT_17_BRA24_CODE \
+#define EXTRACT_FMT_BRA24_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
- f_disp24 = ((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2)); \
+ f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
-#define EXTRACT_FMT_18_CMP_VARS \
+#define EXTRACT_FMT_CMP_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_18_CMP_CODE \
+#define EXTRACT_FMT_CMP_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_19_CMPI_VARS \
+#define EXTRACT_FMT_CMPI_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -712,7 +705,7 @@ struct scache {
UINT f_r2; \
int f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_19_CMPI_CODE \
+#define EXTRACT_FMT_CMPI_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -720,37 +713,21 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_20_CMPUI_VARS \
+#define EXTRACT_FMT_CMPZ_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
- UINT f_uimm16; \
unsigned int length;
-#define EXTRACT_FMT_20_CMPUI_CODE \
- length = 4; \
- f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
- f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
-
-#define EXTRACT_FMT_21_CMPZ_VARS \
- /* Instruction fields. */ \
- UINT f_op1; \
- UINT f_r1; \
- UINT f_op2; \
- UINT f_r2; \
- unsigned int length;
-#define EXTRACT_FMT_21_CMPZ_CODE \
+#define EXTRACT_FMT_CMPZ_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_22_DIV_VARS \
+#define EXTRACT_FMT_DIV_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -758,7 +735,7 @@ struct scache {
UINT f_r2; \
int f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_22_DIV_CODE \
+#define EXTRACT_FMT_DIV_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -766,63 +743,63 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_23_JC_VARS \
+#define EXTRACT_FMT_JC_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_23_JC_CODE \
+#define EXTRACT_FMT_JC_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_24_JL_VARS \
+#define EXTRACT_FMT_JL_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_24_JL_CODE \
+#define EXTRACT_FMT_JL_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_25_JMP_VARS \
+#define EXTRACT_FMT_JMP_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_25_JMP_CODE \
+#define EXTRACT_FMT_JMP_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_26_LD_VARS \
+#define EXTRACT_FMT_LD_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_26_LD_CODE \
+#define EXTRACT_FMT_LD_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_27_LD_D_VARS \
+#define EXTRACT_FMT_LD_D_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -830,7 +807,7 @@ struct scache {
UINT f_r2; \
int f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_27_LD_D_CODE \
+#define EXTRACT_FMT_LD_D_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -838,21 +815,21 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_28_LDB_VARS \
+#define EXTRACT_FMT_LDB_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_28_LDB_CODE \
+#define EXTRACT_FMT_LDB_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_29_LDB_D_VARS \
+#define EXTRACT_FMT_LDB_D_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -860,7 +837,7 @@ struct scache {
UINT f_r2; \
int f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_29_LDB_D_CODE \
+#define EXTRACT_FMT_LDB_D_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -868,21 +845,21 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_30_LDH_VARS \
+#define EXTRACT_FMT_LDH_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_30_LDH_CODE \
+#define EXTRACT_FMT_LDH_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_31_LDH_D_VARS \
+#define EXTRACT_FMT_LDH_D_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -890,7 +867,7 @@ struct scache {
UINT f_r2; \
int f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_31_LDH_D_CODE \
+#define EXTRACT_FMT_LDH_D_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -898,45 +875,45 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_32_LD_PLUS_VARS \
+#define EXTRACT_FMT_LD_PLUS_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_32_LD_PLUS_CODE \
+#define EXTRACT_FMT_LD_PLUS_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_33_LD24_VARS \
+#define EXTRACT_FMT_LD24_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_uimm24; \
unsigned int length;
-#define EXTRACT_FMT_33_LD24_CODE \
+#define EXTRACT_FMT_LD24_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
f_uimm24 = EXTRACT_UNSIGNED (insn, 32, 8, 24); \
-#define EXTRACT_FMT_34_LDI8_VARS \
+#define EXTRACT_FMT_LDI8_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
int f_simm8; \
unsigned int length;
-#define EXTRACT_FMT_34_LDI8_CODE \
+#define EXTRACT_FMT_LDI8_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
-#define EXTRACT_FMT_35_LDI16_VARS \
+#define EXTRACT_FMT_LDI16_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -944,7 +921,7 @@ struct scache {
UINT f_r2; \
int f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_35_LDI16_CODE \
+#define EXTRACT_FMT_LDI16_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -952,21 +929,21 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_36_LOCK_VARS \
+#define EXTRACT_FMT_LOCK_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_36_LOCK_CODE \
+#define EXTRACT_FMT_LOCK_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_37_MACHI_A_VARS \
+#define EXTRACT_FMT_MACHI_A_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -974,7 +951,7 @@ struct scache {
UINT f_op23; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_37_MACHI_A_CODE \
+#define EXTRACT_FMT_MACHI_A_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
@@ -982,7 +959,21 @@ struct scache {
f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_38_MULHI_A_VARS \
+#define EXTRACT_FMT_MACWHI_VARS \
+ /* Instruction fields. */ \
+ UINT f_op1; \
+ UINT f_r1; \
+ UINT f_op2; \
+ UINT f_r2; \
+ unsigned int length;
+#define EXTRACT_FMT_MACWHI_CODE \
+ length = 2; \
+ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
+ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+
+#define EXTRACT_FMT_MULHI_A_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -990,7 +981,7 @@ struct scache {
UINT f_op23; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_38_MULHI_A_CODE \
+#define EXTRACT_FMT_MULHI_A_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
@@ -998,21 +989,35 @@ struct scache {
f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_39_MV_VARS \
+#define EXTRACT_FMT_MULWHI_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_39_MV_CODE \
+#define EXTRACT_FMT_MULWHI_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_40_MVFACHI_A_VARS \
+#define EXTRACT_FMT_MV_VARS \
+ /* Instruction fields. */ \
+ UINT f_op1; \
+ UINT f_r1; \
+ UINT f_op2; \
+ UINT f_r2; \
+ unsigned int length;
+#define EXTRACT_FMT_MV_CODE \
+ length = 2; \
+ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
+ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+
+#define EXTRACT_FMT_MVFACHI_A_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -1020,7 +1025,7 @@ struct scache {
UINT f_accs; \
UINT f_op3; \
unsigned int length;
-#define EXTRACT_FMT_40_MVFACHI_A_CODE \
+#define EXTRACT_FMT_MVFACHI_A_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
@@ -1028,21 +1033,21 @@ struct scache {
f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
-#define EXTRACT_FMT_41_MVFC_VARS \
+#define EXTRACT_FMT_MVFC_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_41_MVFC_CODE \
+#define EXTRACT_FMT_MVFC_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_42_MVTACHI_A_VARS \
+#define EXTRACT_FMT_MVTACHI_A_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -1050,7 +1055,7 @@ struct scache {
UINT f_accs; \
UINT f_op3; \
unsigned int length;
-#define EXTRACT_FMT_42_MVTACHI_A_CODE \
+#define EXTRACT_FMT_MVTACHI_A_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
@@ -1058,35 +1063,35 @@ struct scache {
f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
-#define EXTRACT_FMT_43_MVTC_VARS \
+#define EXTRACT_FMT_MVTC_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_43_MVTC_CODE \
+#define EXTRACT_FMT_MVTC_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_44_NOP_VARS \
+#define EXTRACT_FMT_NOP_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_44_NOP_CODE \
+#define EXTRACT_FMT_NOP_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_45_RAC_DSI_VARS \
+#define EXTRACT_FMT_RAC_DSI_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_accd; \
@@ -1096,7 +1101,7 @@ struct scache {
UINT f_bit14; \
UINT f_imm1; \
unsigned int length;
-#define EXTRACT_FMT_45_RAC_DSI_CODE \
+#define EXTRACT_FMT_RAC_DSI_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_accd = EXTRACT_UNSIGNED (insn, 16, 4, 2); \
@@ -1106,21 +1111,21 @@ struct scache {
f_bit14 = EXTRACT_UNSIGNED (insn, 16, 14, 1); \
f_imm1 = ((EXTRACT_UNSIGNED (insn, 16, 15, 1)) + (1)); \
-#define EXTRACT_FMT_46_RTE_VARS \
+#define EXTRACT_FMT_RTE_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_46_RTE_CODE \
+#define EXTRACT_FMT_RTE_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_47_SETH_VARS \
+#define EXTRACT_FMT_SETH_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -1128,7 +1133,7 @@ struct scache {
UINT f_r2; \
UINT f_hi16; \
unsigned int length;
-#define EXTRACT_FMT_47_SETH_CODE \
+#define EXTRACT_FMT_SETH_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -1136,7 +1141,7 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_hi16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_48_SLL3_VARS \
+#define EXTRACT_FMT_SLL3_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -1144,7 +1149,7 @@ struct scache {
UINT f_r2; \
int f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_48_SLL3_CODE \
+#define EXTRACT_FMT_SLL3_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -1152,35 +1157,35 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_49_SLLI_VARS \
+#define EXTRACT_FMT_SLLI_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_shift_op2; \
UINT f_uimm5; \
unsigned int length;
-#define EXTRACT_FMT_49_SLLI_CODE \
+#define EXTRACT_FMT_SLLI_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3); \
f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5); \
-#define EXTRACT_FMT_50_ST_VARS \
+#define EXTRACT_FMT_ST_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_50_ST_CODE \
+#define EXTRACT_FMT_ST_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_51_ST_D_VARS \
+#define EXTRACT_FMT_ST_D_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -1188,7 +1193,7 @@ struct scache {
UINT f_r2; \
int f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_51_ST_D_CODE \
+#define EXTRACT_FMT_ST_D_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -1196,21 +1201,21 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_52_STB_VARS \
+#define EXTRACT_FMT_STB_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_52_STB_CODE \
+#define EXTRACT_FMT_STB_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_53_STB_D_VARS \
+#define EXTRACT_FMT_STB_D_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -1218,7 +1223,7 @@ struct scache {
UINT f_r2; \
int f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_53_STB_D_CODE \
+#define EXTRACT_FMT_STB_D_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -1226,21 +1231,21 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_54_STH_VARS \
+#define EXTRACT_FMT_STH_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_54_STH_CODE \
+#define EXTRACT_FMT_STH_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_55_STH_D_VARS \
+#define EXTRACT_FMT_STH_D_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -1248,7 +1253,7 @@ struct scache {
UINT f_r2; \
int f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_55_STH_D_CODE \
+#define EXTRACT_FMT_STH_D_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -1256,49 +1261,49 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_56_ST_PLUS_VARS \
+#define EXTRACT_FMT_ST_PLUS_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_56_ST_PLUS_CODE \
+#define EXTRACT_FMT_ST_PLUS_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_57_TRAP_VARS \
+#define EXTRACT_FMT_TRAP_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_uimm4; \
unsigned int length;
-#define EXTRACT_FMT_57_TRAP_CODE \
+#define EXTRACT_FMT_TRAP_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_uimm4 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_58_UNLOCK_VARS \
+#define EXTRACT_FMT_UNLOCK_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_58_UNLOCK_CODE \
+#define EXTRACT_FMT_UNLOCK_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_59_SATB_VARS \
+#define EXTRACT_FMT_SATB_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -1306,7 +1311,7 @@ struct scache {
UINT f_r2; \
UINT f_uimm16; \
unsigned int length;
-#define EXTRACT_FMT_59_SATB_CODE \
+#define EXTRACT_FMT_SATB_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -1314,7 +1319,7 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_60_SAT_VARS \
+#define EXTRACT_FMT_SAT_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -1322,7 +1327,7 @@ struct scache {
UINT f_r2; \
UINT f_uimm16; \
unsigned int length;
-#define EXTRACT_FMT_60_SAT_CODE \
+#define EXTRACT_FMT_SAT_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -1330,70 +1335,56 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_61_SADD_VARS \
- /* Instruction fields. */ \
- UINT f_op1; \
- UINT f_r1; \
- UINT f_op2; \
- UINT f_r2; \
- unsigned int length;
-#define EXTRACT_FMT_61_SADD_CODE \
- length = 2; \
- f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-
-#define EXTRACT_FMT_62_MACWU1_VARS \
+#define EXTRACT_FMT_SADD_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_62_MACWU1_CODE \
+#define EXTRACT_FMT_SADD_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_63_MSBLO_VARS \
+#define EXTRACT_FMT_MACWU1_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_63_MSBLO_CODE \
+#define EXTRACT_FMT_MACWU1_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_64_MULWU1_VARS \
+#define EXTRACT_FMT_MULWU1_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_64_MULWU1_CODE \
+#define EXTRACT_FMT_MULWU1_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_65_SC_VARS \
+#define EXTRACT_FMT_SC_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_65_SC_CODE \
+#define EXTRACT_FMT_SC_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
@@ -1407,269 +1398,269 @@ struct parexec {
struct { /* e.g. add $dr,$sr */
SI dr;
SI sr;
- } fmt_0_add;
- struct { /* e.g. add3 $dr,$sr,#$slo16 */
- HI slo16;
+ } fmt_add;
+ struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
SI sr;
- } fmt_1_add3;
- struct { /* e.g. and3 $dr,$sr,#$uimm16 */
+ HI slo16;
+ } fmt_add3;
+ struct { /* e.g. and3 $dr,$sr,$uimm16 */
SI sr;
USI uimm16;
- } fmt_2_and3;
- struct { /* e.g. or3 $dr,$sr,#$ulo16 */
+ } fmt_and3;
+ struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
SI sr;
UHI ulo16;
- } fmt_3_or3;
- struct { /* e.g. addi $dr,#$simm8 */
+ } fmt_or3;
+ struct { /* e.g. addi $dr,$simm8 */
SI dr;
SI simm8;
- } fmt_4_addi;
+ } fmt_addi;
struct { /* e.g. addv $dr,$sr */
SI dr;
SI sr;
- } fmt_5_addv;
- struct { /* e.g. addv3 $dr,$sr,#$simm16 */
- SI simm16;
+ } fmt_addv;
+ struct { /* e.g. addv3 $dr,$sr,$simm16 */
SI sr;
- } fmt_6_addv3;
+ SI simm16;
+ } fmt_addv3;
struct { /* e.g. addx $dr,$sr */
- UBI condbit;
SI dr;
SI sr;
- } fmt_7_addx;
- struct { /* e.g. bc $disp8 */
UBI condbit;
- IADDR disp8;
- } fmt_8_bc8;
- struct { /* e.g. bc $disp24 */
+ } fmt_addx;
+ struct { /* e.g. bc.s $disp8 */
+ UBI condbit;
+ USI disp8;
+ } fmt_bc8;
+ struct { /* e.g. bc.l $disp24 */
UBI condbit;
- IADDR disp24;
- } fmt_9_bc24;
+ USI disp24;
+ } fmt_bc24;
struct { /* e.g. beq $src1,$src2,$disp16 */
- IADDR disp16;
SI src1;
SI src2;
- } fmt_10_beq;
+ USI disp16;
+ } fmt_beq;
struct { /* e.g. beqz $src2,$disp16 */
- IADDR disp16;
SI src2;
- } fmt_11_beqz;
- struct { /* e.g. bl $disp8 */
- IADDR disp8;
+ USI disp16;
+ } fmt_beqz;
+ struct { /* e.g. bl.s $disp8 */
USI pc;
- } fmt_12_bl8;
- struct { /* e.g. bl $disp24 */
- IADDR disp24;
+ USI disp8;
+ } fmt_bl8;
+ struct { /* e.g. bl.l $disp24 */
USI pc;
- } fmt_13_bl24;
- struct { /* e.g. bcl $disp8 */
+ USI disp24;
+ } fmt_bl24;
+ struct { /* e.g. bcl.s $disp8 */
UBI condbit;
- IADDR disp8;
USI pc;
- } fmt_14_bcl8;
- struct { /* e.g. bcl $disp24 */
+ USI disp8;
+ } fmt_bcl8;
+ struct { /* e.g. bcl.l $disp24 */
UBI condbit;
- IADDR disp24;
USI pc;
- } fmt_15_bcl24;
- struct { /* e.g. bra $disp8 */
- IADDR disp8;
- } fmt_16_bra8;
- struct { /* e.g. bra $disp24 */
- IADDR disp24;
- } fmt_17_bra24;
+ USI disp24;
+ } fmt_bcl24;
+ struct { /* e.g. bra.s $disp8 */
+ USI disp8;
+ } fmt_bra8;
+ struct { /* e.g. bra.l $disp24 */
+ USI disp24;
+ } fmt_bra24;
struct { /* e.g. cmp $src1,$src2 */
SI src1;
SI src2;
- } fmt_18_cmp;
- struct { /* e.g. cmpi $src2,#$simm16 */
- SI simm16;
- SI src2;
- } fmt_19_cmpi;
- struct { /* e.g. cmpui $src2,#$uimm16 */
+ } fmt_cmp;
+ struct { /* e.g. cmpi $src2,$simm16 */
SI src2;
- USI uimm16;
- } fmt_20_cmpui;
+ SI simm16;
+ } fmt_cmpi;
struct { /* e.g. cmpz $src2 */
SI src2;
- } fmt_21_cmpz;
+ } fmt_cmpz;
struct { /* e.g. div $dr,$sr */
SI dr;
SI sr;
- } fmt_22_div;
+ } fmt_div;
struct { /* e.g. jc $sr */
UBI condbit;
SI sr;
- } fmt_23_jc;
+ } fmt_jc;
struct { /* e.g. jl $sr */
USI pc;
SI sr;
- } fmt_24_jl;
+ } fmt_jl;
struct { /* e.g. jmp $sr */
SI sr;
- } fmt_25_jmp;
+ } fmt_jmp;
struct { /* e.g. ld $dr,@$sr */
SI h_memory_sr;
- SI sr;
- } fmt_26_ld;
+ USI sr;
+ } fmt_ld;
struct { /* e.g. ld $dr,@($slo16,$sr) */
- SI h_memory_add_WI_sr_slo16;
- HI slo16;
+ SI h_memory_add__VM_sr_slo16;
SI sr;
- } fmt_27_ld_d;
+ HI slo16;
+ } fmt_ld_d;
struct { /* e.g. ldb $dr,@$sr */
QI h_memory_sr;
- SI sr;
- } fmt_28_ldb;
+ USI sr;
+ } fmt_ldb;
struct { /* e.g. ldb $dr,@($slo16,$sr) */
- QI h_memory_add_WI_sr_slo16;
- HI slo16;
+ QI h_memory_add__VM_sr_slo16;
SI sr;
- } fmt_29_ldb_d;
+ HI slo16;
+ } fmt_ldb_d;
struct { /* e.g. ldh $dr,@$sr */
HI h_memory_sr;
- SI sr;
- } fmt_30_ldh;
+ USI sr;
+ } fmt_ldh;
struct { /* e.g. ldh $dr,@($slo16,$sr) */
- HI h_memory_add_WI_sr_slo16;
- HI slo16;
+ HI h_memory_add__VM_sr_slo16;
SI sr;
- } fmt_31_ldh_d;
+ HI slo16;
+ } fmt_ldh_d;
struct { /* e.g. ld $dr,@$sr+ */
SI h_memory_sr;
SI sr;
- } fmt_32_ld_plus;
- struct { /* e.g. ld24 $dr,#$uimm24 */
- ADDR uimm24;
- } fmt_33_ld24;
- struct { /* e.g. ldi $dr,#$simm8 */
+ } fmt_ld_plus;
+ struct { /* e.g. ld24 $dr,$uimm24 */
+ USI uimm24;
+ } fmt_ld24;
+ struct { /* e.g. ldi8 $dr,$simm8 */
SI simm8;
- } fmt_34_ldi8;
- struct { /* e.g. ldi $dr,$slo16 */
+ } fmt_ldi8;
+ struct { /* e.g. ldi16 $dr,$hash$slo16 */
HI slo16;
- } fmt_35_ldi16;
+ } fmt_ldi16;
struct { /* e.g. lock $dr,@$sr */
SI h_memory_sr;
- SI sr;
- } fmt_36_lock;
+ USI sr;
+ } fmt_lock;
struct { /* e.g. machi $src1,$src2,$acc */
DI acc;
SI src1;
SI src2;
- } fmt_37_machi_a;
+ } fmt_machi_a;
+ struct { /* e.g. macwhi $src1,$src2 */
+ DI accum;
+ SI src1;
+ SI src2;
+ } fmt_macwhi;
struct { /* e.g. mulhi $src1,$src2,$acc */
SI src1;
SI src2;
- } fmt_38_mulhi_a;
+ } fmt_mulhi_a;
+ struct { /* e.g. mulwhi $src1,$src2 */
+ SI src1;
+ SI src2;
+ } fmt_mulwhi;
struct { /* e.g. mv $dr,$sr */
SI sr;
- } fmt_39_mv;
+ } fmt_mv;
struct { /* e.g. mvfachi $dr,$accs */
DI accs;
- } fmt_40_mvfachi_a;
+ } fmt_mvfachi_a;
struct { /* e.g. mvfc $dr,$scr */
USI scr;
- } fmt_41_mvfc;
+ } fmt_mvfc;
struct { /* e.g. mvtachi $src1,$accs */
DI accs;
SI src1;
- } fmt_42_mvtachi_a;
+ } fmt_mvtachi_a;
struct { /* e.g. mvtc $sr,$dcr */
SI sr;
- } fmt_43_mvtc;
+ } fmt_mvtc;
struct { /* e.g. nop */
int empty;
- } fmt_44_nop;
- struct { /* e.g. rac $accd,$accs,#$imm1 */
+ } fmt_nop;
+ struct { /* e.g. rac $accd,$accs,$imm1 */
DI accs;
USI imm1;
- } fmt_45_rac_dsi;
+ } fmt_rac_dsi;
struct { /* e.g. rte */
- UBI h_bcond_0;
+ UBI h_bsm_0;
UBI h_bie_0;
+ UBI h_bcond_0;
SI h_bpc_0;
- UBI h_bsm_0;
- } fmt_46_rte;
- struct { /* e.g. seth $dr,#$hi16 */
- UHI hi16;
- } fmt_47_seth;
- struct { /* e.g. sll3 $dr,$sr,#$simm16 */
- SI simm16;
+ } fmt_rte;
+ struct { /* e.g. seth $dr,$hash$hi16 */
+ SI hi16;
+ } fmt_seth;
+ struct { /* e.g. sll3 $dr,$sr,$simm16 */
SI sr;
- } fmt_48_sll3;
- struct { /* e.g. slli $dr,#$uimm5 */
+ SI simm16;
+ } fmt_sll3;
+ struct { /* e.g. slli $dr,$uimm5 */
SI dr;
USI uimm5;
- } fmt_49_slli;
+ } fmt_slli;
struct { /* e.g. st $src1,@$src2 */
+ USI src2;
SI src1;
- SI src2;
- } fmt_50_st;
+ } fmt_st;
struct { /* e.g. st $src1,@($slo16,$src2) */
+ SI src2;
HI slo16;
SI src1;
- SI src2;
- } fmt_51_st_d;
+ } fmt_st_d;
struct { /* e.g. stb $src1,@$src2 */
- SI src1;
- SI src2;
- } fmt_52_stb;
+ USI src2;
+ QI src1;
+ } fmt_stb;
struct { /* e.g. stb $src1,@($slo16,$src2) */
- HI slo16;
- SI src1;
SI src2;
- } fmt_53_stb_d;
+ HI slo16;
+ QI src1;
+ } fmt_stb_d;
struct { /* e.g. sth $src1,@$src2 */
- SI src1;
- SI src2;
- } fmt_54_sth;
+ USI src2;
+ HI src1;
+ } fmt_sth;
struct { /* e.g. sth $src1,@($slo16,$src2) */
- HI slo16;
- SI src1;
SI src2;
- } fmt_55_sth_d;
+ HI slo16;
+ HI src1;
+ } fmt_sth_d;
struct { /* e.g. st $src1,@+$src2 */
- SI src1;
SI src2;
- } fmt_56_st_plus;
- struct { /* e.g. trap #$uimm4 */
+ SI src1;
+ } fmt_st_plus;
+ struct { /* e.g. trap $uimm4 */
USI pc;
- SI h_cr_0;
- USI uimm4;
- } fmt_57_trap;
+ USI h_cr_0;
+ SI uimm4;
+ } fmt_trap;
struct { /* e.g. unlock $src1,@$src2 */
UBI h_lock_0;
+ USI src2;
SI src1;
- SI src2;
- } fmt_58_unlock;
+ } fmt_unlock;
struct { /* e.g. satb $dr,$sr */
SI sr;
- } fmt_59_satb;
+ } fmt_satb;
struct { /* e.g. sat $dr,$sr */
UBI condbit;
SI sr;
- } fmt_60_sat;
+ } fmt_sat;
struct { /* e.g. sadd */
- DI h_accums_0;
DI h_accums_1;
- } fmt_61_sadd;
+ DI h_accums_0;
+ } fmt_sadd;
struct { /* e.g. macwu1 $src1,$src2 */
DI h_accums_1;
SI src1;
SI src2;
- } fmt_62_macwu1;
- struct { /* e.g. msblo $src1,$src2 */
- DI accum;
- SI src1;
- SI src2;
- } fmt_63_msblo;
+ } fmt_macwu1;
struct { /* e.g. mulwu1 $src1,$src2 */
SI src1;
SI src2;
- } fmt_64_mulwu1;
+ } fmt_mulwu1;
struct { /* e.g. sc */
UBI condbit;
- } fmt_65_sc;
+ } fmt_sc;
} operands;
};
diff --git a/sim/m32r/extract.c b/sim/m32r/extract.c
index 110c675..93e58ff 100644
--- a/sim/m32r/extract.c
+++ b/sim/m32r/extract.c
@@ -26,6 +26,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#define WANT_CPU_M32R
#include "sim-main.h"
+#include "cgen-ops.h"
#include "cpu-sim.h"
void
@@ -257,7 +258,7 @@ EX_FN_NAME (m32r,fmt_bc8) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF
EXTRACT_FMT_BC8_CODE
/* Record the fields for the semantic handler. */
- FLD (f_disp8) = (pc & -4L) + f_disp8;
+ FLD (f_disp8) = f_disp8;
TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
abuf->length = length;
@@ -274,7 +275,7 @@ EX_FN_NAME (m32r,fmt_bc24) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF
EXTRACT_FMT_BC24_CODE
/* Record the fields for the semantic handler. */
- FLD (f_disp24) = pc + f_disp24;
+ FLD (f_disp24) = f_disp24;
TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
abuf->length = length;
@@ -293,7 +294,7 @@ EX_FN_NAME (m32r,fmt_beq) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF
/* Record the fields for the semantic handler. */
FLD (f_r1) = & CPU (h_gr)[f_r1];
FLD (f_r2) = & CPU (h_gr)[f_r2];
- FLD (f_disp16) = pc + f_disp16;
+ FLD (f_disp16) = f_disp16;
TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_beq", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, (char *) 0));
abuf->length = length;
@@ -319,7 +320,7 @@ EX_FN_NAME (m32r,fmt_beqz) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF
/* Record the fields for the semantic handler. */
FLD (f_r2) = & CPU (h_gr)[f_r2];
- FLD (f_disp16) = pc + f_disp16;
+ FLD (f_disp16) = f_disp16;
TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_beqz", "src2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, (char *) 0));
abuf->length = length;
@@ -344,7 +345,7 @@ EX_FN_NAME (m32r,fmt_bl8) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF
EXTRACT_FMT_BL8_CODE
/* Record the fields for the semantic handler. */
- FLD (f_disp8) = (pc & -4L) + f_disp8;
+ FLD (f_disp8) = f_disp8;
TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
abuf->length = length;
@@ -369,7 +370,7 @@ EX_FN_NAME (m32r,fmt_bl24) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF
EXTRACT_FMT_BL24_CODE
/* Record the fields for the semantic handler. */
- FLD (f_disp24) = pc + f_disp24;
+ FLD (f_disp24) = f_disp24;
TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
abuf->length = length;
@@ -394,7 +395,7 @@ EX_FN_NAME (m32r,fmt_bra8) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF
EXTRACT_FMT_BRA8_CODE
/* Record the fields for the semantic handler. */
- FLD (f_disp8) = (pc & -4L) + f_disp8;
+ FLD (f_disp8) = f_disp8;
TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
abuf->length = length;
@@ -411,7 +412,7 @@ EX_FN_NAME (m32r,fmt_bra24) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBU
EXTRACT_FMT_BRA24_CODE
/* Record the fields for the semantic handler. */
- FLD (f_disp24) = pc + f_disp24;
+ FLD (f_disp24) = f_disp24;
TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
abuf->length = length;
diff --git a/sim/m32r/readx.c b/sim/m32r/readx.c
index fb33ba8..5896486 100644
--- a/sim/m32r/readx.c
+++ b/sim/m32r/readx.c
@@ -279,7 +279,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
EXTRACT_FMT_BC8_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (condbit) = CPU (h_cond);
- OPRND (disp8) = (pc & -4L) + f_disp8;
+ OPRND (disp8) = f_disp8;
#undef OPRND
}
BREAK (read);
@@ -291,7 +291,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
EXTRACT_FMT_BC24_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (condbit) = CPU (h_cond);
- OPRND (disp24) = pc + f_disp24;
+ OPRND (disp24) = f_disp24;
#undef OPRND
}
BREAK (read);
@@ -304,7 +304,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
/* Fetch the input operands for the semantic handler. */
OPRND (src1) = CPU (h_gr[f_r1]);
OPRND (src2) = CPU (h_gr[f_r2]);
- OPRND (disp16) = pc + f_disp16;
+ OPRND (disp16) = f_disp16;
#undef OPRND
}
BREAK (read);
@@ -316,7 +316,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
EXTRACT_FMT_BEQZ_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (src2) = CPU (h_gr[f_r2]);
- OPRND (disp16) = pc + f_disp16;
+ OPRND (disp16) = f_disp16;
#undef OPRND
}
BREAK (read);
@@ -328,7 +328,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
EXTRACT_FMT_BL8_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (pc) = CPU (h_pc);
- OPRND (disp8) = (pc & -4L) + f_disp8;
+ OPRND (disp8) = f_disp8;
#undef OPRND
}
BREAK (read);
@@ -340,7 +340,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
EXTRACT_FMT_BL24_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (pc) = CPU (h_pc);
- OPRND (disp24) = pc + f_disp24;
+ OPRND (disp24) = f_disp24;
#undef OPRND
}
BREAK (read);
@@ -353,7 +353,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
/* Fetch the input operands for the semantic handler. */
OPRND (condbit) = CPU (h_cond);
OPRND (pc) = CPU (h_pc);
- OPRND (disp8) = (pc & -4L) + f_disp8;
+ OPRND (disp8) = f_disp8;
#undef OPRND
}
BREAK (read);
@@ -366,7 +366,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
/* Fetch the input operands for the semantic handler. */
OPRND (condbit) = CPU (h_cond);
OPRND (pc) = CPU (h_pc);
- OPRND (disp24) = pc + f_disp24;
+ OPRND (disp24) = f_disp24;
#undef OPRND
}
BREAK (read);
@@ -377,7 +377,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
EXTRACT_FMT_BRA8_VARS /* f-op1 f-r1 f-disp8 */
EXTRACT_FMT_BRA8_CODE
/* Fetch the input operands for the semantic handler. */
- OPRND (disp8) = (pc & -4L) + f_disp8;
+ OPRND (disp8) = f_disp8;
#undef OPRND
}
BREAK (read);
@@ -388,7 +388,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
EXTRACT_FMT_BRA24_VARS /* f-op1 f-r1 f-disp24 */
EXTRACT_FMT_BRA24_CODE
/* Fetch the input operands for the semantic handler. */
- OPRND (disp24) = pc + f_disp24;
+ OPRND (disp24) = f_disp24;
#undef OPRND
}
BREAK (read);
diff --git a/sim/m32r/semx.c b/sim/m32r/semx.c
index e1e621b..7dd1358 100644
--- a/sim/m32r/semx.c
+++ b/sim/m32r/semx.c
@@ -44,6 +44,7 @@ SEM_FN_NAME (m32rx,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
#define OPRND(f) par_exec->operands.fmt_add.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_ADD_CODE
@@ -77,6 +78,7 @@ SEM_FN_NAME (m32rx,add3) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_add3.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+ CIA pc = PC;
EXTRACT_FMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_ADD3_CODE
@@ -110,6 +112,7 @@ SEM_FN_NAME (m32rx,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
#define OPRND(f) par_exec->operands.fmt_add.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_ADD_CODE
@@ -143,6 +146,7 @@ SEM_FN_NAME (m32rx,and3) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_and3.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+ CIA pc = PC;
EXTRACT_FMT_AND3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
EXTRACT_FMT_AND3_CODE
@@ -176,6 +180,7 @@ SEM_FN_NAME (m32rx,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec
#define OPRND(f) par_exec->operands.fmt_add.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_ADD_CODE
@@ -209,6 +214,7 @@ SEM_FN_NAME (m32rx,or3) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
#define OPRND(f) par_exec->operands.fmt_or3.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+ CIA pc = PC;
EXTRACT_FMT_OR3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
EXTRACT_FMT_OR3_CODE
@@ -242,6 +248,7 @@ SEM_FN_NAME (m32rx,xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
#define OPRND(f) par_exec->operands.fmt_add.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_ADD_CODE
@@ -275,6 +282,7 @@ SEM_FN_NAME (m32rx,xor3) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_and3.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+ CIA pc = PC;
EXTRACT_FMT_AND3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
EXTRACT_FMT_AND3_CODE
@@ -308,6 +316,7 @@ SEM_FN_NAME (m32rx,addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_addi.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_ADDI_VARS /* f-op1 f-r1 f-simm8 */
EXTRACT_FMT_ADDI_CODE
@@ -341,6 +350,7 @@ SEM_FN_NAME (m32rx,addv) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_addv.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_ADDV_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_ADDV_CODE
@@ -384,6 +394,7 @@ SEM_FN_NAME (m32rx,addv3) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_e
#define OPRND(f) par_exec->operands.fmt_addv3.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+ CIA pc = PC;
EXTRACT_FMT_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_ADDV3_CODE
@@ -427,6 +438,7 @@ SEM_FN_NAME (m32rx,addx) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_addx.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_ADDX_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_ADDX_CODE
@@ -471,6 +483,7 @@ SEM_FN_NAME (m32rx,bc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
int taken_p = 0;
+ CIA pc = PC;
EXTRACT_FMT_BC8_VARS /* f-op1 f-r1 f-disp8 */
EXTRACT_FMT_BC8_CODE
@@ -506,6 +519,7 @@ SEM_FN_NAME (m32rx,bc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
int taken_p = 0;
+ CIA pc = PC;
EXTRACT_FMT_BC24_VARS /* f-op1 f-r1 f-disp24 */
EXTRACT_FMT_BC24_CODE
@@ -541,6 +555,7 @@ SEM_FN_NAME (m32rx,beq) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
int taken_p = 0;
+ CIA pc = PC;
EXTRACT_FMT_BEQ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
EXTRACT_FMT_BEQ_CODE
@@ -577,6 +592,7 @@ SEM_FN_NAME (m32rx,beqz) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
int taken_p = 0;
+ CIA pc = PC;
EXTRACT_FMT_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
EXTRACT_FMT_BEQZ_CODE
@@ -613,6 +629,7 @@ SEM_FN_NAME (m32rx,bgez) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
int taken_p = 0;
+ CIA pc = PC;
EXTRACT_FMT_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
EXTRACT_FMT_BEQZ_CODE
@@ -649,6 +666,7 @@ SEM_FN_NAME (m32rx,bgtz) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
int taken_p = 0;
+ CIA pc = PC;
EXTRACT_FMT_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
EXTRACT_FMT_BEQZ_CODE
@@ -685,6 +703,7 @@ SEM_FN_NAME (m32rx,blez) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
int taken_p = 0;
+ CIA pc = PC;
EXTRACT_FMT_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
EXTRACT_FMT_BEQZ_CODE
@@ -721,6 +740,7 @@ SEM_FN_NAME (m32rx,bltz) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
int taken_p = 0;
+ CIA pc = PC;
EXTRACT_FMT_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
EXTRACT_FMT_BEQZ_CODE
@@ -757,6 +777,7 @@ SEM_FN_NAME (m32rx,bnez) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
int taken_p = 0;
+ CIA pc = PC;
EXTRACT_FMT_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
EXTRACT_FMT_BEQZ_CODE
@@ -793,6 +814,7 @@ SEM_FN_NAME (m32rx,bl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
int taken_p = 0;
+ CIA pc = PC;
EXTRACT_FMT_BL8_VARS /* f-op1 f-r1 f-disp8 */
EXTRACT_FMT_BL8_CODE
@@ -834,6 +856,7 @@ SEM_FN_NAME (m32rx,bl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
int taken_p = 0;
+ CIA pc = PC;
EXTRACT_FMT_BL24_VARS /* f-op1 f-r1 f-disp24 */
EXTRACT_FMT_BL24_CODE
@@ -875,6 +898,7 @@ SEM_FN_NAME (m32rx,bcl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
int taken_p = 0;
+ CIA pc = PC;
EXTRACT_FMT_BCL8_VARS /* f-op1 f-r1 f-disp8 */
EXTRACT_FMT_BCL8_CODE
@@ -918,6 +942,7 @@ SEM_FN_NAME (m32rx,bcl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_e
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
int taken_p = 0;
+ CIA pc = PC;
EXTRACT_FMT_BCL24_VARS /* f-op1 f-r1 f-disp24 */
EXTRACT_FMT_BCL24_CODE
@@ -961,6 +986,7 @@ SEM_FN_NAME (m32rx,bnc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
int taken_p = 0;
+ CIA pc = PC;
EXTRACT_FMT_BC8_VARS /* f-op1 f-r1 f-disp8 */
EXTRACT_FMT_BC8_CODE
@@ -996,6 +1022,7 @@ SEM_FN_NAME (m32rx,bnc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_e
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
int taken_p = 0;
+ CIA pc = PC;
EXTRACT_FMT_BC24_VARS /* f-op1 f-r1 f-disp24 */
EXTRACT_FMT_BC24_CODE
@@ -1031,6 +1058,7 @@ SEM_FN_NAME (m32rx,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
int taken_p = 0;
+ CIA pc = PC;
EXTRACT_FMT_BEQ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
EXTRACT_FMT_BEQ_CODE
@@ -1067,6 +1095,7 @@ SEM_FN_NAME (m32rx,bra8) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
int taken_p = 0;
+ CIA pc = PC;
EXTRACT_FMT_BRA8_VARS /* f-op1 f-r1 f-disp8 */
EXTRACT_FMT_BRA8_CODE
@@ -1100,6 +1129,7 @@ SEM_FN_NAME (m32rx,bra24) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_e
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
int taken_p = 0;
+ CIA pc = PC;
EXTRACT_FMT_BRA24_VARS /* f-op1 f-r1 f-disp24 */
EXTRACT_FMT_BRA24_CODE
@@ -1133,6 +1163,7 @@ SEM_FN_NAME (m32rx,bncl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_e
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
int taken_p = 0;
+ CIA pc = PC;
EXTRACT_FMT_BCL8_VARS /* f-op1 f-r1 f-disp8 */
EXTRACT_FMT_BCL8_CODE
@@ -1176,6 +1207,7 @@ SEM_FN_NAME (m32rx,bncl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
int taken_p = 0;
+ CIA pc = PC;
EXTRACT_FMT_BCL24_VARS /* f-op1 f-r1 f-disp24 */
EXTRACT_FMT_BCL24_CODE
@@ -1218,6 +1250,7 @@ SEM_FN_NAME (m32rx,cmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
#define OPRND(f) par_exec->operands.fmt_cmp.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_CMP_CODE
@@ -1250,6 +1283,7 @@ SEM_FN_NAME (m32rx,cmpi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_cmpi.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+ CIA pc = PC;
EXTRACT_FMT_CMPI_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_CMPI_CODE
@@ -1282,6 +1316,7 @@ SEM_FN_NAME (m32rx,cmpu) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_cmp.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_CMP_CODE
@@ -1314,6 +1349,7 @@ SEM_FN_NAME (m32rx,cmpui) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_e
#define OPRND(f) par_exec->operands.fmt_cmpi.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+ CIA pc = PC;
EXTRACT_FMT_CMPI_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_CMPI_CODE
@@ -1346,6 +1382,7 @@ SEM_FN_NAME (m32rx,cmpeq) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_e
#define OPRND(f) par_exec->operands.fmt_cmp.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_CMP_CODE
@@ -1378,6 +1415,7 @@ SEM_FN_NAME (m32rx,cmpz) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_cmpz.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_CMPZ_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_CMPZ_CODE
@@ -1410,6 +1448,7 @@ SEM_FN_NAME (m32rx,div) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
#define OPRND(f) par_exec->operands.fmt_div.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+ CIA pc = PC;
EXTRACT_FMT_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_DIV_CODE
@@ -1445,6 +1484,7 @@ SEM_FN_NAME (m32rx,divu) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_div.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+ CIA pc = PC;
EXTRACT_FMT_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_DIV_CODE
@@ -1480,6 +1520,7 @@ SEM_FN_NAME (m32rx,rem) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
#define OPRND(f) par_exec->operands.fmt_div.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+ CIA pc = PC;
EXTRACT_FMT_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_DIV_CODE
@@ -1515,6 +1556,7 @@ SEM_FN_NAME (m32rx,remu) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_div.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+ CIA pc = PC;
EXTRACT_FMT_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_DIV_CODE
@@ -1550,6 +1592,7 @@ SEM_FN_NAME (m32rx,divh) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_div.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+ CIA pc = PC;
EXTRACT_FMT_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_DIV_CODE
@@ -1586,6 +1629,7 @@ SEM_FN_NAME (m32rx,jc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
int taken_p = 0;
+ CIA pc = PC;
EXTRACT_FMT_JC_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_JC_CODE
@@ -1622,6 +1666,7 @@ SEM_FN_NAME (m32rx,jnc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
int taken_p = 0;
+ CIA pc = PC;
EXTRACT_FMT_JC_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_JC_CODE
@@ -1658,6 +1703,7 @@ SEM_FN_NAME (m32rx,jl) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
int taken_p = 0;
+ CIA pc = PC;
EXTRACT_FMT_JL_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_JL_CODE
@@ -1703,6 +1749,7 @@ SEM_FN_NAME (m32rx,jmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
int taken_p = 0;
+ CIA pc = PC;
EXTRACT_FMT_JMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_JMP_CODE
@@ -1736,6 +1783,7 @@ SEM_FN_NAME (m32rx,ld) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec
#define OPRND(f) par_exec->operands.fmt_ld.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_LD_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_LD_CODE
@@ -1769,6 +1817,7 @@ SEM_FN_NAME (m32rx,ld_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_ld_d.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+ CIA pc = PC;
EXTRACT_FMT_LD_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_LD_D_CODE
@@ -1802,6 +1851,7 @@ SEM_FN_NAME (m32rx,ldb) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
#define OPRND(f) par_exec->operands.fmt_ldb.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_LDB_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_LDB_CODE
@@ -1835,6 +1885,7 @@ SEM_FN_NAME (m32rx,ldb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_e
#define OPRND(f) par_exec->operands.fmt_ldb_d.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+ CIA pc = PC;
EXTRACT_FMT_LDB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_LDB_D_CODE
@@ -1868,6 +1919,7 @@ SEM_FN_NAME (m32rx,ldh) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
#define OPRND(f) par_exec->operands.fmt_ldh.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_LDH_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_LDH_CODE
@@ -1901,6 +1953,7 @@ SEM_FN_NAME (m32rx,ldh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_e
#define OPRND(f) par_exec->operands.fmt_ldh_d.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+ CIA pc = PC;
EXTRACT_FMT_LDH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_LDH_D_CODE
@@ -1934,6 +1987,7 @@ SEM_FN_NAME (m32rx,ldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_ldb.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_LDB_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_LDB_CODE
@@ -1967,6 +2021,7 @@ SEM_FN_NAME (m32rx,ldub_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_
#define OPRND(f) par_exec->operands.fmt_ldb_d.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+ CIA pc = PC;
EXTRACT_FMT_LDB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_LDB_D_CODE
@@ -2000,6 +2055,7 @@ SEM_FN_NAME (m32rx,lduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_ldh.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_LDH_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_LDH_CODE
@@ -2033,6 +2089,7 @@ SEM_FN_NAME (m32rx,lduh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_
#define OPRND(f) par_exec->operands.fmt_ldh_d.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+ CIA pc = PC;
EXTRACT_FMT_LDH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_LDH_D_CODE
@@ -2066,6 +2123,7 @@ SEM_FN_NAME (m32rx,ld_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par
#define OPRND(f) par_exec->operands.fmt_ld_plus.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_LD_PLUS_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_LD_PLUS_CODE
@@ -2109,6 +2167,7 @@ SEM_FN_NAME (m32rx,ld24) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_ld24.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+ CIA pc = PC;
EXTRACT_FMT_LD24_VARS /* f-op1 f-r1 f-uimm24 */
EXTRACT_FMT_LD24_CODE
@@ -2141,6 +2200,7 @@ SEM_FN_NAME (m32rx,ldi8) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_ldi8.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_LDI8_VARS /* f-op1 f-r1 f-simm8 */
EXTRACT_FMT_LDI8_CODE
@@ -2173,6 +2233,7 @@ SEM_FN_NAME (m32rx,ldi16) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_e
#define OPRND(f) par_exec->operands.fmt_ldi16.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+ CIA pc = PC;
EXTRACT_FMT_LDI16_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_LDI16_CODE
@@ -2205,6 +2266,7 @@ SEM_FN_NAME (m32rx,lock) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_lock.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_LOCK_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_LOCK_CODE
@@ -2245,6 +2307,7 @@ SEM_FN_NAME (m32rx,machi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par
#define OPRND(f) par_exec->operands.fmt_machi_a.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_MACHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
EXTRACT_FMT_MACHI_A_CODE
@@ -2277,6 +2340,7 @@ SEM_FN_NAME (m32rx,maclo_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par
#define OPRND(f) par_exec->operands.fmt_machi_a.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_MACHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
EXTRACT_FMT_MACHI_A_CODE
@@ -2309,6 +2373,7 @@ SEM_FN_NAME (m32rx,macwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_
#define OPRND(f) par_exec->operands.fmt_macwhi.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_MACWHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_MACWHI_CODE
@@ -2341,6 +2406,7 @@ SEM_FN_NAME (m32rx,macwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_
#define OPRND(f) par_exec->operands.fmt_macwhi.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_MACWHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_MACWHI_CODE
@@ -2373,6 +2439,7 @@ SEM_FN_NAME (m32rx,mul) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
#define OPRND(f) par_exec->operands.fmt_add.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_ADD_CODE
@@ -2406,6 +2473,7 @@ SEM_FN_NAME (m32rx,mulhi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par
#define OPRND(f) par_exec->operands.fmt_mulhi_a.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_MULHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
EXTRACT_FMT_MULHI_A_CODE
@@ -2438,6 +2506,7 @@ SEM_FN_NAME (m32rx,mullo_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par
#define OPRND(f) par_exec->operands.fmt_mulhi_a.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_MULHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
EXTRACT_FMT_MULHI_A_CODE
@@ -2470,6 +2539,7 @@ SEM_FN_NAME (m32rx,mulwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_
#define OPRND(f) par_exec->operands.fmt_mulwhi.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_MULWHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_MULWHI_CODE
@@ -2502,6 +2572,7 @@ SEM_FN_NAME (m32rx,mulwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_
#define OPRND(f) par_exec->operands.fmt_mulwhi.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_MULWHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_MULWHI_CODE
@@ -2534,6 +2605,7 @@ SEM_FN_NAME (m32rx,mv) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec
#define OPRND(f) par_exec->operands.fmt_mv.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_MV_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_MV_CODE
@@ -2567,6 +2639,7 @@ SEM_FN_NAME (m32rx,mvfachi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *p
#define OPRND(f) par_exec->operands.fmt_mvfachi_a.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_MVFACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
EXTRACT_FMT_MVFACHI_A_CODE
@@ -2599,6 +2672,7 @@ SEM_FN_NAME (m32rx,mvfaclo_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *p
#define OPRND(f) par_exec->operands.fmt_mvfachi_a.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_MVFACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
EXTRACT_FMT_MVFACHI_A_CODE
@@ -2631,6 +2705,7 @@ SEM_FN_NAME (m32rx,mvfacmi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *p
#define OPRND(f) par_exec->operands.fmt_mvfachi_a.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_MVFACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
EXTRACT_FMT_MVFACHI_A_CODE
@@ -2663,6 +2738,7 @@ SEM_FN_NAME (m32rx,mvfc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_mvfc.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_MVFC_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_MVFC_CODE
@@ -2695,6 +2771,7 @@ SEM_FN_NAME (m32rx,mvtachi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *p
#define OPRND(f) par_exec->operands.fmt_mvtachi_a.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_MVTACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
EXTRACT_FMT_MVTACHI_A_CODE
@@ -2727,6 +2804,7 @@ SEM_FN_NAME (m32rx,mvtaclo_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *p
#define OPRND(f) par_exec->operands.fmt_mvtachi_a.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_MVTACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
EXTRACT_FMT_MVTACHI_A_CODE
@@ -2759,6 +2837,7 @@ SEM_FN_NAME (m32rx,mvtc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_mvtc.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_MVTC_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_MVTC_CODE
@@ -2791,6 +2870,7 @@ SEM_FN_NAME (m32rx,neg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
#define OPRND(f) par_exec->operands.fmt_mv.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_MV_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_MV_CODE
@@ -2824,6 +2904,7 @@ SEM_FN_NAME (m32rx,nop) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
#define OPRND(f) par_exec->operands.fmt_nop.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_NOP_CODE
@@ -2851,6 +2932,7 @@ SEM_FN_NAME (m32rx,not) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
#define OPRND(f) par_exec->operands.fmt_mv.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_MV_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_MV_CODE
@@ -2884,6 +2966,7 @@ SEM_FN_NAME (m32rx,rac_dsi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par
#define OPRND(f) par_exec->operands.fmt_rac_dsi.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_RAC_DSI_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */
EXTRACT_FMT_RAC_DSI_CODE
@@ -2920,6 +3003,7 @@ SEM_FN_NAME (m32rx,rach_dsi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *pa
#define OPRND(f) par_exec->operands.fmt_rac_dsi.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_RAC_DSI_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */
EXTRACT_FMT_RAC_DSI_CODE
@@ -2957,6 +3041,7 @@ SEM_FN_NAME (m32rx,rte) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
int taken_p = 0;
+ CIA pc = PC;
EXTRACT_FMT_RTE_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_RTE_CODE
@@ -3006,6 +3091,7 @@ SEM_FN_NAME (m32rx,seth) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_seth.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+ CIA pc = PC;
EXTRACT_FMT_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */
EXTRACT_FMT_SETH_CODE
@@ -3038,6 +3124,7 @@ SEM_FN_NAME (m32rx,sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
#define OPRND(f) par_exec->operands.fmt_add.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_ADD_CODE
@@ -3071,6 +3158,7 @@ SEM_FN_NAME (m32rx,sll3) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_sll3.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+ CIA pc = PC;
EXTRACT_FMT_SLL3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_SLL3_CODE
@@ -3104,6 +3192,7 @@ SEM_FN_NAME (m32rx,slli) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_slli.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
EXTRACT_FMT_SLLI_CODE
@@ -3137,6 +3226,7 @@ SEM_FN_NAME (m32rx,sra) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
#define OPRND(f) par_exec->operands.fmt_add.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_ADD_CODE
@@ -3170,6 +3260,7 @@ SEM_FN_NAME (m32rx,sra3) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_sll3.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+ CIA pc = PC;
EXTRACT_FMT_SLL3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_SLL3_CODE
@@ -3203,6 +3294,7 @@ SEM_FN_NAME (m32rx,srai) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_slli.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
EXTRACT_FMT_SLLI_CODE
@@ -3236,6 +3328,7 @@ SEM_FN_NAME (m32rx,srl) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
#define OPRND(f) par_exec->operands.fmt_add.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_ADD_CODE
@@ -3269,6 +3362,7 @@ SEM_FN_NAME (m32rx,srl3) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_sll3.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+ CIA pc = PC;
EXTRACT_FMT_SLL3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_SLL3_CODE
@@ -3302,6 +3396,7 @@ SEM_FN_NAME (m32rx,srli) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_slli.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
EXTRACT_FMT_SLLI_CODE
@@ -3335,6 +3430,7 @@ SEM_FN_NAME (m32rx,st) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec
#define OPRND(f) par_exec->operands.fmt_st.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_ST_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_ST_CODE
@@ -3367,6 +3463,7 @@ SEM_FN_NAME (m32rx,st_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_st_d.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+ CIA pc = PC;
EXTRACT_FMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_ST_D_CODE
@@ -3399,6 +3496,7 @@ SEM_FN_NAME (m32rx,stb) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
#define OPRND(f) par_exec->operands.fmt_stb.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_STB_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_STB_CODE
@@ -3431,6 +3529,7 @@ SEM_FN_NAME (m32rx,stb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_e
#define OPRND(f) par_exec->operands.fmt_stb_d.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+ CIA pc = PC;
EXTRACT_FMT_STB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_STB_D_CODE
@@ -3463,6 +3562,7 @@ SEM_FN_NAME (m32rx,sth) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
#define OPRND(f) par_exec->operands.fmt_sth.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_STH_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_STH_CODE
@@ -3495,6 +3595,7 @@ SEM_FN_NAME (m32rx,sth_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_e
#define OPRND(f) par_exec->operands.fmt_sth_d.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+ CIA pc = PC;
EXTRACT_FMT_STH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_STH_D_CODE
@@ -3527,6 +3628,7 @@ SEM_FN_NAME (m32rx,st_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par
#define OPRND(f) par_exec->operands.fmt_st_plus.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_ST_PLUS_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_ST_PLUS_CODE
@@ -3569,6 +3671,7 @@ SEM_FN_NAME (m32rx,st_minus) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *pa
#define OPRND(f) par_exec->operands.fmt_st_plus.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_ST_PLUS_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_ST_PLUS_CODE
@@ -3611,6 +3714,7 @@ SEM_FN_NAME (m32rx,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
#define OPRND(f) par_exec->operands.fmt_add.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_ADD_CODE
@@ -3644,6 +3748,7 @@ SEM_FN_NAME (m32rx,subv) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_addv.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_ADDV_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_ADDV_CODE
@@ -3687,6 +3792,7 @@ SEM_FN_NAME (m32rx,subx) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_addx.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_ADDX_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_ADDX_CODE
@@ -3731,6 +3837,7 @@ SEM_FN_NAME (m32rx,trap) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
int taken_p = 0;
+ CIA pc = PC;
EXTRACT_FMT_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
EXTRACT_FMT_TRAP_CODE
@@ -3775,6 +3882,7 @@ SEM_FN_NAME (m32rx,unlock) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_
#define OPRND(f) par_exec->operands.fmt_unlock.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_UNLOCK_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_UNLOCK_CODE
@@ -3816,6 +3924,7 @@ SEM_FN_NAME (m32rx,satb) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_satb.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+ CIA pc = PC;
EXTRACT_FMT_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
EXTRACT_FMT_SATB_CODE
@@ -3849,6 +3958,7 @@ SEM_FN_NAME (m32rx,sath) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_satb.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+ CIA pc = PC;
EXTRACT_FMT_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
EXTRACT_FMT_SATB_CODE
@@ -3882,6 +3992,7 @@ SEM_FN_NAME (m32rx,sat) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
#define OPRND(f) par_exec->operands.fmt_sat.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+ CIA pc = PC;
EXTRACT_FMT_SAT_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
EXTRACT_FMT_SAT_CODE
@@ -3915,6 +4026,7 @@ SEM_FN_NAME (m32rx,pcmpbz) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_
#define OPRND(f) par_exec->operands.fmt_cmpz.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_CMPZ_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_CMPZ_CODE
@@ -3947,6 +4059,7 @@ SEM_FN_NAME (m32rx,sadd) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
#define OPRND(f) par_exec->operands.fmt_sadd.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_SADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_SADD_CODE
@@ -3978,6 +4091,7 @@ SEM_FN_NAME (m32rx,macwu1) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_
#define OPRND(f) par_exec->operands.fmt_macwu1.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_MACWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_MACWU1_CODE
@@ -4010,6 +4124,7 @@ SEM_FN_NAME (m32rx,msblo) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_e
#define OPRND(f) par_exec->operands.fmt_macwhi.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_MACWHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_MACWHI_CODE
@@ -4042,6 +4157,7 @@ SEM_FN_NAME (m32rx,mulwu1) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_
#define OPRND(f) par_exec->operands.fmt_mulwu1.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_MULWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_MULWU1_CODE
@@ -4074,6 +4190,7 @@ SEM_FN_NAME (m32rx,maclh1) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_
#define OPRND(f) par_exec->operands.fmt_macwu1.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_MACWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_MACWU1_CODE
@@ -4106,6 +4223,7 @@ SEM_FN_NAME (m32rx,sc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec
#define OPRND(f) par_exec->operands.fmt_sc.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_SC_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_SC_CODE
@@ -4135,6 +4253,7 @@ SEM_FN_NAME (m32rx,snc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
#define OPRND(f) par_exec->operands.fmt_sc.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+ CIA pc = PC;
EXTRACT_FMT_SC_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_SC_CODE
generated by cgit v1.1 at 2024-11-03 19:49:03 +0000