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| author | Joern Rennecke <joern.rennecke@embecosm.com> | 1997-09-02 22:43:55 +0000 |
|---|---|---|
| committer | Joern Rennecke <joern.rennecke@embecosm.com> | 1997-09-02 22:43:55 +0000 |
| commit | 552c6220e0bf1173ccf939170835dcd505282a1d (patch) | |
| tree | d204025d86b0dd545bed8ecbe00db35e989f8ec9 /sim | |
| parent | 1f302a3bd9dbeacd407ba6e454db1f72c5bb3ba4 (diff) | |
| download | gdb-552c6220e0bf1173ccf939170835dcd505282a1d.zip gdb-552c6220e0bf1173ccf939170835dcd505282a1d.tar.gz gdb-552c6220e0bf1173ccf939170835dcd505282a1d.tar.bz2 | |
Comment typo fix.
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/sh/interp.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sim/sh/interp.c b/sim/sh/interp.c index ce8c8d1..ff40f49 100644 --- a/sim/sh/interp.c +++ b/sim/sh/interp.c @@ -283,7 +283,7 @@ special_address (addr, bits_written, data) { if ((unsigned) addr >> 24 == 0xf0 && bits_written == 32 && (data & 1) == 0) /* This invalidates (if not associative) or might invalidate - (if assiciative) an instruction cache line. This is used for + (if associative) an instruction cache line. This is used for trampolines. Since we don't simulate the cache, this is a no-op as far as the simulator is concerned. */ return 1; |