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authorJason Molenda <jmolenda@apple.com>1999-11-17 02:31:06 +0000
committerJason Molenda <jmolenda@apple.com>1999-11-17 02:31:06 +0000
commit4ce44c668ddc0a909c3f081d98c68bea90a93af9 (patch)
treecf330e250ee02bf77884cb91292faaaa849c5837 /sim
parent2daf4fd8960262b76e597427e2e230b3fe6470b3 (diff)
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import gdb-1999-11-16 snapshot
Diffstat (limited to 'sim')
-rw-r--r--sim/d10v/ChangeLog83
-rw-r--r--sim/d10v/d10v_sim.h63
-rw-r--r--sim/d10v/interp.c845
-rw-r--r--sim/d10v/simops.c28
-rw-r--r--sim/mips/ChangeLog5
-rw-r--r--sim/mips/interp.c9
-rw-r--r--sim/testsuite/d10v-elf/ChangeLog9
-rw-r--r--sim/testsuite/d10v-elf/t-mvtc.s56
8 files changed, 780 insertions, 318 deletions
diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog
index 0be82fa..449e256 100644
--- a/sim/d10v/ChangeLog
+++ b/sim/d10v/ChangeLog
@@ -1,7 +1,88 @@
+Fri Oct 29 18:34:28 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * simops.c (move_to_cr): Don't allow user to set PSW.DM in either
+ DPSW and BPSW.
+
+Thu Oct 28 01:26:18 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * simops.c (OP_5F20): Use SET_HW_PSW when updating PSW.
+ (PSW_HW_MASK): Declare.
+
+ * d10v_sim.h (move_to_cr): Add ``psw_hw_p'' parameter.
+ (SET_CREG, SET_PSW_BIT): Update.
+ (SET_HW_CREG, SET_HW_PSW): Define.
+
+Sun Oct 24 21:38:04 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_d10v_translate_dmap_addr): Fix extraction of IOSP
+ for DMAP3.
+
+Sun Oct 24 16:04:16 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_d10v_translate_addr): New function.
+ (xfer_mem): Rewrite. Use sim_d10v_translate_addr.
+ (map_memory): Make INLINE.
+
+Sun Oct 24 13:45:19 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_d10v_translate_dmap_addr): New function.
+ (dmem_addr): Rewrite. Use sim_d10v_translate_dmap_addr. Change
+ offset parameter to type uint16.
+ * d10v_sim.h (dmem_addr): Update declaration.
+
+Sun Oct 24 13:07:31 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (imap_register, set_imap_register, dmap_register,
+ set_imap_register): Use map_memory.
+ (DMAP): Update.
+ (sim_create_inferior): Initialize all DMAP registers. NOTE that
+ DMAP2, in internal memory mode, is set to 0x0000 and NOT
+ 0x2000. This is consistent with the older d10v boards.
+
+Sun Oct 24 11:22:12 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_d10v_translate_imap_addr): New function.
+ (imem_addr): Rewrite. Use sim_d10v_translate_imap_addr.
+ (last_from, last_to): Declare.
+
+Sun Oct 24 01:21:56 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * d10v_sim.h (struct d10v_memory): Define. Support very long
+ memories.
+ (struct _state): Replace imem, dmem and umem by mem.
+ (IMAP_BLOCK_SIZE, DMAP_BLOCK_SIZE, SEGMENT_SIZE, IMEM_SEGMENTS,
+ DMEM_SEGMENTS, UMEM_SEGMENTS): Define.
+
+ * interp.c (map_memory): New function.
+ (sim_size, xfer_memory, imem_addr, dmem_addr): Update.
+ (UMEM_SEGMENTS): Moveed to "d10v_sim.h".
+ (IMEM_SIZEDMEM_SIZE): Delete.
+
+Sat Oct 23 20:06:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c: Include "sim-d10v.h".
+ (imap_register, set_imap_register, dmap_register,
+ set_dmap_register, spi_register, spu_register, set_spi_register,
+ set_spu_register): New functions.
+ (sim_create_inferior): Update.
+ (sim_fetch_register, sim_store_register): Rewrite. Use enums
+ defined in sim-d10v.h.
+
+ * d10v_sim.h (DEBUG_MEMORY): Define.
+ (IMAP0, IMAP1, DMAP, SET_IMAP0, SET_IMAP1, SET_DMAP): Delete.
+
+Sat Oct 23 18:41:18 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_open): Allow a debug value to be passed to the -t
+ option.
+ (lookup_hash): Don't exit on an illegal instruction.
+ (do_long, do_2_short, do_parallel): Check for failed instruction
+ lookup.
+
Mon Oct 18 18:03:24 MDT 1999 Diego Novillo <dnovillo@cygnus.com>
* simops.c (OP_3220): Fix trace output for illegal accumulator
- message.
+ message.
1999-09-14 Nick Clifton <nickc@cygnus.com>
diff --git a/sim/d10v/d10v_sim.h b/sim/d10v/d10v_sim.h
index ca7e02e..130aed9 100644
--- a/sim/d10v/d10v_sim.h
+++ b/sim/d10v/d10v_sim.h
@@ -13,6 +13,7 @@
#define DEBUG_MEMSIZE 0x00000008
#define DEBUG_INSTRUCTION 0x00000010
#define DEBUG_TRAP 0x00000020
+#define DEBUG_MEMORY 0x00000040
#ifndef DEBUG
#define DEBUG (DEBUG_TRACE | DEBUG_VALUES | DEBUG_LINE_NUMBER)
@@ -197,6 +198,37 @@ enum {
} \
while (0)
+/* d10v memory: There are three separate d10v memory regions IMEM,
+ UMEM and DMEM. The IMEM and DMEM are further broken down into
+ blocks (very like VM pages). */
+
+enum
+{
+ IMAP_BLOCK_SIZE = 0x20000,
+ DMAP_BLOCK_SIZE = 0x4000,
+};
+
+/* Implement the three memory regions using sparse arrays. Allocate
+ memory using ``segments''. A segment must be at least as large as
+ a BLOCK - ensures that an access that doesn't cross a block
+ boundary can't cross a segment boundary */
+
+enum
+{
+ SEGMENT_SIZE = 0x20000, /* 128KB - MAX(IMAP_BLOCK_SIZE,DMAP_BLOCK_SIZE) */
+ IMEM_SEGMENTS = 8, /* 1MB */
+ DMEM_SEGMENTS = 8, /* 1MB */
+ UMEM_SEGMENTS = 128 /* 16MB */
+};
+
+struct d10v_memory
+{
+ uint8 *insn[IMEM_SEGMENTS];
+ uint8 *data[DMEM_SEGMENTS];
+ uint8 *unif[UMEM_SEGMENTS];
+ uint8 fault[16];
+};
+
struct _state
{
reg_t regs[16]; /* general-purpose registers */
@@ -209,7 +241,8 @@ struct _state
reg_t cregs[16]; /* control registers */
#define CREG(N) (State.cregs[(N)] + 0)
-#define SET_CREG(N,VAL) move_to_cr ((N), 0, (VAL))
+#define SET_CREG(N,VAL) move_to_cr ((N), 0, (VAL), 0)
+#define SET_HW_CREG(N,VAL) move_to_cr ((N), 0, (VAL), 1)
reg_t sp[2]; /* holding area for SPI(0)/SPU(1) */
#define HELD_SP(N) (State.sp[(N)] + 0)
@@ -232,10 +265,11 @@ struct _state
int exception;
int pc_changed;
- /* NOTE: everything below this line is not reset by sim_create_inferior() */
- uint8 *imem;
- uint8 *dmem;
- uint8 *umem[128];
+ /* NOTE: everything below this line is not reset by
+ sim_create_inferior() */
+
+ struct d10v_memory mem;
+
enum _ins_type ins_type;
} State;
@@ -283,7 +317,8 @@ enum
#define PSW CREG (PSW_CR)
#define SET_PSW(VAL) SET_CREG (PSW_CR, (VAL))
-#define SET_PSW_BIT(MASK,VAL) move_to_cr (PSW_CR, ~(MASK), (VAL) ? (MASK) : 0)
+#define SET_HW_PSW(VAL) SET_HW_CREG (PSW_CR, (VAL))
+#define SET_PSW_BIT(MASK,VAL) move_to_cr (PSW_CR, ~(MASK), (VAL) ? (MASK) : 0, 1)
#define PSW_SM ((PSW & PSW_SM_BIT) != 0)
#define SET_PSW_SM(VAL) SET_PSW_BIT (PSW_SM_BIT, (VAL))
@@ -404,7 +439,7 @@ do \
} \
while (0)
-extern uint8 *dmem_addr PARAMS ((uint32));
+extern uint8 *dmem_addr (uint16 offset);
extern uint8 *imem_addr PARAMS ((uint32));
extern bfd_vma decode_pc PARAMS ((void));
@@ -434,13 +469,6 @@ extern void write_longlong PARAMS ((uint8 *addr, int64 data));
#define READ_64(x) get_longlong(x)
#define WRITE_64(addr,data) write_longlong(addr,data)
-#define IMAP0 RW(0xff00)
-#define IMAP1 RW(0xff02)
-#define DMAP RW(0xff04)
-#define SET_IMAP0(x) SW(0xff00,x)
-#define SET_IMAP1(x) SW(0xff02,x)
-#define SET_DMAP(x) SW(0xff04,x)
-
#define JMP(x) do { SET_PC (x); State.pc_changed = 1; } while (0)
#define RIE_VECTOR_START 0xffc2
@@ -449,4 +477,9 @@ extern void write_longlong PARAMS ((uint8 *addr, int64 data));
#define DBT_VECTOR_START 0xffd4
#define SDBT_VECTOR_START 0xffd5
-extern reg_t move_to_cr PARAMS ((int cr, reg_t mask, reg_t val));
+/* Scedule a store of VAL into cr[CR]. MASK indicates the bits in
+ cr[CR] that should not be modified (i.e. cr[CR] = (cr[CR] & MASK) |
+ (VAL & ~MASK)). In addition, unless PSW_HW_P, a VAL intended for
+ PSW is masked for zero bits. */
+
+extern reg_t move_to_cr (int cr, reg_t mask, reg_t val, int psw_hw_p);
diff --git a/sim/d10v/interp.c b/sim/d10v/interp.c
index bd16391..2a9ae04 100644
--- a/sim/d10v/interp.c
+++ b/sim/d10v/interp.c
@@ -5,11 +5,7 @@
#include "remote-sim.h"
#include "d10v_sim.h"
-
-#define IMEM_SIZE 18 /* D10V instruction memory size is 18 bits */
-#define DMEM_SIZE 16 /* Data memory is 64K (but only 32K internal RAM) */
-#define UMEM_SIZE 17 /* Each unified memory segment is 17 bits */
-#define UMEM_SEGMENTS 128 /* Number of segments in unified memory region */
+#include "sim-d10v.h"
enum _leftright { LEFT_FIRST, RIGHT_FIRST };
@@ -43,6 +39,7 @@ static void do_parallel PARAMS ((uint16 ins1, uint16 ins2));
static char *add_commas PARAMS ((char *buf, int sizeof_buf, unsigned long value));
extern void sim_set_profile PARAMS ((int n));
extern void sim_set_profile_size PARAMS ((int n));
+static INLINE uint8 *map_memory (unsigned phys_addr);
#ifdef NEED_UI_LOOP_HOOK
/* How often to run the ui_loop update, when in use */
@@ -102,8 +99,10 @@ lookup_hash (ins, size)
{
if (h->next == NULL)
{
- (*d10v_callback->printf_filtered) (d10v_callback, "ERROR looking up hash for %x at PC %x\n",ins, PC);
- exit (1);
+ (*d10v_callback->printf_filtered)
+ (d10v_callback, "ERROR: Illegal instruction %x at PC %x\n", ins, PC);
+ State.exception = SIGILL;
+ return NULL;
}
h = h->next;
}
@@ -158,6 +157,8 @@ do_long (ins)
(*d10v_callback->printf_filtered) (d10v_callback, "do_long 0x%x\n", ins);
#endif
h = lookup_hash (ins, 1);
+ if (h == NULL)
+ return;
get_operands (h->ops, ins);
State.ins_type = INS_LONG;
ins_type_counters[ (int)State.ins_type ]++;
@@ -193,6 +194,8 @@ do_2_short (ins1, ins2, leftright)
/* Issue the first instruction */
h = lookup_hash (ins1, 0);
+ if (h == NULL)
+ return;
get_operands (h->ops, ins1);
State.ins_type = first;
ins_type_counters[ (int)State.ins_type ]++;
@@ -204,6 +207,8 @@ do_2_short (ins1, ins2, leftright)
/* finish any existing instructions */
SLOT_FLUSH ();
h = lookup_hash (ins2, 0);
+ if (h == NULL)
+ return;
get_operands (h->ops, ins2);
State.ins_type = second;
ins_type_counters[ (int)State.ins_type ]++;
@@ -225,7 +230,11 @@ do_parallel (ins1, ins2)
#endif
ins_type_counters[ (int)INS_PARALLEL ]++;
h1 = lookup_hash (ins1, 0);
+ if (h1 == NULL)
+ return;
h2 = lookup_hash (ins2, 0);
+ if (h2 == NULL)
+ return;
if (h1->ops->exec_type == PARONLY)
{
@@ -306,252 +315,446 @@ sim_size (power)
{
int i;
-
- if (State.imem)
+ for (i = 0; i < IMEM_SEGMENTS; i++)
{
- for (i=0;i<UMEM_SEGMENTS;i++)
- {
- if (State.umem[i])
- {
- free (State.umem[i]);
- State.umem[i] = NULL;
- }
- }
- free (State.imem);
- free (State.dmem);
+ if (State.mem.insn[i])
+ free (State.mem.insn[i]);
}
-
- State.imem = (uint8 *)calloc(1,1<<IMEM_SIZE);
- State.dmem = (uint8 *)calloc(1,1<<DMEM_SIZE);
- for (i=1;i<(UMEM_SEGMENTS-1);i++)
- State.umem[i] = NULL;
- State.umem[0] = (uint8 *)calloc(1,1<<UMEM_SIZE);
- State.umem[1] = (uint8 *)calloc(1,1<<UMEM_SIZE);
- State.umem[2] = (uint8 *)calloc(1,1<<UMEM_SIZE);
- State.umem[UMEM_SEGMENTS-1] = (uint8 *)calloc(1,1<<UMEM_SIZE);
- if (!State.imem || !State.dmem || !State.umem[0] || !State.umem[1] || !State.umem[2] || !State.umem[UMEM_SEGMENTS-1] )
+ for (i = 0; i < DMEM_SEGMENTS; i++)
{
- (*d10v_callback->printf_filtered) (d10v_callback, "Memory allocation failed.\n");
- exit(1);
+ if (State.mem.data[i])
+ free (State.mem.data[i]);
}
-
+ for (i = 0; i < UMEM_SEGMENTS; i++)
+ {
+ if (State.mem.unif[i])
+ free (State.mem.unif[i]);
+ }
+ /* Always allocate dmem segment 0. This contains the IMAP and DMAP
+ registers. */
+ State.mem.data[0] = calloc (1, SEGMENT_SIZE);
+}
+
+/* For tracing - leave info on last access around. */
+static char *last_segname = "invalid";
+static char *last_from = "invalid";
+static char *last_to = "invalid";
+
+enum
+ {
+ IMAP0_OFFSET = 0xff00,
+ DMAP0_OFFSET = 0xff08,
+ DMAP2_SHADDOW = 0xff04,
+ DMAP2_OFFSET = 0xff0c
+ };
+
+static void
+set_dmap_register (int reg_nr, unsigned long value)
+{
+ uint8 *raw = map_memory (SIM_D10V_MEMORY_DATA
+ + DMAP0_OFFSET + 2 * reg_nr);
+ WRITE_16 (raw, value);
#ifdef DEBUG
- if ((d10v_debug & DEBUG_MEMSIZE) != 0)
+ if ((d10v_debug & DEBUG_MEMORY))
{
- char buffer[20];
- (*d10v_callback->printf_filtered) (d10v_callback,
- "Allocated %s bytes instruction memory and\n",
- add_commas (buffer, sizeof (buffer), (1UL<<IMEM_SIZE)));
+ (*d10v_callback->printf_filtered)
+ (d10v_callback, "mem: dmap%d=0x%04lx\n", reg_nr, value);
+ }
+#endif
+}
- (*d10v_callback->printf_filtered) (d10v_callback, " %s bytes data memory.\n",
- add_commas (buffer, sizeof (buffer), (1UL<<IMEM_SIZE)));
+static unsigned long
+dmap_register (int reg_nr)
+{
+ uint8 *raw = map_memory (SIM_D10V_MEMORY_DATA
+ + DMAP0_OFFSET + 2 * reg_nr);
+ return READ_16 (raw);
+}
+
+static void
+set_imap_register (int reg_nr, unsigned long value)
+{
+ uint8 *raw = map_memory (SIM_D10V_MEMORY_DATA
+ + IMAP0_OFFSET + 2 * reg_nr);
+ WRITE_16 (raw, value);
+#ifdef DEBUG
+ if ((d10v_debug & DEBUG_MEMORY))
+ {
+ (*d10v_callback->printf_filtered)
+ (d10v_callback, "mem: imap%d=0x%04lx\n", reg_nr, value);
}
#endif
}
-/* Transfer data to/from simulated memory. Since a bug in either the
- simulated program or in gdb or the simulator itself may cause a
- bogus address to be passed in, we need to do some sanity checking
- on addresses to make sure they are within bounds. When an address
- fails the bounds check, treat it as a zero length read/write rather
- than aborting the entire run. */
+static unsigned long
+imap_register (int reg_nr)
+{
+ uint8 *raw = map_memory (SIM_D10V_MEMORY_DATA
+ + IMAP0_OFFSET + 2 * reg_nr);
+ return READ_16 (raw);
+}
-static int
-xfer_mem (SIM_ADDR addr,
- unsigned char *buffer,
- int size,
- int write_p)
+enum
+ {
+ HELD_SPI_IDX = 0,
+ HELD_SPU_IDX = 1
+ };
+
+static unsigned long
+spu_register (void)
{
- unsigned char *memory;
- int segment = ((addr >> 24) & 0xff);
- addr = (addr & 0x00ffffff);
+ if (PSW_SM)
+ return GPR (SP_IDX);
+ else
+ return HELD_SP (HELD_SPU_IDX);
+}
-#ifdef DEBUG
- if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
+static unsigned long
+spi_register (void)
+{
+ if (!PSW_SM)
+ return GPR (SP_IDX);
+ else
+ return HELD_SP (HELD_SPI_IDX);
+}
+
+static void
+set_spi_register (unsigned long value)
+{
+ if (!PSW_SM)
+ SET_GPR (SP_IDX, value);
+ SET_HELD_SP (HELD_SPI_IDX, value);
+}
+
+static void
+set_spu_register (unsigned long value)
+{
+ if (PSW_SM)
+ SET_GPR (SP_IDX, value);
+ SET_HELD_SP (HELD_SPU_IDX, value);
+}
+
+/* Given a virtual address in the DMAP address space, translate it
+ into a physical address. */
+
+unsigned long
+sim_d10v_translate_dmap_addr (unsigned long offset,
+ int nr_bytes,
+ unsigned long *phys,
+ unsigned long (*dmap_register) (int reg_nr))
+{
+ short map;
+ int regno;
+ last_from = "logical-data";
+ if (offset >= DMAP_BLOCK_SIZE * SIM_D10V_NR_DMAP_REGS)
{
- if (write_p)
- {
- (*d10v_callback->printf_filtered) (d10v_callback, "sim_write %d bytes to 0x%02x:%06x\n", size, segment, addr);
- }
- else
+ /* Logical address out side of data segments, not supported */
+ return 0;
+ }
+ regno = (offset / DMAP_BLOCK_SIZE);
+ offset = (offset % DMAP_BLOCK_SIZE);
+ if ((offset % DMAP_BLOCK_SIZE) + nr_bytes > DMAP_BLOCK_SIZE)
+ {
+ /* Don't cross a BLOCK boundary */
+ nr_bytes = DMAP_BLOCK_SIZE - (offset % DMAP_BLOCK_SIZE);
+ }
+ map = dmap_register (regno);
+ if (regno == 3)
+ {
+ /* Always maps to data memory */
+ int iospi = (offset / 0x1000) % 4;
+ int iosp = (map >> (4 * (3 - iospi))) % 0x10;
+ last_to = "io-space";
+ *phys = (SIM_D10V_MEMORY_DATA + (iosp * 0x10000) + 0xc000 + offset);
+ }
+ else
+ {
+ int sp = ((map & 0x3000) >> 12);
+ int segno = (map & 0x3ff);
+ switch (sp)
{
- (*d10v_callback->printf_filtered) (d10v_callback, "sim_read %d bytes from 0x%2x:%6x\n", size, segment, addr);
+ case 0: /* 00: Unified memory */
+ *phys = SIM_D10V_MEMORY_UNIFIED + (segno * DMAP_BLOCK_SIZE) + offset;
+ last_to = "unified";
+ break;
+ case 1: /* 01: Instruction Memory */
+ *phys = SIM_D10V_MEMORY_INSN + (segno * DMAP_BLOCK_SIZE) + offset;
+ last_to = "chip-insn";
+ break;
+ case 2: /* 10: Internal data memory */
+ *phys = SIM_D10V_MEMORY_DATA + (segno << 16) + (regno * DMAP_BLOCK_SIZE) + offset;
+ last_to = "chip-data";
+ break;
+ case 3: /* 11: Reserved */
+ return 0;
}
}
-#endif
+ return nr_bytes;
+}
- /* To access data, we use the following mappings:
+/* Given a virtual address in the IMAP address space, translate it
+ into a physical address. */
- 0x00xxxxxx: Physical unified memory segment (Unified memory)
- 0x01xxxxxx: Physical instruction memory segment (On-chip insn memory)
- 0x02xxxxxx: Physical data memory segment (On-chip data memory)
- 0x10xxxxxx: Logical data address segment (DMAP translated memory)
- 0x11xxxxxx: Logical instruction address segment (IMAP translated memory)
+unsigned long
+sim_d10v_translate_imap_addr (unsigned long offset,
+ int nr_bytes,
+ unsigned long *phys,
+ unsigned long (*imap_register) (int reg_nr))
+{
+ short map;
+ int regno;
+ int sp;
+ int segno;
+ last_from = "logical-insn";
+ if (offset >= (IMAP_BLOCK_SIZE * SIM_D10V_NR_IMAP_REGS))
+ {
+ /* Logical address outside of IMAP segments, not supported */
+ return 0;
+ }
+ regno = (offset / IMAP_BLOCK_SIZE);
+ offset = (offset % IMAP_BLOCK_SIZE);
+ if (offset + nr_bytes > IMAP_BLOCK_SIZE)
+ {
+ /* Don't cross a BLOCK boundary */
+ nr_bytes = IMAP_BLOCK_SIZE - offset;
+ }
+ map = imap_register (regno);
+ sp = (map & 0x3000) >> 12;
+ segno = (map & 0x007f);
+ switch (sp)
+ {
+ case 0: /* 00: unified memory */
+ *phys = SIM_D10V_MEMORY_UNIFIED + (segno << 17) + offset;
+ last_to = "unified";
+ break;
+ case 1: /* 01: instruction memory */
+ *phys = SIM_D10V_MEMORY_INSN + (IMAP_BLOCK_SIZE * regno) + offset;
+ last_to = "chip-insn";
+ break;
+ case 2: /*10*/
+ /* Reserved. */
+ return 0;
+ case 3: /* 11: for testing - instruction memory */
+ offset = (offset % 0x800);
+ *phys = SIM_D10V_MEMORY_INSN + offset;
+ if (offset + nr_bytes > 0x800)
+ /* don't cross VM boundary */
+ nr_bytes = 0x800 - offset;
+ last_to = "test-insn";
+ break;
+ }
+ return nr_bytes;
+}
- Alternatively, the "old segment mapping" is still available by setting
- old_segment_mapping to 1. It looks like this:
+unsigned long
+sim_d10v_translate_addr (unsigned long memaddr,
+ int nr_bytes,
+ unsigned long *targ_addr,
+ unsigned long (*dmap_register) (int reg_nr),
+ unsigned long (*imap_register) (int reg_nr))
+{
+ unsigned long phys;
+ unsigned long seg;
+ unsigned long off;
- 0x00xxxxxx: Logical data address segment (DMAP translated memory)
- 0x01xxxxxx: Logical instruction address segment (IMAP translated memory)
- 0x10xxxxxx: Physical data memory segment (On-chip data memory)
- 0x11xxxxxx: Physical instruction memory segment (On-chip insn memory)
- 0x12xxxxxx: Physical unified memory segment (Unified memory)
+ last_from = "unknown";
+ last_to = "unknown";
- */
+ seg = (memaddr >> 24);
+ off = (memaddr & 0xffffffL);
/* However, if we've asked to use the previous generation of segment
mapping, rearrange the segments as follows. */
if (old_segment_mapping)
{
- switch (segment)
+ switch (seg)
{
case 0x00: /* DMAP translated memory */
- segment = 0x10;
+ seg = 0x10;
break;
case 0x01: /* IMAP translated memory */
- segment = 0x11;
+ seg = 0x11;
break;
case 0x10: /* On-chip data memory */
- segment = 0x02;
+ seg = 0x02;
break;
case 0x11: /* On-chip insn memory */
- segment = 0x01;
+ seg = 0x01;
break;
case 0x12: /* Unified memory */
- segment = 0x00;
+ seg = 0x00;
break;
}
}
- switch (segment)
+ switch (seg)
{
- case 0x10: /* DMAP translated memory */
- {
- int byte;
- for (byte = 0; byte < size; byte++)
- {
- uint8 *mem = dmem_addr (addr + byte);
- if (mem == NULL)
- return byte;
- else if (write_p)
- *mem = buffer[byte];
- else
- buffer[byte] = *mem;
- }
- return byte;
- }
+ case 0x00: /* Physical unified memory */
+ last_from = "phys-unified";
+ last_to = "unified";
+ phys = SIM_D10V_MEMORY_UNIFIED + off;
+ if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
+ nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
+ break;
- case 0x11: /* IMAP translated memory */
- {
- int byte;
- for (byte = 0; byte < size; byte++)
- {
- uint8 *mem = imem_addr (addr + byte);
- if (mem == NULL)
- return byte;
- else if (write_p)
- *mem = buffer[byte];
- else
- buffer[byte] = *mem;
- }
- return byte;
- }
+ case 0x01: /* Physical instruction memory */
+ last_from = "phys-insn";
+ last_to = "chip-insn";
+ phys = SIM_D10V_MEMORY_INSN + off;
+ if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
+ nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
+ break;
- case 0x02: /* On-chip data memory */
+ case 0x02: /* Physical data memory segment */
+ last_from = "phys-data";
+ last_to = "chip-data";
+ phys = SIM_D10V_MEMORY_DATA + off;
+ if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
+ nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
+ break;
+
+ case 0x10: /* in logical data address segment */
+ nr_bytes = sim_d10v_translate_dmap_addr (off, nr_bytes, &phys,
+ dmap_register);
+ break;
+
+ case 0x11: /* in logical instruction address segment */
+ nr_bytes = sim_d10v_translate_imap_addr (off, nr_bytes, &phys,
+ imap_register);
+ break;
+
+ default:
+ return 0;
+ }
+
+ *targ_addr = phys;
+ return nr_bytes;
+}
+
+/* Return a pointer into the raw buffer designated by phys_addr. It
+ is assumed that the client has already ensured that the access
+ isn't going to cross a segment boundary. */
+
+uint8 *
+map_memory (unsigned phys_addr)
+{
+ uint8 **memory;
+ uint8 *raw;
+ unsigned offset;
+ int segment = ((phys_addr >> 24) & 0xff);
+
+ switch (segment)
+ {
+
+ case 0x00: /* Unified memory */
{
- addr &= ((1 << DMEM_SIZE) - 1);
- if ((addr + size) > (1 << DMEM_SIZE))
- {
- (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: data address 0x%x is outside range 0-0x%x.\n",
- addr + size - 1, (1 << DMEM_SIZE) - 1);
- return (0);
- }
- memory = State.dmem + addr;
+ memory = &State.mem.unif[(phys_addr / SEGMENT_SIZE) % UMEM_SEGMENTS];
+ last_segname = "umem";
break;
}
-
+
case 0x01: /* On-chip insn memory */
{
- addr &= ((1 << IMEM_SIZE) - 1);
- if ((addr + size) > (1 << IMEM_SIZE))
- {
- (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: instruction address 0x%x is outside range 0-0x%x.\n",
- addr + size - 1, (1 << IMEM_SIZE) - 1);
- return (0);
- }
- memory = State.imem + addr;
+ memory = &State.mem.insn[(phys_addr / SEGMENT_SIZE) % IMEM_SEGMENTS];
+ last_segname = "imem";
break;
}
-
- case 0x00: /* Unified memory */
+
+ case 0x02: /* On-chip data memory */
{
- int startsegment, startoffset; /* Segment and offset within segment where xfer starts */
- int endsegment, endoffset; /* Segment and offset within segment where xfer ends */
-
- startsegment = addr >> UMEM_SIZE;
- startoffset = addr & ((1 << UMEM_SIZE) - 1);
- endsegment = (addr + size) >> UMEM_SIZE;
- endoffset = (addr + size) & ((1 << UMEM_SIZE) - 1);
-
- /* FIXME: We do not currently implement xfers across segments,
- so detect this case and fail gracefully. */
-
- if ((startsegment != endsegment) && !((endsegment == (startsegment + 1)) && endoffset == 0))
- {
- (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: Unimplemented support for transfers across unified memory segment boundaries\n");
- return (0);
- }
- if (!State.umem[startsegment])
+ if ((phys_addr & 0xff00) == 0xff00)
{
-#ifdef DEBUG
- if ((d10v_debug & DEBUG_MEMSIZE) != 0)
+ phys_addr = (phys_addr & 0xffff);
+ if (phys_addr == DMAP2_SHADDOW)
{
- (*d10v_callback->printf_filtered) (d10v_callback,"Allocating %s bytes unified memory to region %d\n",
- add_commas (buffer, sizeof (buffer), (1UL<<IMEM_SIZE)), startsegment);
+ phys_addr = DMAP2_OFFSET;
+ last_segname = "dmap";
}
-#endif
- State.umem[startsegment] = (uint8 *)calloc(1,1<<UMEM_SIZE);
- }
- if (!State.umem[startsegment])
- {
- (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: Memory allocation of 0x%x bytes failed.\n", 1<<UMEM_SIZE);
- return (0);
+ else
+ last_segname = "reg";
}
- memory = State.umem[startsegment] + startoffset;
+ else
+ last_segname = "dmem";
+ memory = &State.mem.data[(phys_addr / SEGMENT_SIZE) % DMEM_SEGMENTS];
break;
}
-
+
default:
- {
- (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: address 0x%lx is not in valid range\n", (long) addr);
- if (old_segment_mapping)
- {
- (*d10v_callback->printf_filtered) (d10v_callback, "0x00xxxxxx: Logical data address segment (DMAP translated memory)\n");
- (*d10v_callback->printf_filtered) (d10v_callback, "0x01xxxxxx: Logical instruction address segment (IMAP translated memory)\n");
- (*d10v_callback->printf_filtered) (d10v_callback, "0x10xxxxxx: Physical data memory segment (On-chip data memory)\n");
- (*d10v_callback->printf_filtered) (d10v_callback, "0x11xxxxxx: Physical instruction memory segment (On-chip insn memory)\n");
- (*d10v_callback->printf_filtered) (d10v_callback, "0x12xxxxxx: Phisical unified memory segment (Unified memory)\n");
- }
- else
- {
- (*d10v_callback->printf_filtered) (d10v_callback, "0x00xxxxxx: Physical unified memory segment (Unified memory)\n");
- (*d10v_callback->printf_filtered) (d10v_callback, "0x01xxxxxx: Physical instruction memory segment (On-chip insn memory)\n");
- (*d10v_callback->printf_filtered) (d10v_callback, "0x02xxxxxx: Physical data memory segment (On-chip data memory)\n");
- (*d10v_callback->printf_filtered) (d10v_callback, "0x10xxxxxx: Logical data address segment (DMAP translated memory)\n");
- (*d10v_callback->printf_filtered) (d10v_callback, "0x11xxxxxx: Logical instruction address segment (IMAP translated memory)\n");
- }
- return (0);
- }
+ /* OOPS! */
+ last_segname = "scrap";
+ return State.mem.fault;
}
-
- if (write_p)
+
+ if (*memory == NULL)
{
- memcpy (memory, buffer, size);
+ *memory = calloc (1, SEGMENT_SIZE);
+ if (*memory == NULL)
+ {
+ (*d10v_callback->printf_filtered) (d10v_callback, "Malloc failed.\n");
+ return State.mem.fault;
+ }
}
- else
+
+ offset = (phys_addr % SEGMENT_SIZE);
+ raw = *memory + offset;
+ return raw;
+}
+
+/* Transfer data to/from simulated memory. Since a bug in either the
+ simulated program or in gdb or the simulator itself may cause a
+ bogus address to be passed in, we need to do some sanity checking
+ on addresses to make sure they are within bounds. When an address
+ fails the bounds check, treat it as a zero length read/write rather
+ than aborting the entire run. */
+
+static int
+xfer_mem (SIM_ADDR virt,
+ unsigned char *buffer,
+ int size,
+ int write_p)
+{
+ int xfered = 0;
+
+ while (xfered < size)
{
- memcpy (buffer, memory, size);
+ uint8 *memory;
+ unsigned long phys;
+ int phys_size;
+ phys_size = sim_d10v_translate_addr (virt, size,
+ &phys,
+ dmap_register,
+ imap_register);
+ if (phys_size == 0)
+ return xfered;
+
+ memory = map_memory (phys);
+
+#ifdef DEBUG
+ if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
+ {
+ (*d10v_callback->printf_filtered)
+ (d10v_callback,
+ "sim_%s %d bytes: 0x%08lx (%s) -> 0x%08lx (%s) -> 0x%08lx (%s)\n",
+ (write_p ? "write" : "read"),
+ phys_size, virt, last_from,
+ phys, last_to,
+ (long) memory, last_segname);
+ }
+#endif
+
+ if (write_p)
+ {
+ memcpy (memory, buffer, phys_size);
+ }
+ else
+ {
+ memcpy (buffer, memory, phys_size);
+ }
+
+ virt += phys_size;
+ buffer += phys_size;
+ xfered += phys_size;
}
return size;
@@ -598,6 +801,9 @@ sim_open (kind, callback, abfd, argv)
myname = argv[0];
old_segment_mapping = 0;
+ /* NOTE: This argument parsing is only effective when this function
+ is called by GDB. Standalone argument parsing is handled by
+ sim/common/run.c. */
for (p = argv + 1; *p; ++p)
{
if (strcmp (*p, "-oldseg") == 0)
@@ -605,6 +811,8 @@ sim_open (kind, callback, abfd, argv)
#ifdef DEBUG
else if (strcmp (*p, "-t") == 0)
d10v_debug = DEBUG;
+ else if (strncmp (*p, "-t", 2) == 0)
+ d10v_debug = atoi (*p + 2);
#endif
else
(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: unsupported option(s): %s\n",*p);
@@ -637,8 +845,8 @@ sim_open (kind, callback, abfd, argv)
}
/* reset the processor state */
- if (!State.imem)
- sim_size(1);
+ if (!State.mem.data[0])
+ sim_size (1);
sim_create_inferior ((SIM_DESC) 1, NULL, NULL, NULL);
/* Fudge our descriptor. */
@@ -673,84 +881,64 @@ sim_set_profile_size (n)
(*d10v_callback->printf_filtered) (d10v_callback, "sim_set_profile_size %d\n",n);
}
-
uint8 *
-dmem_addr( addr )
- uint32 addr;
+dmem_addr (uint16 offset)
{
- int seg;
+ unsigned long phys;
+ uint8 *mem;
+ int phys_size;
- addr &= 0xffff;
+ /* Note: DMEM address range is 0..0x10000. Calling code can compute
+ things like ``0xfffe + 0x0e60 == 0x10e5d''. Since offset's type
+ is uint16 this is modulo'ed onto 0x0e5d. */
- if (addr > 0xbfff)
+ phys_size = sim_d10v_translate_dmap_addr (offset, 1, &phys,
+ dmap_register);
+ if (phys_size == 0)
{
- if ( (addr & 0xfff0) != 0xff00)
- {
- (*d10v_callback->printf_filtered) (d10v_callback, "Data address 0x%lx is in I/O space, pc = 0x%lx.\n",
- (long)addr, (long)decode_pc ());
- State.exception = SIGBUS;
- }
-
- return State.dmem + addr;
+ mem = State.mem.fault;
}
-
- if (addr > 0x7fff)
- {
- if (DMAP & 0x1000)
- {
- /* instruction memory */
- return (DMAP & 0xf) * 0x4000 + State.imem + (addr - 0x8000);
- }
- else
- {
- /* unified memory */
- /* this is ugly because we allocate unified memory in 128K segments and */
- /* dmap addresses 16k segments */
- seg = (DMAP & 0x3ff) >> 3;
- if (State.umem[seg] == NULL)
- {
+ else
+ mem = map_memory (phys);
#ifdef DEBUG
- (*d10v_callback->printf_filtered) (d10v_callback,"Allocating %d bytes unified memory to region %d\n", 1<<UMEM_SIZE, seg);
-#endif
- State.umem[seg] = (uint8 *)calloc(1,1<<UMEM_SIZE);
- if (!State.umem[seg])
- {
- (*d10v_callback->printf_filtered) (d10v_callback,
- "ERROR: alloc failed. unified memory region %d unmapped, pc = 0x%lx\n",
- seg, (long)decode_pc ());
- State.exception = SIGBUS;
- }
- }
- return State.umem[seg] + (DMAP & 7) * 0x4000 + (addr - 0x8000);
- }
+ if ((d10v_debug & DEBUG_MEMORY))
+ {
+ (*d10v_callback->printf_filtered)
+ (d10v_callback,
+ "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
+ offset, last_from,
+ phys, phys_size, last_to,
+ (long) mem, last_segname);
}
- return State.dmem + addr;
+#endif
+ return mem;
}
-
uint8 *
-imem_addr (uint32 pc)
+imem_addr (uint32 offset)
{
- uint16 imap;
-
- if (pc & 0x20000)
- imap = IMAP1;
- else
- imap = IMAP0;
-
- if (imap & 0x1000)
- return State.imem + pc;
-
- if (State.umem[imap & 0xff] == NULL)
- return 0;
-
- /* Discard upper bit(s) of PC in case IMAP1 selects unified memory. */
- pc &= (1 << UMEM_SIZE) - 1;
-
- return State.umem[imap & 0xff] + pc;
+ unsigned long phys;
+ uint8 *mem;
+ int phys_size = sim_d10v_translate_imap_addr (offset, 1, &phys, imap_register);
+ if (phys_size == 0)
+ {
+ return State.mem.fault;
+ }
+ mem = map_memory (phys);
+#ifdef DEBUG
+ if ((d10v_debug & DEBUG_MEMORY))
+ {
+ (*d10v_callback->printf_filtered)
+ (d10v_callback,
+ "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
+ offset, last_from,
+ phys, phys_size, last_to,
+ (long) mem, last_segname);
+ }
+#endif
+ return mem;
}
-
static int stop_simulator = 0;
int
@@ -779,7 +967,7 @@ sim_resume (sd, step, siggnal)
do
{
iaddr = imem_addr ((uint32)PC << 2);
- if (iaddr == NULL)
+ if (iaddr == State.mem.fault)
{
State.exception = SIGBUS;
break;
@@ -990,7 +1178,7 @@ sim_create_inferior (sd, abfd, argv, env)
bfd_vma start_address;
/* reset all state information */
- memset (&State.regs, 0, (int)&State.imem - (int)&State.regs[0]);
+ memset (&State.regs, 0, (int)&State.mem - (int)&State.regs);
if (argv)
{
@@ -1022,19 +1210,28 @@ sim_create_inferior (sd, abfd, argv, env)
#endif
SET_CREG (PC_CR, start_address >> 2);
- /* cpu resets imap0 to 0 and imap1 to 0x7f, but D10V-EVA board */
- /* resets imap0 and imap1 to 0x1000. */
+ /* cpu resets imap0 to 0 and imap1 to 0x7f, but D10V-EVA board
+ initializes imap0 and imap1 to 0x1000 as part of its ROM
+ initialization. */
if (old_segment_mapping)
{
- SET_IMAP0 (0x0000);
- SET_IMAP1 (0x007f);
- SET_DMAP (0x0000);
+ /* External memory startup. This is the HARD reset state. */
+ set_imap_register (0, 0x0000);
+ set_imap_register (1, 0x007f);
+ set_dmap_register (0, 0x2000);
+ set_dmap_register (1, 0x2000);
+ set_dmap_register (2, 0x0000); /* Old DMAP */
+ set_dmap_register (3, 0x0000);
}
else
{
- SET_IMAP0 (0x1000);
- SET_IMAP1 (0x1000);
- SET_DMAP(0);
+ /* Internal memory startup. This is the ROM intialized state. */
+ set_imap_register (0, 0x1000);
+ set_imap_register (1, 0x1000);
+ set_dmap_register (0, 0x2000);
+ set_dmap_register (1, 0x2000);
+ set_dmap_register (2, 0x0000); /* Old DMAP, Value is not 0x2000 */
+ set_dmap_register (3, 0x0000);
}
SLOT_FLUSH ();
@@ -1088,19 +1285,56 @@ sim_fetch_register (sd, rn, memory, length)
unsigned char *memory;
int length;
{
- if (rn > 34)
- WRITE_64 (memory, ACC (rn-35));
- else if (rn == 32)
- WRITE_16 (memory, IMAP0);
- else if (rn == 33)
- WRITE_16 (memory, IMAP1);
- else if (rn == 34)
- WRITE_16 (memory, DMAP);
- else if (rn >= 16)
- WRITE_16 (memory, CREG (rn - 16));
+ int size;
+ if (rn < 0)
+ size = 0;
+ else if (rn >= SIM_D10V_R0_REGNUM
+ && rn < SIM_D10V_R0_REGNUM + SIM_D10V_NR_R_REGS)
+ {
+ WRITE_16 (memory, GPR (rn - SIM_D10V_R0_REGNUM));
+ size = 2;
+ }
+ else if (rn >= SIM_D10V_CR0_REGNUM
+ && rn < SIM_D10V_CR0_REGNUM + SIM_D10V_NR_CR_REGS)
+ {
+ WRITE_16 (memory, CREG (rn - SIM_D10V_CR0_REGNUM));
+ size = 2;
+ }
+ else if (rn >= SIM_D10V_A0_REGNUM
+ && rn < SIM_D10V_A0_REGNUM + SIM_D10V_NR_A_REGS)
+ {
+ WRITE_64 (memory, ACC (rn - SIM_D10V_A0_REGNUM));
+ size = 8;
+ }
+ else if (rn == SIM_D10V_SPI_REGNUM)
+ {
+ /* PSW_SM indicates that the current SP is the USER
+ stack-pointer. */
+ WRITE_16 (memory, spi_register ());
+ size = 2;
+ }
+ else if (rn == SIM_D10V_SPU_REGNUM)
+ {
+ /* PSW_SM indicates that the current SP is the USER
+ stack-pointer. */
+ WRITE_16 (memory, spu_register ());
+ size = 2;
+ }
+ else if (rn >= SIM_D10V_IMAP0_REGNUM
+ && rn < SIM_D10V_IMAP0_REGNUM + SIM_D10V_NR_IMAP_REGS)
+ {
+ WRITE_16 (memory, imap_register (rn - SIM_D10V_IMAP0_REGNUM));
+ size = 2;
+ }
+ else if (rn >= SIM_D10V_DMAP0_REGNUM
+ && rn < SIM_D10V_DMAP0_REGNUM + SIM_D10V_NR_DMAP_REGS)
+ {
+ WRITE_16 (memory, dmap_register (rn - SIM_D10V_DMAP0_REGNUM));
+ size = 2;
+ }
else
- WRITE_16 (memory, GPR (rn));
- return -1;
+ size = 0;
+ return size;
}
int
@@ -1110,20 +1344,55 @@ sim_store_register (sd, rn, memory, length)
unsigned char *memory;
int length;
{
- if (rn > 34)
- SET_ACC (rn-35, READ_64 (memory) & MASK40);
- else if (rn == 34)
- SET_DMAP( READ_16(memory) );
- else if (rn == 33)
- SET_IMAP1( READ_16(memory) );
- else if (rn == 32)
- SET_IMAP0( READ_16(memory) );
- else if (rn >= 16)
- SET_CREG (rn - 16, READ_16 (memory));
+ int size;
+ if (rn < 0)
+ size = 0;
+ else if (rn >= SIM_D10V_R0_REGNUM
+ && rn < SIM_D10V_R0_REGNUM + SIM_D10V_NR_R_REGS)
+ {
+ SET_GPR (rn - SIM_D10V_R0_REGNUM, READ_16 (memory));
+ size = 2;
+ }
+ else if (rn >= SIM_D10V_CR0_REGNUM
+ && rn < SIM_D10V_CR0_REGNUM + SIM_D10V_NR_CR_REGS)
+ {
+ SET_CREG (rn - SIM_D10V_CR0_REGNUM, READ_16 (memory));
+ size = 2;
+ }
+ else if (rn >= SIM_D10V_A0_REGNUM
+ && rn < SIM_D10V_A0_REGNUM + SIM_D10V_NR_A_REGS)
+ {
+ SET_ACC (rn - SIM_D10V_A0_REGNUM, READ_64 (memory) & MASK40);
+ size = 8;
+ }
+ else if (rn == SIM_D10V_SPI_REGNUM)
+ {
+ /* PSW_SM indicates that the current SP is the USER
+ stack-pointer. */
+ set_spi_register (READ_16 (memory));
+ size = 2;
+ }
+ else if (rn == SIM_D10V_SPU_REGNUM)
+ {
+ set_spu_register (READ_16 (memory));
+ size = 2;
+ }
+ else if (rn >= SIM_D10V_IMAP0_REGNUM
+ && rn < SIM_D10V_IMAP0_REGNUM + SIM_D10V_NR_IMAP_REGS)
+ {
+ set_imap_register (rn - SIM_D10V_IMAP0_REGNUM, READ_16(memory));
+ size = 2;
+ }
+ else if (rn >= SIM_D10V_DMAP0_REGNUM
+ && rn < SIM_D10V_DMAP0_REGNUM + SIM_D10V_NR_DMAP_REGS)
+ {
+ set_dmap_register (rn - SIM_D10V_DMAP0_REGNUM, READ_16(memory));
+ size = 2;
+ }
else
- SET_GPR (rn, READ_16 (memory));
+ size = 0;
SLOT_FLUSH ();
- return -1;
+ return size;
}
diff --git a/sim/d10v/simops.c b/sim/d10v/simops.c
index 5f19ebd..d80c923 100644
--- a/sim/d10v/simops.c
+++ b/sim/d10v/simops.c
@@ -56,10 +56,13 @@ enum {
| PSW_F0_BIT
| PSW_F1_BIT
| PSW_C_BIT),
+ /* The following bits in the PSW _can't_ be set by instructions such
+ as mvtc. */
+ PSW_HW_MASK = (PSW_MASK | PSW_DM_BIT)
};
reg_t
-move_to_cr (int cr, reg_t mask, reg_t val)
+move_to_cr (int cr, reg_t mask, reg_t val, int psw_hw_p)
{
/* A MASK bit is set when the corresponding bit in the CR should
be left alone */
@@ -67,13 +70,18 @@ move_to_cr (int cr, reg_t mask, reg_t val)
switch (cr)
{
case PSW_CR:
- val &= PSW_MASK;
+ if (psw_hw_p)
+ val &= PSW_HW_MASK;
+ else
+ val &= PSW_MASK;
if ((mask & PSW_SM_BIT) == 0)
{
- int new_sm = (val & PSW_SM_BIT) != 0;
- SET_HELD_SP (PSW_SM, GPR (SP_IDX)); /* save old SP */
- if (PSW_SM != new_sm)
- SET_GPR (SP_IDX, HELD_SP (new_sm)); /* restore new SP */
+ int new_psw_sm = (val & PSW_SM_BIT) != 0;
+ /* save old SP */
+ SET_HELD_SP (PSW_SM, GPR (SP_IDX));
+ if (PSW_SM != new_psw_sm)
+ /* restore new SP */
+ SET_GPR (SP_IDX, HELD_SP (new_psw_sm));
}
if ((mask & (PSW_ST_BIT | PSW_FX_BIT)) == 0)
{
@@ -91,7 +99,11 @@ move_to_cr (int cr, reg_t mask, reg_t val)
break;
case BPSW_CR:
case DPSW_CR:
- val &= PSW_MASK;
+ /* Just like PSW, mask things like DM out. */
+ if (psw_hw_p)
+ val &= PSW_HW_MASK;
+ else
+ val &= PSW_MASK;
break;
case MOD_S_CR:
case MOD_E_CR:
@@ -1096,7 +1108,7 @@ OP_5F20 ()
trace_input ("dbt", OP_VOID, OP_VOID, OP_VOID);
SET_DPC (PC + 1);
SET_DPSW (PSW);
- SET_PSW (PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT));
+ SET_HW_PSW (PSW_DM_BIT | (PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
JMP (DBT_VECTOR_START);
trace_output_void ();
}
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index c12ec65..6c8bc4a 100644
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,8 @@
+1999-11-11 Andrew Haley <aph@cygnus.com>
+
+ * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
+ instructions.
+
Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
* mips.igen (MULT): Correct previous mis-applied patch.
diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index 68ffd27..9c53ff9 100644
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -3124,9 +3124,14 @@ decode_coproc (SIM_DESC sd,
CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
ERET Exception return (VR4100 = 01000010000000000000000000011000)
*/
- if (((code == 0x00) || (code == 0x04)) && tail == 0)
+ if (((code == 0x00) || (code == 0x04) /* MFC0 / MTC0 */
+ || (code == 0x01) || (code == 0x05)) /* DMFC0 / DMTC0 */
+ && tail == 0)
{
- /* M[TF]C0 - 32 bit word */
+ /* Clear double/single coprocessor move bit. */
+ code &= ~1;
+
+ /* M[TF]C0 (32 bits) | DM[TF]C0 (64 bits) */
switch (rd) /* NOTEs: Standard CP0 registers */
{
diff --git a/sim/testsuite/d10v-elf/ChangeLog b/sim/testsuite/d10v-elf/ChangeLog
index 723f88a..de4a22c 100644
--- a/sim/testsuite/d10v-elf/ChangeLog
+++ b/sim/testsuite/d10v-elf/ChangeLog
@@ -1,3 +1,12 @@
+Fri Oct 29 18:36:34 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * t-mvtc.s: Check that the user can not modify the DM bit in the
+ BPSW or DPSW.
+
+Thu Oct 28 01:47:26 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * t-mvtc.s: Update. Check that user can not modify DM bit.
+
Wed Sep 8 19:34:55 MDT 1999 Diego Novillo <dnovillo@cygnus.com>
* t-ld-st.s: New file.
diff --git a/sim/testsuite/d10v-elf/t-mvtc.s b/sim/testsuite/d10v-elf/t-mvtc.s
index cbf9308..2eed833 100644
--- a/sim/testsuite/d10v-elf/t-mvtc.s
+++ b/sim/testsuite/d10v-elf/t-mvtc.s
@@ -17,7 +17,7 @@
checkpsw2 4 PSW_DB
loadpsw2 PSW_DM
- checkpsw2 5 PSW_DM
+ checkpsw2 5 0 ;; PSW_DM
loadpsw2 PSW_IE
checkpsw2 6 PSW_IE
@@ -65,17 +65,65 @@
mvfc r7, cr11
check 18 r7 0xbeee
-;;; Check that certain bits of the DPSW and BPSW are hardwired to zero
+;;; Check that certain bits of the PSW, DPSW and BPSW are hardwired to zero
+psw_ffff:
+ ldi r6, 0xffff
+ mvtc r6, psw
+ mvfc r7, psw
+ check 18 r7 0xb7cd
+
+bpsw_ffff:
ldi r6, 0xffff
mvtc r6, bpsw
mvfc r7, bpsw
- check 18 r7 0xbfcd
+ check 18 r7 0xb7cd
+dpsw_ffff:
ldi r6, 0xffff
mvtc r6, dpsw
mvfc r7, dpsw
- check 18 r7 0xbfcd
+ check 18 r7 0xb7cd
+
+;;; Another check. Very similar
+
+psw_dfff:
+ ldi r6, 0xdfff
+ mvtc r6, psw
+ mvfc r7, psw
+ check 18 r7 0x97cd
+
+bpsw_dfff:
+ ldi r6, 0xdfff
+ mvtc r6, bpsw
+ mvfc r7, bpsw
+ check 18 r7 0x97cd
+
+dpsw_dfff:
+ ldi r6, 0xdfff
+ mvtc r6, dpsw
+ mvfc r7, dpsw
+ check 18 r7 0x97cd
+
+;;; And again.
+
+psw_8005:
+ ldi r6, 0x8005
+ mvtc r6, psw
+ mvfc r7, psw
+ check 18 r7 0x8005
+
+bpsw_8005:
+ ldi r6, 0x8005
+ mvtc r6, bpsw
+ mvfc r7, bpsw
+ check 18 r7 0x8005
+
+dpsw_8005:
+ ldi r6, 0x8005
+ mvtc r6, dpsw
+ mvfc r7, dpsw
+ check 18 r7 0x8005
exit0