Thu Dec 10 18:46:25 1998 Dave Brolley <brolley@cygnus.com>

	* sim/fr30/div0s.cgs: New testcase.
	* sim/fr30/div0u.cgs: New testcase.
	* sim/fr30/div1.cgs: New testcase.
	* sim/fr30/div2.cgs: New testcase.
	* sim/fr30/div3.cgs: New testcase.
	* sim/fr30/div4s.cgs: New testcase.
	* sim/fr30/testutils.inc (mvi_h_dr,set_dbits,test_dbits): New Macros.

8 files changed, 428 insertions, 0 deletions

diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog
index c59e93a..27c1964 100644
--- a/sim/testsuite/ChangeLog
+++ b/sim/testsuite/ChangeLog
@@ -1,3 +1,13 @@
+Thu Dec 10 18:46:25 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* sim/fr30/div0s.cgs: New testcase.
+	* sim/fr30/div0u.cgs: New testcase.
+	* sim/fr30/div1.cgs: New testcase.
+	* sim/fr30/div2.cgs: New testcase.
+	* sim/fr30/div3.cgs: New testcase.
+	* sim/fr30/div4s.cgs: New testcase.
+	* sim/fr30/testutils.inc (mvi_h_dr,set_dbits,test_dbits): New Macros.
+
 Tue Dec  8 13:16:53 1998  Dave Brolley  <brolley@cygnus.com>
 
 	* sim/fr30/testutils.inc (set_s_user): Correct Mask.
diff --git a/sim/testsuite/sim/fr30/div0s.cgs b/sim/testsuite/sim/fr30/div0s.cgs
new file mode 100644
index 0000000..84d76c4
--- /dev/null
+++ b/sim/testsuite/sim/fr30/div0s.cgs
@@ -0,0 +1,64 @@
+# fr30 testcase for div0s $Ri
+# mach(): fr30
+
+	.include "testutils.inc"
+
+	START
+
+	.text
+	.global div0s
+div0s:
+	; Test div0s $Rj,$Ri
+	; example from the manual - negative dividend
+	mvi_h_gr   	0x0fffffff,r2
+	mvi_h_dr   	0x00000000,mdh
+	mvi_h_dr   	0xfffffff0,mdl
+	set_dbits	0x0		; Set opposite of expected
+	set_cc          0x0f		; Condition codes should not change
+	div0s      	r2
+	test_cc		1 1 1 1
+	test_h_gr  	0x0fffffff,r2
+	test_h_dr  	0xffffffff,mdh
+	test_h_dr  	0xfffffff0,mdl
+	test_dbits	0x3
+
+	; negative divisor
+	mvi_h_gr   	0xffffffff,r2
+	mvi_h_dr   	0xffffffff,mdh
+	mvi_h_dr   	0x7fffffff,mdl
+	set_dbits	0x1		; Set opposite of expected
+	set_cc          0x0f		; Condition codes should not change
+	div0s      	r2
+	test_cc		1 1 1 1
+	test_h_gr  	0xffffffff,r2
+	test_h_dr  	0x00000000,mdh
+	test_h_dr  	0x7fffffff,mdl
+	test_dbits	0x2
+
+	; Both sign bits 0
+	mvi_h_gr   	0x0fffffff,r2
+	mvi_h_dr   	0xffffffff,mdh
+	mvi_h_dr   	0x7ffffff0,mdl
+	set_dbits	0x3		; Set opposite of expected
+	set_cc          0x0f		; Condition codes should not change
+	div0s      	r2
+	test_cc		1 1 1 1
+	test_h_gr  	0x0fffffff,r2
+	test_h_dr  	0x00000000,mdh
+	test_h_dr  	0x7ffffff0,mdl
+	test_dbits	0x0
+
+	; Both sign bits 1
+	mvi_h_gr   	0xffffffff,r2
+	mvi_h_dr   	0x00000000,mdh
+	mvi_h_dr   	0xffffffff,mdl
+	set_dbits	0x2		; Set opposite of expected
+	set_cc          0x0f		; Condition codes should not change
+	div0s      	r2
+	test_cc		1 1 1 1
+	test_h_gr  	0xffffffff,r2
+	test_h_dr  	0xffffffff,mdh
+	test_h_dr  	0xffffffff,mdl
+	test_dbits	0x1
+
+	pass
diff --git a/sim/testsuite/sim/fr30/div0u.cgs b/sim/testsuite/sim/fr30/div0u.cgs
new file mode 100644
index 0000000..8fd84a6
--- /dev/null
+++ b/sim/testsuite/sim/fr30/div0u.cgs
@@ -0,0 +1,25 @@
+# fr30 testcase for div0u $Ri
+# mach(): fr30
+
+	.include "testutils.inc"
+
+	START
+
+	.text
+	.global div0u
+div0u:
+	; Test div0u $Rj,$Ri
+	; operand register has no effect
+	mvi_h_gr   	0xdeadbeef,r2
+	mvi_h_dr   	0xdeadbeef,mdh
+	mvi_h_dr   	0x0ffffff0,mdl
+	set_dbits	0x3		; Set opposite of expected
+	set_cc          0x0f		; Condition codes should not change
+	div0u      	r2
+	test_cc		1 1 1 1
+	test_h_gr  	0xdeadbeef,r2
+	test_h_dr  	0x00000000,mdh
+	test_h_dr  	0x0ffffff0,mdl
+	test_dbits	0x0
+
+	pass
diff --git a/sim/testsuite/sim/fr30/div1.cgs b/sim/testsuite/sim/fr30/div1.cgs
new file mode 100644
index 0000000..dac35fe
--- /dev/null
+++ b/sim/testsuite/sim/fr30/div1.cgs
@@ -0,0 +1,113 @@
+# fr30 testcase for div1 $Ri
+# mach(): fr30
+
+	.include "testutils.inc"
+
+	START
+
+	.text
+	.global div1
+div1:
+	; Test div1 $Ri
+	; example from the manual -- all status bits 0
+	mvi_h_gr   	0x00ffffff,r2
+	mvi_h_dr   	0x00ffffff,mdh
+	mvi_h_dr   	0x00000000,mdl
+	set_dbits	0x0
+	set_cc          0x00
+	div1      	r2
+	test_cc		0 0 0 0
+	test_dbits	0x0
+	test_h_gr  	0x00ffffff,r2
+	test_h_dr  	0x00ffffff,mdh	; misprinted in manual?
+	test_h_dr  	0x00000001,mdl
+
+	; D0 == 1
+	set_dbits	0x1
+	set_cc          0x00
+	div1      	r2
+	test_cc		0 0 0 0
+	test_dbits	0x1
+	test_h_gr  	0x00ffffff,r2
+	test_h_dr  	0x01fffffe,mdh
+	test_h_dr  	0x00000002,mdl
+
+	; D1 == 1
+	set_dbits	0x2
+	set_cc          0x00
+	div1      	r2
+	test_cc		0 0 0 0
+	test_dbits	0x2
+	test_h_gr  	0x00ffffff,r2
+	test_h_dr  	0x03fffffc,mdh
+	test_h_dr  	0x00000004,mdl
+
+	; D0 == 1, D1 == 1
+	set_dbits	0x3
+	set_cc          0x00
+	div1      	r2
+	test_cc		0 0 0 0
+	test_dbits	0x3
+	test_h_gr  	0x00ffffff,r2
+	test_h_dr  	0x08fffff7,mdh
+	test_h_dr  	0x00000009,mdl
+
+	; C == 1
+	mvi_h_gr  	0x11ffffef,r2
+	set_dbits	0x0
+	set_cc          0x00
+	div1      	r2
+	test_cc		0 0 0 1
+	test_dbits	0x0
+	test_h_gr  	0x11ffffef,r2
+	test_h_dr  	0x11ffffee,mdh
+	test_h_dr  	0x00000012,mdl
+
+	; D0 == 1, C == 1
+	mvi_h_gr  	0x23ffffdd,r2
+	set_dbits	0x1
+	set_cc          0x00
+	div1      	r2
+	test_cc		0 0 0 1
+	test_dbits	0x1
+	test_h_gr  	0x23ffffdd,r2
+	test_h_dr  	0xffffffff,mdh
+	test_h_dr  	0x00000025,mdl
+
+	; D1 == 1, C == 1
+	mvi_h_gr  	0x00000003,r2
+	set_dbits	0x2
+	set_cc          0x00
+	div1      	r2
+	test_cc		0 0 0 1
+	test_dbits	0x2
+	test_h_gr  	0x00000003,r2
+	test_h_dr  	0x00000001,mdh
+	test_h_dr  	0x0000004b,mdl
+
+	; D0 == 1, D1 == 1, C == 1
+	mvi_h_gr  	0xfffffffe,r2
+	set_dbits	0x3
+	set_cc          0x00
+	div1      	r2
+	test_cc		0 0 0 1
+	test_dbits	0x3
+	test_h_gr  	0xfffffffe,r2
+	test_h_dr  	0x00000002,mdh
+	test_h_dr  	0x00000096,mdl
+
+	; remainder is zero
+	mvi_h_gr  	0x00000004,r2
+	set_dbits	0x0
+	set_cc          0x00
+	div1      	r2
+	test_cc		0 1 0 0
+	test_dbits	0x0
+	test_h_gr  	0x00000004,r2
+	test_h_dr  	0x00000000,mdh
+	test_h_dr  	0x0000012d,mdl
+
+	pass
+
+
+
diff --git a/sim/testsuite/sim/fr30/div2.cgs b/sim/testsuite/sim/fr30/div2.cgs
new file mode 100644
index 0000000..03000a2
--- /dev/null
+++ b/sim/testsuite/sim/fr30/div2.cgs
@@ -0,0 +1,120 @@
+# fr30 testcase for div2 $Ri
+# mach(): fr30
+
+	.include "testutils.inc"
+
+	START
+
+	.text
+	.global div2
+div2:
+	; Test div2 $Ri
+	; example from the manual -- all status bits 0
+	mvi_h_gr   	0x00ffffff,r2
+	mvi_h_dr   	0x00ffffff,mdh
+	mvi_h_dr   	0x0000000f,mdl
+	set_dbits	0x0
+	set_cc          0x00
+	div2      	r2
+	test_cc		0 1 0 0
+	test_dbits	0x0
+	test_h_gr  	0x00ffffff,r2
+	test_h_dr  	0x00000000,mdh
+	test_h_dr  	0x0000000f,mdl
+
+	; D0 == 1
+	mvi_h_dr   	0x00ffffff,mdh
+	set_dbits	0x1
+	set_cc          0x00
+	div2      	r2
+	test_cc		0 1 0 0
+	test_dbits	0x1
+	test_h_gr  	0x00ffffff,r2
+	test_h_dr  	0x00000000,mdh
+	test_h_dr  	0x0000000f,mdl
+
+	; D1 == 1
+	mvi_h_dr   	0x00ffffff,mdh
+	set_dbits	0x2
+	set_cc          0x00
+	div2      	r2
+	test_cc		0 0 0 0
+	test_dbits	0x2
+	test_h_gr  	0x00ffffff,r2
+	test_h_dr  	0x00ffffff,mdh
+	test_h_dr  	0x0000000f,mdl
+
+	; D0 == 1, D1 == 1
+	set_dbits	0x3
+	set_cc          0x00
+	div2      	r2
+	test_cc		0 0 0 0
+	test_dbits	0x3
+	test_h_gr  	0x00ffffff,r2
+	test_h_dr  	0x00ffffff,mdh
+	test_h_dr  	0x0000000f,mdl
+
+	; C == 1
+	mvi_h_dr   	0x11ffffee,mdh
+	mvi_h_gr  	0x11ffffef,r2
+	set_dbits	0x0
+	set_cc          0x00
+	div2      	r2
+	test_cc		0 0 0 1
+	test_dbits	0x0
+	test_h_gr  	0x11ffffef,r2
+	test_h_dr  	0x11ffffee,mdh
+	test_h_dr  	0x0000000f,mdl
+
+	; D0 == 1, C == 1
+	mvi_h_dr   	0x23ffffdc,mdh
+	mvi_h_gr  	0x23ffffdd,r2
+	set_dbits	0x1
+	set_cc          0x00
+	div2      	r2
+	test_cc		0 0 0 1
+	test_dbits	0x1
+	test_h_gr  	0x23ffffdd,r2
+	test_h_dr  	0x23ffffdc,mdh
+	test_h_dr  	0x0000000f,mdl
+
+	; D1 == 1, C == 1
+	mvi_h_dr   	0xfffffffd,mdh
+	mvi_h_gr  	0x00000004,r2
+	set_dbits	0x2
+	set_cc          0x00
+	div2      	r2
+	test_cc		0 0 0 1
+	test_dbits	0x2
+	test_h_gr  	0x00000004,r2
+	test_h_dr  	0xfffffffd,mdh
+	test_h_dr  	0x0000000f,mdl
+
+	; D0 == 1, D1 == 1, C == 1
+	mvi_h_dr   	0x00000002,mdh
+	mvi_h_gr  	0xffffffff,r2
+	set_dbits	0x3
+	set_cc          0x00
+	div2      	r2
+	test_cc		0 0 0 1
+	test_dbits	0x3
+	test_h_gr  	0xffffffff,r2
+	test_h_dr  	0x00000002,mdh
+	test_h_dr  	0x0000000f,mdl
+
+	; remainder is zero
+	mvi_h_dr   	0x00000004,mdh
+	mvi_h_gr  	0x00000004,r2
+	set_dbits	0x0
+	set_cc          0x00
+	div2      	r2
+	test_cc		0 1 0 0
+	test_dbits	0x0
+	test_h_gr  	0x00000004,r2
+	test_h_dr  	0x00000000,mdh
+	test_h_dr  	0x0000000f,mdl
+
+	pass
+
+
+
diff --git a/sim/testsuite/sim/fr30/div3.cgs b/sim/testsuite/sim/fr30/div3.cgs
new file mode 100644
index 0000000..ee7da1a
--- /dev/null
+++ b/sim/testsuite/sim/fr30/div3.cgs
@@ -0,0 +1,34 @@
+# fr30 testcase for div3
+# mach(): fr30
+
+	.include "testutils.inc"
+
+	START
+
+	.text
+	.global div3
+div3:
+	; Test div3
+	; example from the manual
+	mvi_h_gr   	0x00ffffff,r2
+	mvi_h_dr   	0x00000000,mdh
+	mvi_h_dr   	0x0000000f,mdl
+	set_dbits	0x0
+	set_cc          0x04
+	div3
+	test_cc		0 1 0 0
+	test_dbits	0x0
+	test_h_gr  	0x00ffffff,r2
+	test_h_dr  	0x00000000,mdh
+	test_h_dr  	0x00000010,mdl
+
+	set_dbits	0x0
+	set_cc          0x00
+	div3
+	test_cc		0 0 0 0
+	test_dbits	0x0
+	test_h_gr  	0x00ffffff,r2
+	test_h_dr  	0x00000000,mdh
+	test_h_dr  	0x00000010,mdl
+
+	pass
diff --git a/sim/testsuite/sim/fr30/div4s.cgs b/sim/testsuite/sim/fr30/div4s.cgs
new file mode 100644
index 0000000..3b98eca
--- /dev/null
+++ b/sim/testsuite/sim/fr30/div4s.cgs
@@ -0,0 +1,34 @@
+# fr30 testcase for div4s
+# mach(): fr30
+
+	.include "testutils.inc"
+
+	START
+
+	.text
+	.global div4s
+div4s:
+	; Test div4s
+	; example from the manual
+	mvi_h_gr   	0x00ffffff,r2
+	mvi_h_dr   	0x00000000,mdh
+	mvi_h_dr   	0x0000000f,mdl
+	set_dbits	0x3
+	set_cc          0x0f
+	div4s
+	test_cc		1 1 1 1
+	test_dbits	0x3
+	test_h_gr  	0x00ffffff,r2
+	test_h_dr  	0x00000000,mdh
+	test_h_dr  	0xfffffff1,mdl
+
+	set_dbits	0x0
+	set_cc          0x00
+	div4s
+	test_cc		0 0 0 0
+	test_dbits	0x0
+	test_h_gr  	0x00ffffff,r2
+	test_h_dr  	0x00000000,mdh
+	test_h_dr  	0xfffffff1,mdl
+
+	pass
diff --git a/sim/testsuite/sim/fr30/testutils.inc b/sim/testsuite/sim/fr30/testutils.inc
index 90e18dd..f335ea1 100644
--- a/sim/testsuite/sim/fr30/testutils.inc
+++ b/sim/testsuite/sim/fr30/testutils.inc
@@ -45,6 +45,12 @@ _start:
 	ldi32 \val,\reg
 	.endm
 
+; Load an immediate value into a dedicated register
+	.macro mvi_h_dr val reg
+	ldi32 \val,r0
+	mov r0,\reg
+	.endm
+
 ; Load a general register into another general register
 	.macro mvr_h_gr src targ
 	mov \src,\targ
@@ -168,3 +174,25 @@ fail\@:
 	fail
 test_cc\@:
 	.endm
+
+; Set the division bits
+	.macro set_dbits val
+	mvr_h_gr ps,r5
+	mvi_h_gr 0xfffff8ff,r4
+	and r4,r5
+	mvi_h_gr \val,r0
+	mvi_h_gr 3,r4
+	and r4,r0
+	lsl 9,r0
+	or r0,r5
+	mvr_h_gr r5,ps
+	.endm
+
+; Test the division bits
+	.macro test_dbits val
+	mvr_h_gr ps,r0
+	lsr 9,r0
+	mvi_h_gr 3,r4
+	and r4,r0
+	test_h_gr \val,r0
+	.endm