Update the machine code decode algorithm using hash table.

1 files changed, 584 insertions, 456 deletions

diff --git a/sim/cr16/interp.c b/sim/cr16/interp.c
index f6397c5..1eed5e5 100644
--- a/sim/cr16/interp.c
+++ b/sim/cr16/interp.c
@@ -14,8 +14,8 @@
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
  
-   You should have received a copy of the GNU General Public License along
-   with this program. If not, see <http://www.gnu.org/licenses/>.  */
+   You should have received a copy of the GNU General Public License 
+   along with this program. If not, see <http://www.gnu.org/licenses/>.  */
 
 #include <signal.h>
 #include "sysdep.h"
@@ -28,8 +28,6 @@
 #include "gdb/signals.h"
 #include "opcode/cr16.h"
 
-enum _leftright { LEFT_FIRST, RIGHT_FIRST };
-
 static char *myname;
 static SIM_OPEN_KIND sim_kind;
 int cr16_debug;
@@ -52,8 +50,10 @@ asection *text;
 bfd_vma text_start;
 bfd_vma text_end;
 
-static void get_operands PARAMS ((operand_desc *s, uint64 mcode, int isize));
-static void do_run PARAMS ((inst *ins, uint64 mc));
+static long hash PARAMS ((uint64 linsn, int));
+static struct hash_entry *lookup_hash PARAMS ((uint64 ins, int size));
+static void get_operands PARAMS ((operand_desc *s, uint64 mcode, int isize, int nops));
+static int do_run PARAMS ((uint64 mc));
 static char *add_commas PARAMS ((char *buf, int sizeof_buf, unsigned long value));
 extern void sim_set_profile PARAMS ((int n));
 extern void sim_set_profile_size PARAMS ((int n));
@@ -77,9 +77,72 @@ extern int (*deprecated_ui_loop_hook) PARAMS ((int signo));
 #define INLINE
 #endif
 #endif
+#define MAX_HASH  16
+
+struct hash_entry
+{
+  struct hash_entry *next;
+  uint32 opcode;
+  uint32 mask;
+  int format;
+  int size;
+  struct simops *ops;
+};
+
+struct hash_entry hash_table[MAX_HASH+1];
+
+INLINE static long
+hash(unsigned long long insn, int format)
+{ 
+  unsigned int i = 4, tmp;
+  if (format)
+    {
+      while ((insn >> i) != 0) i +=4;
+
+      return ((insn >> (i-4)) & 0xf); /* Use last 4 bits as hask key.  */
+    }
+  return ((insn & 0xF)); /* Use last 4 bits as hask key.  */
+}
+
+
+INLINE static struct hash_entry *
+lookup_hash (uint64 ins, int size)
+{
+  uint32 mask;
+  struct hash_entry *h;
+
+  h = &hash_table[hash(ins,1)];
+
+
+  mask = (((1 << (32 - h->mask)) -1) << h->mask);
+
+ /* Adjuest mask for branch with 2 word instructions.  */
+  if ((h->ops->mnimonic != NULL) &&
+      ((streq(h->ops->mnimonic,"b") && h->size == 2)))
+    mask = 0xff0f0000;
+
+
+  while ((ins & mask) != (BIN(h->opcode, h->mask)))
+    {
+      if (h->next == NULL)
+        {
+          State.exception = SIGILL;
+          State.pc_changed = 1; /* Don't increment the PC. */
+          return NULL;
+        }
+      h = h->next;
+
+      mask = (((1 << (32 - h->mask)) -1) << h->mask);
+     /* Adjuest mask for branch with 2 word instructions.  */
+     if ((streq(h->ops->mnimonic,"b")) && h->size == 2)
+       mask = 0xff0f0000;
+
+     }
+   return (h);
+}
 
 INLINE static void
-get_operands (operand_desc *s, uint64 ins, int isize)
+get_operands (operand_desc *s, uint64 ins, int isize, int nops)
 {
   uint32 i, opn = 0, start_bit = 0, op_type = 0; 
   int32 op_size = 0, mask = 0;
@@ -87,211 +150,215 @@ get_operands (operand_desc *s, uint64 ins, int isize)
   if (isize == 1) /* Trunkcate the extra 16 bits of INS.  */
     ins = ins >> 16;
 
-  for (i=0; i < 3; ++i,++opn)
+  for (i=0; i < 4; ++i,++opn)
     {
-      if ((s[opn].op_type == dummy) || (s[opn].op_type > cr16_num_optab))
-         break;
-      else 
-	op_type = s[opn].op_type;
+      if (s[opn].op_type == dummy) break;
 
+      op_type = s[opn].op_type;
       start_bit = s[opn].shift;
       op_size = cr16_optab[op_type].bit_size;
 
       switch (op_type)
-	{
+        {
           case imm3: case imm4: case imm5: case imm6:
-	    {
-	     if (isize == 1)
-	       OP[i] = ((ins >> 4) & ((1 << op_size) -1));
+            {
+             if (isize == 1)
+               OP[i] = ((ins >> 4) & ((1 << op_size) -1));
              else
-	       OP[i] = ((ins >> (32 - start_bit)) & ((1 << op_size) -1));
-
-	     if (OP[i] & ((long)1 << (op_size -1))) 
-	       {
-	         sign_flag = 1;
-		 OP[i] = ~(OP[i]) + 1;
-	       }
-	     OP[i] = (unsigned long int)(OP[i] & (((long)1 << op_size) -1));
+               OP[i] = ((ins >> (32 - start_bit)) & ((1 << op_size) -1));
+
+             if (OP[i] & ((long)1 << (op_size -1))) 
+               {
+                 sign_flag = 1;
+                 OP[i] = ~(OP[i]) + 1;
+               }
+             OP[i] = (unsigned long int)(OP[i] & (((long)1 << op_size) -1));
             }
-	    break;
+            break;
 
           case uimm3: case uimm3_1: case uimm4_1:
-	     if (isize == 1)
-	       OP[i] = ((ins >> 4) & ((1 << op_size) -1));
-             else
-	       OP[i] = ((ins >> (32 - start_bit)) & ((1 << op_size) -1));
-	    break;
+             switch (isize)
+               {
+              case 1:
+               OP[i] = ((ins >> 4) & ((1 << op_size) -1)); break;
+              case 2:
+               OP[i] = ((ins >> (32 - start_bit)) & ((1 << op_size) -1));break;
+              default: /* for case 3.  */
+               OP[i] = ((ins >> (16 + start_bit)) & ((1 << op_size) -1)); break;
+               break;
+               }
+            break;
 
           case uimm4:
-	    switch (isize)
-	      {
-	      case 1:
-	         if (start_bit == 20)
-	           OP[i] = ((ins >> 4) & ((1 << op_size) -1));
-	         else
-		   OP[i] = (ins & ((1 << op_size) -1));
-		 break;
-	      case 2:
-	         OP[i] = ((ins >> start_bit) & ((1 << op_size) -1));
-		 break;
-	      case 3:
-	         OP[i] = ((ins >> (start_bit + 16)) & ((1 << op_size) -1));
-		 break;
-	      default:
-	         OP[i] = ((ins >> start_bit) & ((1 << op_size) -1));
-		 break;
-	      }
-	    break;
+            switch (isize)
+              {
+              case 1:
+                 if (start_bit == 20)
+                   OP[i] = ((ins >> 4) & ((1 << op_size) -1));
+                 else
+                   OP[i] = (ins & ((1 << op_size) -1));
+                 break;
+              case 2:
+                 OP[i] = ((ins >> start_bit) & ((1 << op_size) -1));
+                 break;
+              case 3:
+                 OP[i] = ((ins >> (start_bit + 16)) & ((1 << op_size) -1));
+                 break;
+              default:
+                 OP[i] = ((ins >> start_bit) & ((1 << op_size) -1));
+                 break;
+              }
+            break;
 
           case imm16: case uimm16:
             OP[i] = ins & 0xFFFF;
-	    break;
+            break;
 
           case uimm20: case imm20:
-	    OP[i] = ins & (((long)1 << op_size) - 1);
-	    break;
+            OP[i] = ins & (((long)1 << op_size) - 1);
+            break;
 
           case imm32: case uimm32:
             OP[i] = ins & 0xFFFFFFFF;
-	    break;
+            break;
 
-	  case uimm5: break; /*NOT USED.  */
+          case uimm5: break; /*NOT USED.  */
             OP[i] = ins & ((1 << op_size) - 1); break;
 
           case disps5: 
             OP[i] = (ins >> 4) & ((1 << 4) - 1); 
             OP[i] = (OP[i] * 2) + 2;
-	    if (OP[i] & ((long)1 << 5)) 
-	      {
-	        sign_flag = 1;
-	        OP[i] = ~(OP[i]) + 1;
-	        OP[i] = (unsigned long int)(OP[i] & 0x1F);
-	      }
-	    break;
-
-	  case dispe9: 
-	    OP[i] = ((((ins >> 8) & 0xf) << 4) | (ins & 0xf)); 
-	    OP[i] <<= 1;
-	    if (OP[i] & ((long)1 << 8)) 
-	      {
-	        sign_flag = 1;
-	        OP[i] = ~(OP[i]) + 1;
-	        OP[i] = (unsigned long int)(OP[i] & 0xFF);
-	      }
-	    break;
-
-	  case disps17: 
-	    OP[i] = (ins & 0xFFFF);
-	    if (OP[i] & 1) 
-	      {
-	        OP[i] = (OP[i] & 0xFFFE);
-	        sign_flag = 1;
-	        OP[i] = ~(OP[i]) + 1;
-	        OP[i] = (unsigned long int)(OP[i] & 0xFFFF);
+            if (OP[i] & ((long)1 << 5)) 
+              {
+                sign_flag = 1;
+                OP[i] = ~(OP[i]) + 1;
+                OP[i] = (unsigned long int)(OP[i] & 0x1F);
+              }
+            break;
+
+          case dispe9: 
+            OP[i] = ((((ins >> 8) & 0xf) << 4) | (ins & 0xf)); 
+            OP[i] <<= 1;
+            if (OP[i] & ((long)1 << 8)) 
+              {
+                sign_flag = 1;
+                OP[i] = ~(OP[i]) + 1;
+                OP[i] = (unsigned long int)(OP[i] & 0xFF);
+              }
+            break;
+
+          case disps17: 
+            OP[i] = (ins & 0xFFFF);
+            if (OP[i] & 1) 
+              {
+                OP[i] = (OP[i] & 0xFFFE);
+                sign_flag = 1;
+                OP[i] = ~(OP[i]) + 1;
+                OP[i] = (unsigned long int)(OP[i] & 0xFFFF);
               }
-	    break;
-
-	  case disps25: 
-	    if (isize == 2)
-	      OP[i] = (ins & 0xFFFFFF);
-	    else 
-	      OP[i] = (ins & 0xFFFF) | (((ins >> 24) & 0xf) << 16) |
-	              (((ins >> 16) & 0xf) << 20);
-
-	    if (OP[i] & 1) 
-	      {
-	        OP[i] = (OP[i] & 0xFFFFFE);
-	        sign_flag = 1;
-	        OP[i] = ~(OP[i]) + 1;
-	        OP[i] = (unsigned long int)(OP[i] & 0xFFFFFF);
+            break;
+
+          case disps25: 
+            if (isize == 2)
+              OP[i] = (ins & 0xFFFFFF);
+            else 
+              OP[i] = (ins & 0xFFFF) | (((ins >> 24) & 0xf) << 16) |
+                      (((ins >> 16) & 0xf) << 20);
+
+            if (OP[i] & 1) 
+              {
+                OP[i] = (OP[i] & 0xFFFFFE);
+                sign_flag = 1;
+                OP[i] = ~(OP[i]) + 1;
+                OP[i] = (unsigned long int)(OP[i] & 0xFFFFFF);
               }
-	    break;
+            break;
 
           case abs20:
-	    if (isize == 3)
+            if (isize == 3)
               OP[i] = (ins) & 0xFFFFF; 
-	    else
+            else
               OP[i] = (ins >> start_bit) & 0xFFFFF;
-	    break;
+            break;
           case abs24:
-	    if (isize == 3)
-	      OP[i] = ((ins & 0xFFFF) | (((ins >> 16) & 0xf) << 20)
-	               | (((ins >> 24) & 0xf) << 16));
-	    else
-	      OP[i] = (ins >> 16) & 0xFFFFFF;
-	    break;
+            if (isize == 3)
+              OP[i] = ((ins & 0xFFFF) | (((ins >> 16) & 0xf) << 20)
+                       | (((ins >> 24) & 0xf) << 16));
+            else
+              OP[i] = (ins >> 16) & 0xFFFFFF;
+            break;
 
           case rra:
           case rbase: break; /* NOT USED.  */
           case rbase_disps20:  case rbase_dispe20:
           case rpbase_disps20: case rpindex_disps20:
-	    OP[i] = ((((ins >> 24)&0xf) << 16)|((ins) & 0xFFFF));
-	    OP[++i] = (ins >> 16) & 0xF;     /* get 4 bit for reg.  */
-	    break;
+            OP[i] = ((((ins >> 24)&0xf) << 16)|((ins) & 0xFFFF));
+            OP[++i] = (ins >> 16) & 0xF;     /* get 4 bit for reg.  */
+            break;
           case rpbase_disps0:
-	    OP[i] = 0;                       /* 4 bit disp const.  */
-	    OP[++i] = (ins) & 0xF;           /* get 4 bit for reg.  */
-	    break;
+            OP[i] = 0;                       /* 4 bit disp const.  */
+            OP[++i] = (ins) & 0xF;           /* get 4 bit for reg.  */
+            break;
           case rpbase_dispe4:
-	    OP[i] = ((ins >> 8) & 0xF) * 2;  /* 4 bit disp const.   */
-	    OP[++i] = (ins) & 0xF;           /* get 4 bit for reg.  */
-	    break;
+            OP[i] = ((ins >> 8) & 0xF) * 2;  /* 4 bit disp const.   */
+            OP[++i] = (ins) & 0xF;           /* get 4 bit for reg.  */
+            break;
           case rpbase_disps4:
-	    OP[i] = ((ins >> 8) & 0xF);      /* 4 bit disp const.  */
-	    OP[++i] = (ins) & 0xF;           /* get 4 bit for reg.  */
-	    break;
+            OP[i] = ((ins >> 8) & 0xF);      /* 4 bit disp const.  */
+            OP[++i] = (ins) & 0xF;           /* get 4 bit for reg.  */
+            break;
           case rpbase_disps16:
-	    OP[i] = (ins) & 0xFFFF;
-	    OP[++i] = (ins >> 16) & 0xF;     /* get 4 bit for reg.  */
-	    break;
+            OP[i] = (ins) & 0xFFFF;
+            OP[++i] = (ins >> 16) & 0xF;     /* get 4 bit for reg.  */
+            break;
           case rpindex_disps0:
-	    OP[i] = 0;
-	    OP[++i] = (ins >> 4) & 0xF;      /* get 4 bit for reg.  */
-	    OP[++i] = (ins >> 8) & 0x1;      /* get 1 bit for index-reg.  */
-	    break;
+            OP[i] = 0;
+            OP[++i] = (ins >> 4) & 0xF;      /* get 4 bit for reg.  */
+            OP[++i] = (ins >> 8) & 0x1;      /* get 1 bit for index-reg.  */
+            break;
           case rpindex_disps14:
-	    OP[i] = (ins) & 0x3FFF;
-	    OP[++i] = (ins >> 14) & 0x1;     /* get 1 bit for index-reg.  */
-	    OP[++i] = (ins >> 16) & 0xF;     /* get 4 bit for reg.  */
+            OP[i] = (ins) & 0x3FFF;
+            OP[++i] = (ins >> 14) & 0x1;     /* get 1 bit for index-reg.  */
+            OP[++i] = (ins >> 16) & 0xF;     /* get 4 bit for reg.  */
           case rindex7_abs20:
           case rindex8_abs20:
-	    OP[i] = (ins) & 0xFFFFF;
-	    OP[++i] = (ins >> 24) & 0x1;     /* get 1 bit for index-reg.  */
-	    OP[++i] = (ins >> 20) & 0xF;     /* get 4 bit for reg.  */
-	    break;
+            OP[i] = (ins) & 0xFFFFF;
+            OP[++i] = (ins >> 24) & 0x1;     /* get 1 bit for index-reg.  */
+            OP[++i] = (ins >> 20) & 0xF;     /* get 4 bit for reg.  */
+            break;
           case regr: case regp: case pregr: case pregrp:
-	      switch(isize)
-		{
-		  case 1: 
-		    if (start_bit == 20) OP[i] = (ins >> 4) & 0xF;
-		    else if (start_bit == 16) OP[i] = ins & 0xF;
-		    break;
-		  case 2: OP[i] = (ins >>  start_bit) & 0xF; break;
-		  case 3: OP[i] = (ins >> (start_bit + 16)) & 0xF; break;
-		}
-	       break;
+              switch(isize)
+                {
+                  case 1: 
+                    if (start_bit == 20) OP[i] = (ins >> 4) & 0xF;
+                    else if (start_bit == 16) OP[i] = ins & 0xF;
+                    break;
+                  case 2: OP[i] = (ins >>  start_bit) & 0xF; break;
+                  case 3: OP[i] = (ins >> (start_bit + 16)) & 0xF; break;
+                }
+               break;
           case cc: 
-	    {
-	      if (isize == 1) OP[i] = (ins >> 4) & 0xF;
-	      else if (isize == 2)  OP[i] = (ins >> start_bit)  & 0xF;
-	      else  OP[i] = (ins >> (start_bit + 16)) & 0xF; 
-	      break;
-	    }
-	  default: break;
-	}
+            {
+              if (isize == 1) OP[i] = (ins >> 4) & 0xF;
+              else if (isize == 2)  OP[i] = (ins >> start_bit)  & 0xF;
+              else  OP[i] = (ins >> (start_bit + 16)) & 0xF; 
+              break;
+            }
+          default: break;
+        }
      
-      /* For ESC on uimm4_1 operand */
+      /* For ESC on uimm4_1 operand.  */
       if (op_type == uimm4_1)
-	if (OP[i] == 9)
-	   OP[i] = -1;
+        if (OP[i] == 9)
+           OP[i] = -1;
+
+      /* For increment by 1.  */
+      if ((op_type == pregr) || (op_type == pregrp))
+          OP[i] += 1;
    }
   /* FIXME: for tracing, update values that need to be updated each
             instruction decode cycle */
-#if 0 // DEBUG
-  (*cr16_callback->printf_filtered) (cr16_callback, "OP0=0x%X\t,OP1=0x%X\t,OP2=0x%X\t,OP3=0X%X\n",OP[0],OP[1],OP[2],OP[3]);
-#endif
   State.trace.psw = PSR;
-
 }
 
 bfd_vma
@@ -302,13 +369,13 @@ decode_pc ()
     {
       init_text_p = 1;
       for (s = prog_bfd->sections; s; s = s->next)
-	if (strcmp (bfd_get_section_name (prog_bfd, s), ".text") == 0)
-	  {
-	    text = s;
-	    text_start = bfd_get_section_vma (prog_bfd, s);
-	    text_end = text_start + bfd_section_size (prog_bfd, s);
-	    break;
-	   }
+        if (strcmp (bfd_get_section_name (prog_bfd, s), ".text") == 0)
+          {
+            text = s;
+            text_start = bfd_get_section_vma (prog_bfd, s);
+            text_end = text_start + bfd_section_size (prog_bfd, s);
+            break;
+           }
      }
 
   return (PC) + text_start;
@@ -316,35 +383,44 @@ decode_pc ()
 
 
 
-static void
-do_run(inst *instruction, uint64 mcode)
+static int
+do_run(uint64 mcode)
 {
   struct simops *s= Simops;
+  struct hash_entry *h;
   char func[12]="\0";
+  uint8 *iaddr;
 #ifdef DEBUG
   if ((cr16_debug & DEBUG_INSTRUCTION) != 0)
-    (*cr16_callback->printf_filtered) (cr16_callback, "do_long 0x%x\n", instruction);
+    (*cr16_callback->printf_filtered) (cr16_callback, "do_long 0x%x\n", mcode);
 #endif
   
-  /* Re-set OP list */
+   h =  lookup_hash(mcode, 1);
+
+   if ((h == NULL) || (h->opcode == NULL)) return 0;
+
+   if (h->size == 3)
+    {
+      iaddr = imem_addr ((uint32)PC + 2);
+       mcode = (mcode << 16) | get_longword( iaddr );
+    }
+
+  /* Re-set OP list.  */
   OP[0] = OP[1] = OP[2] = OP[3] = sign_flag = 0;
 
-  /* for push/pop/pushrtn with RA instructions */
-  if ((INST_HAS_REG_LIST) && (mcode & 0x800000))
-    OP[2] = 1; /* Set 1 for RA operand */
+  /* for push/pop/pushrtn with RA instructions. */
+  if ((h->format & REG_LIST) && (mcode & 0x800000))
+    OP[2] = 1; /* Set 1 for RA operand.  */
 
-  get_operands (&instruction->operands, mcode, instruction->size);
+  /* numops == 0 means, no operands.  */
+  if (((h->ops) != NULL) && (((h->ops)->numops) != 0))
+    get_operands ((h->ops)->operands, mcode, h->size, (h->ops)->numops);
 
-  State.ins_type = instruction->flags;
-  //ins_type_counters[ (int)State.ins_type ]++;
-  sprintf(func,"OP_%X_%X",instruction->match,(32 - instruction->match_bits));
-  /* Check for appropriate opcode function */
-  for ( ;s->opcode!=0;s++)
-  {
-    if (strcmp(s->fname,func) == 0)
-       break;
-  }
-  (s->func)();
+  //State.ins_type = h->flags;
+
+  (h->ops->func)();
+
+  return h->size;
 }
 
 static char *
@@ -357,8 +433,8 @@ add_commas(char *buf, int sizeof_buf, unsigned long value)
   do {
     if (comma-- == 0)
       {
-	*--endbuf = ',';
-	comma = 2;
+        *--endbuf = ',';
+        comma = 2;
       }
 
     *--endbuf = (value % 10) + '0';
@@ -374,17 +450,17 @@ sim_size (int power)
   for (i = 0; i < IMEM_SEGMENTS; i++)
     {
       if (State.mem.insn[i])
-	free (State.mem.insn[i]);
+        free (State.mem.insn[i]);
     }
   for (i = 0; i < DMEM_SEGMENTS; i++)
     {
       if (State.mem.data[i])
-	free (State.mem.data[i]);
+        free (State.mem.data[i]);
     }
   for (i = 0; i < UMEM_SEGMENTS; i++)
     {
       if (State.mem.unif[i])
-	free (State.mem.unif[i]);
+        free (State.mem.unif[i]);
     }
   /* Always allocate dmem segment 0.  This contains the IMAP and DMAP
      registers. */
@@ -408,13 +484,13 @@ static void
 set_dmap_register (int reg_nr, unsigned long value)
 {
   uint8 *raw = map_memory (SIM_CR16_MEMORY_DATA
-			   + DMAP0_OFFSET + 2 * reg_nr);
+                           + DMAP0_OFFSET + 2 * reg_nr);
   WRITE_16 (raw, value);
 #ifdef DEBUG
   if ((cr16_debug & DEBUG_MEMORY))
     {
       (*cr16_callback->printf_filtered)
-	(cr16_callback, "mem: dmap%d=0x%04lx\n", reg_nr, value);
+        (cr16_callback, "mem: dmap%d=0x%04lx\n", reg_nr, value);
     }
 #endif
 }
@@ -423,7 +499,7 @@ static unsigned long
 dmap_register (void *regcache, int reg_nr)
 {
   uint8 *raw = map_memory (SIM_CR16_MEMORY_DATA
-			   + DMAP0_OFFSET + 2 * reg_nr);
+                           + DMAP0_OFFSET + 2 * reg_nr);
   return READ_16 (raw);
 }
 
@@ -431,13 +507,13 @@ static void
 set_imap_register (int reg_nr, unsigned long value)
 {
   uint8 *raw = map_memory (SIM_CR16_MEMORY_DATA
-			   + IMAP0_OFFSET + 2 * reg_nr);
+                           + IMAP0_OFFSET + 2 * reg_nr);
   WRITE_16 (raw, value);
 #ifdef DEBUG
   if ((cr16_debug & DEBUG_MEMORY))
     {
       (*cr16_callback->printf_filtered)
-	(cr16_callback, "mem: imap%d=0x%04lx\n", reg_nr, value);
+        (cr16_callback, "mem: imap%d=0x%04lx\n", reg_nr, value);
     }
 #endif
 }
@@ -446,7 +522,7 @@ static unsigned long
 imap_register (void *regcache, int reg_nr)
 {
   uint8 *raw = map_memory (SIM_CR16_MEMORY_DATA
-			   + IMAP0_OFFSET + 2 * reg_nr);
+                           + IMAP0_OFFSET + 2 * reg_nr);
   return READ_16 (raw);
 }
 
@@ -485,11 +561,11 @@ set_spu_register  (unsigned long value)
 
 unsigned long
 sim_cr16_translate_dmap_addr (unsigned long offset,
-			      int nr_bytes,
-			      unsigned long *phys,
-			      void *regcache,
-			      unsigned long (*dmap_register) (void *regcache,
-							      int reg_nr))
+                              int nr_bytes,
+                              unsigned long *phys,
+                              void *regcache,
+                              unsigned long (*dmap_register) (void *regcache,
+                                                              int reg_nr))
 {
   short map;
   int regno;
@@ -522,22 +598,22 @@ sim_cr16_translate_dmap_addr (unsigned long offset,
       int sp = ((map & 0x3000) >> 12);
       int segno = (map & 0x3ff);
       switch (sp)
-	{
-	case 0: /* 00: Unified memory */
-	  *phys = SIM_CR16_MEMORY_UNIFIED + (segno * DMAP_BLOCK_SIZE) + offset;
-	  last_to = "unified";
-	  break;
-	case 1: /* 01: Instruction Memory */
-	  *phys = SIM_CR16_MEMORY_INSN + (segno * DMAP_BLOCK_SIZE) + offset;
-	  last_to = "chip-insn";
-	  break;
-	case 2: /* 10: Internal data memory */
-	  *phys = SIM_CR16_MEMORY_DATA + (segno << 16) + (regno * DMAP_BLOCK_SIZE) + offset;
-	  last_to = "chip-data";
-	  break;
-	case 3: /* 11: Reserved */
-	  return 0;
-	}
+        {
+        case 0: /* 00: Unified memory */
+          *phys = SIM_CR16_MEMORY_UNIFIED + (segno * DMAP_BLOCK_SIZE) + offset;
+          last_to = "unified";
+          break;
+        case 1: /* 01: Instruction Memory */
+          *phys = SIM_CR16_MEMORY_INSN + (segno * DMAP_BLOCK_SIZE) + offset;
+          last_to = "chip-insn";
+          break;
+        case 2: /* 10: Internal data memory */
+          *phys = SIM_CR16_MEMORY_DATA + (segno << 16) + (regno * DMAP_BLOCK_SIZE) + offset;
+          last_to = "chip-data";
+          break;
+        case 3: /* 11: Reserved */
+          return 0;
+        }
     }
 #endif
   return nr_bytes;
@@ -548,11 +624,11 @@ sim_cr16_translate_dmap_addr (unsigned long offset,
 
 unsigned long
 sim_cr16_translate_imap_addr (unsigned long offset,
-			      int nr_bytes,
-			      unsigned long *phys,
-			      void *regcache,
-			      unsigned long (*imap_register) (void *regcache,
-							      int reg_nr))
+                              int nr_bytes,
+                              unsigned long *phys,
+                              void *regcache,
+                              unsigned long (*imap_register) (void *regcache,
+                                                              int reg_nr))
 {
   short map;
   int regno;
@@ -591,8 +667,8 @@ sim_cr16_translate_imap_addr (unsigned long offset,
       offset = (offset % 0x800);
       *phys = SIM_CR16_MEMORY_INSN + offset;
       if (offset + nr_bytes > 0x800)
-	/* don't cross VM boundary */
-	nr_bytes = 0x800 - offset;
+        /* don't cross VM boundary */
+        nr_bytes = 0x800 - offset;
       last_to = "test-insn";
       break;
     }
@@ -600,14 +676,12 @@ sim_cr16_translate_imap_addr (unsigned long offset,
 }
 
 unsigned long
-sim_cr16_translate_addr (unsigned long memaddr,
-			 int nr_bytes,
-			 unsigned long *targ_addr,
-			 void *regcache,
-			 unsigned long (*dmap_register) (void *regcache,
-							 int reg_nr),
-			 unsigned long (*imap_register) (void *regcache,
-							 int reg_nr))
+sim_cr16_translate_addr (unsigned long memaddr, int nr_bytes,
+                         unsigned long *targ_addr, void *regcache,
+                         unsigned long (*dmap_register) (void *regcache,
+                                                         int reg_nr),
+                         unsigned long (*imap_register) (void *regcache,
+                                                         int reg_nr))
 {
   unsigned long phys;
   unsigned long seg;
@@ -625,59 +699,59 @@ sim_cr16_translate_addr (unsigned long memaddr,
   if (old_segment_mapping)
     {
       switch (seg)
-	{
-	case 0x00: /* DMAP translated memory */
-	  seg = 0x10;
-	  break;
-	case 0x01: /* IMAP translated memory */
-	  seg = 0x11;
-	  break;
-	case 0x10: /* On-chip data memory */
-	  seg = 0x02;
-	  break;
-	case 0x11: /* On-chip insn memory */
-	  seg = 0x01;
-	  break;
-	case 0x12: /* Unified memory */
-	  seg = 0x00;
-	  break;
-	}
+        {
+        case 0x00: /* DMAP translated memory */
+          seg = 0x10;
+          break;
+        case 0x01: /* IMAP translated memory */
+          seg = 0x11;
+          break;
+        case 0x10: /* On-chip data memory */
+          seg = 0x02;
+          break;
+        case 0x11: /* On-chip insn memory */
+          seg = 0x01;
+          break;
+        case 0x12: /* Unified memory */
+          seg = 0x00;
+          break;
+        }
     }
 
   switch (seg)
     {
-    case 0x00:			/* Physical unified memory */
+    case 0x00:                        /* Physical unified memory */
       last_from = "phys-unified";
       last_to = "unified";
       phys = SIM_CR16_MEMORY_UNIFIED + off;
       if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
-	nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
+        nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
       break;
 
-    case 0x01:			/* Physical instruction memory */
+    case 0x01:                        /* Physical instruction memory */
       last_from = "phys-insn";
       last_to = "chip-insn";
       phys = SIM_CR16_MEMORY_INSN + off;
       if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
-	nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
+        nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
       break;
 
-    case 0x02:			/* Physical data memory segment */
+    case 0x02:                        /* Physical data memory segment */
       last_from = "phys-data";
       last_to = "chip-data";
       phys = SIM_CR16_MEMORY_DATA + off;
       if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
-	nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
+        nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
       break;
 
-    case 0x10:			/* in logical data address segment */
+    case 0x10:                        /* in logical data address segment */
       nr_bytes = sim_cr16_translate_dmap_addr (off, nr_bytes, &phys, regcache,
-					       dmap_register);
+                                               dmap_register);
       break;
 
-    case 0x11:			/* in logical instruction address segment */
+    case 0x11:                        /* in logical instruction address segment */
       nr_bytes = sim_cr16_translate_imap_addr (off, nr_bytes, &phys, regcache,
-					       imap_register);
+                                               imap_register);
       break;
 
     default:
@@ -705,35 +779,35 @@ map_memory (unsigned phys_addr)
       
     case 0x00: /* Unified memory */
       {
-	memory = &State.mem.unif[(phys_addr / SEGMENT_SIZE) % UMEM_SEGMENTS];
-	last_segname = "umem";
-	break;
+        memory = &State.mem.unif[(phys_addr / SEGMENT_SIZE) % UMEM_SEGMENTS];
+        last_segname = "umem";
+        break;
       }
     
     case 0x01: /* On-chip insn memory */
       {
-	memory = &State.mem.insn[(phys_addr / SEGMENT_SIZE) % IMEM_SEGMENTS];
-	last_segname = "imem";
-	break;
+        memory = &State.mem.insn[(phys_addr / SEGMENT_SIZE) % IMEM_SEGMENTS];
+        last_segname = "imem";
+        break;
       }
     
     case 0x02: /* On-chip data memory */
       {
-	if ((phys_addr & 0xff00) == 0xff00)
-	  {
-	    phys_addr = (phys_addr & 0xffff);
-	    if (phys_addr == DMAP2_SHADDOW)
-	      {
-		phys_addr = DMAP2_OFFSET;
-		last_segname = "dmap";
-	      }
-	    else
-	      last_segname = "reg";
-	  }
-	else
-	  last_segname = "dmem";
-	memory = &State.mem.data[(phys_addr / SEGMENT_SIZE) % DMEM_SEGMENTS];
-	break;
+        if ((phys_addr & 0xff00) == 0xff00)
+          {
+            phys_addr = (phys_addr & 0xffff);
+            if (phys_addr == DMAP2_SHADDOW)
+              {
+                phys_addr = DMAP2_OFFSET;
+                last_segname = "dmap";
+              }
+            else
+              last_segname = "reg";
+          }
+        else
+          last_segname = "dmem";
+        memory = &State.mem.data[(phys_addr / SEGMENT_SIZE) % DMEM_SEGMENTS];
+        break;
       }
     
     default:
@@ -746,10 +820,10 @@ map_memory (unsigned phys_addr)
     {
       *memory = calloc (1, SEGMENT_SIZE);
       if (*memory == NULL)
-	{
-	  (*cr16_callback->printf_filtered) (cr16_callback, "Malloc failed.\n");
-	  return State.mem.fault;
-	}
+        {
+          (*cr16_callback->printf_filtered) (cr16_callback, "Malloc failed.\n");
+          return State.mem.fault;
+        }
     }
   
   offset = (phys_addr % SEGMENT_SIZE);
@@ -766,15 +840,15 @@ map_memory (unsigned phys_addr)
 
 static int
 xfer_mem (SIM_ADDR virt,
-	  unsigned char *buffer,
-	  int size,
-	  int write_p)
+          unsigned char *buffer,
+          int size,
+          int write_p)
 {
   uint8 *memory;
   unsigned long phys;
   int phys_size;
   phys_size = sim_cr16_translate_addr (virt, size, &phys, NULL,
-				       dmap_register, imap_register);
+                                       dmap_register, imap_register);
   if (phys_size == 0)
     return 0;
 
@@ -784,12 +858,12 @@ xfer_mem (SIM_ADDR virt,
   if ((cr16_debug & DEBUG_INSTRUCTION) != 0)
     {
       (*cr16_callback->printf_filtered)
-	(cr16_callback,
-	 "sim_%s %d bytes: 0x%08lx (%s) -> 0x%08lx (%s) -> 0x%08lx (%s)\n",
-	     (write_p ? "write" : "read"),
-	 phys_size, virt, last_from,
-	 phys, last_to,
-	 (long) memory, last_segname);
+        (cr16_callback,
+         "sim_%s %d bytes: 0x%08lx (%s) -> 0x%08lx (%s) -> 0x%08lx (%s)\n",
+             (write_p ? "write" : "read"),
+         phys_size, virt, last_from,
+         phys, last_to,
+         (long) memory, last_segname);
     }
 #endif
 
@@ -828,11 +902,11 @@ sim_read (sd, addr, buffer, size)
   return xfer_mem( addr, buffer, size, 0);
 }
 
-
 SIM_DESC
 sim_open (SIM_OPEN_KIND kind, struct host_callback_struct *callback, struct bfd *abfd, char **argv)
 {
   struct simops *s;
+  struct hash_entry *h;
   static int init_p = 0;
   char **p;
 
@@ -848,18 +922,124 @@ sim_open (SIM_OPEN_KIND kind, struct host_callback_struct *callback, struct bfd
   for (p = argv + 1; *p; ++p)
     {
       if (strcmp (*p, "-oldseg") == 0)
-	old_segment_mapping = 1;
+        old_segment_mapping = 1;
 #ifdef DEBUG
       else if (strcmp (*p, "-t") == 0)
-	cr16_debug = DEBUG;
+        cr16_debug = DEBUG;
       else if (strncmp (*p, "-t", 2) == 0)
-	cr16_debug = atoi (*p + 2);
+        cr16_debug = atoi (*p + 2);
 #endif
       else
-	(*cr16_callback->printf_filtered) (cr16_callback, "ERROR: unsupported option(s): %s\n",*p);
+        (*cr16_callback->printf_filtered) (cr16_callback, "ERROR: unsupported option(s): %s\n",*p);
     }
 #endif
   
+  /* put all the opcodes in the hash table.  */
+  if (!init_p++)
+    {
+      for (s = Simops; s->func; s++)
+        {
+          switch(32 - s->mask)
+            {
+            case 0x4:
+               h = &hash_table[hash(s->opcode, 0)]; 
+               break;
+
+            case 0x7:
+               if (((s->opcode << 1) >> 4) != 0)
+                  h = &hash_table[hash((s->opcode << 1) >> 4, 0)];
+               else
+                  h = &hash_table[hash((s->opcode << 1), 0)];
+               break;
+
+            case 0x8:
+               if ((s->opcode >> 4) != 0)
+                  h = &hash_table[hash(s->opcode >> 4, 0)];
+               else
+                  h = &hash_table[hash(s->opcode, 0)];
+               break;
+
+            case 0x9:
+               if (((s->opcode  >> 1) >> 4) != 0)
+                 h = &hash_table[hash((s->opcode >>1) >> 4, 0)]; 
+               else 
+                 h = &hash_table[hash((s->opcode >> 1), 0)]; 
+               break;
+
+            case 0xa:
+               if ((s->opcode >> 8) != 0)
+                 h = &hash_table[hash(s->opcode >> 8, 0)];
+               else if ((s->opcode >> 4) != 0)
+                 h = &hash_table[hash(s->opcode >> 4, 0)];
+               else
+                 h = &hash_table[hash(s->opcode, 0)]; 
+               break;
+
+            case 0xc:
+               if ((s->opcode >> 8) != 0)
+                 h = &hash_table[hash(s->opcode >> 8, 0)];
+               else if ((s->opcode >> 4) != 0)
+                 h = &hash_table[hash(s->opcode >> 4, 0)];
+               else
+                 h = &hash_table[hash(s->opcode, 0)];
+               break;
+
+            case 0xd:
+               if (((s->opcode >> 1) >> 8) != 0)
+                 h = &hash_table[hash((s->opcode >>1) >> 8, 0)];
+               else if (((s->opcode >> 1) >> 4) != 0)
+                 h = &hash_table[hash((s->opcode >>1) >> 4, 0)];
+               else
+                 h = &hash_table[hash((s->opcode >>1), 0)];
+               break;
+
+            case 0x10:
+               if ((s->opcode >> 0xc) != 0)
+                 h = &hash_table[hash(s->opcode >> 12, 0)]; 
+               else if ((s->opcode >> 8) != 0)
+                 h = &hash_table[hash(s->opcode >> 8, 0)];
+               else if ((s->opcode >> 4) != 0)
+                 h = &hash_table[hash(s->opcode >> 4, 0)];
+               else 
+                 h = &hash_table[hash(s->opcode, 0)];
+               break;
+
+            case 0x14:
+               if ((s->opcode >> 16) != 0)
+                 h = &hash_table[hash(s->opcode >> 16, 0)];
+               else if ((s->opcode >> 12) != 0)
+                 h = &hash_table[hash(s->opcode >> 12, 0)];
+               else if ((s->opcode >> 8) != 0)
+                 h = &hash_table[hash(s->opcode >> 8, 0)];
+               else if ((s->opcode >> 4) != 0)
+                 h = &hash_table[hash(s->opcode >> 4, 0)];
+               else 
+                 h = &hash_table[hash(s->opcode, 0)];
+               break;
+            default:
+              break;
+            }
+      
+          /* go to the last entry in the chain.  */
+          while (h->next)
+            h = h->next;
+
+          if (h->ops)
+            {
+              h->next = (struct hash_entry *) calloc(1,sizeof(struct hash_entry));
+              if (!h->next)
+                perror ("malloc failure");
+
+              h = h->next;
+            }
+          h->ops = s;
+          h->mask = s->mask;
+          h->opcode = s->opcode;
+          h->format = s->format;
+          h->size = s->size;
+        }
+    }
+
   /* reset the processor state */
   if (!State.mem.data[0])
     sim_size (1);
@@ -907,7 +1087,7 @@ dmem_addr (uint32 offset)
      is uint16 this is modulo'ed onto 0x0e5d. */
 
   phys_size = sim_cr16_translate_dmap_addr (offset, 1, &phys, NULL,
-					    dmap_register);
+                                            dmap_register);
   if (phys_size == 0)
     {
       mem = State.mem.fault;
@@ -918,11 +1098,11 @@ dmem_addr (uint32 offset)
   if ((cr16_debug & DEBUG_MEMORY))
     {
       (*cr16_callback->printf_filtered)
-	(cr16_callback,
-	 "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
-	 offset, last_from,
-	 phys, phys_size, last_to,
-	 (long) mem, last_segname);
+        (cr16_callback,
+         "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
+         offset, last_from,
+         phys, phys_size, last_to,
+         (long) mem, last_segname);
     }
 #endif
   return mem;
@@ -934,7 +1114,7 @@ imem_addr (uint32 offset)
   unsigned long phys;
   uint8 *mem;
   int phys_size = sim_cr16_translate_imap_addr (offset, 1, &phys, NULL,
-						imap_register);
+                                                imap_register);
   if (phys_size == 0)
     {
       return State.mem.fault;
@@ -944,11 +1124,11 @@ imem_addr (uint32 offset)
   if ((cr16_debug & DEBUG_MEMORY))
     {
       (*cr16_callback->printf_filtered)
-	(cr16_callback,
-	 "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
-	 offset, last_from,
-	 phys, phys_size, last_to,
-	 (long) mem, last_segname);
+        (cr16_callback,
+         "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
+         offset, last_from,
+         phys, phys_size, last_to,
+         (long) mem, last_segname);
     }
 #endif
   return mem;
@@ -969,8 +1149,8 @@ sim_stop (sd)
 void
 sim_resume (SIM_DESC sd, int step, int siggnal)
 {
-  uint32 mask = 0, ins_found = 0;
-  uint64 mcode=0;
+  uint32 curr_ins_size = 0;
+  uint64 mcode = 0;
   uint8 *iaddr;
 
 #ifdef DEBUG
@@ -1009,94 +1189,42 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
   do
     {
       iaddr = imem_addr ((uint32)PC);
-      ins_found = 0;
       if (iaddr == State.mem.fault)
- 	{
- 	  State.exception = SIGBUS;
- 	  break;
- 	}
+        {
+          State.exception = SIGBUS;
+          break;
+        }
  
       mcode = get_longword( iaddr ); 
  
       State.pc_changed = 0;
       
-      /* Start searching from end of instruction table.  */
-      const inst *instruction = &cr16_instruction[NUMOPCODES - 2];
-
-      /* Loop over instruction table until a full match is found.  */
-      while (instruction >= cr16_instruction)
-        {
-           mask = (((1 << (32 - instruction->match_bits)) -1) <<
-                   instruction->match_bits);
-
-          /* Adjuest mask for branch with 2 word instructions.  */
-	  if ((IS_INSN_MNEMONIC("b") && instruction->size == 2))
-	     mask = 0xff0f0000;
-
-	  if ((mcode & mask) == (BIN(instruction->match, instruction->match_bits)))
-	    {
-	      ins_found = 1;
-	      break; 
-	    }
-	  else
-	    instruction--;
-	}
+      curr_ins_size = do_run(mcode);
 
 #if CR16_DEBUG
  (*cr16_callback->printf_filtered) (cr16_callback, "INS: PC=0x%X, mcode=0x%X\n",PC,mcode); 
 #endif
-       if ((mcode == 0x0L) /*|| (!ins_found )*/)
-	{
-	  State.exception = SIG_CR16_EXIT; /* exit trap */
-          break;
-        }
 
-       /* Check if the ins_found is '0', then set illigel instruction trap */
-       if ( !ins_found )
-	 State.exception = SIGILL;
-       else
-	 {
-	   /* For 3 word instructions only */
-	   if (instruction->size == 3)
-	     {
-               iaddr = imem_addr ((uint32)PC + 2);
-               mcode = (mcode << 16) | get_longword( iaddr );
-	     }
-
-	   do_run(instruction, mcode);
-	 }
-
-      /* If the PC of the current instruction matches RPT_E then
-	 schedule a branch to the loop start.  If one of those
-	 instructions happens to be a branch, than that instruction
-	 will be ignored */
       if (!State.pc_changed)
-	{
-	  switch (instruction->size)
-	    {
-	     case 1:
-	       SET_PC (PC + 2); /* For 1 word instructions */
-	       break;
-	     case 2:
-	       SET_PC (PC + 4); /* For 2 word instructions */
-	       break;
-	     case 3:
-	       SET_PC (PC + 6); /* For 3 word instructions */
-	       break;
-	      default: break;
-	    }
-
-	}
-      
-      /* Check for a breakpoint trap on this instruction.  This
-	 overrides any pending branches or loops */
+        {
+          if (curr_ins_size == 0) 
+           {
+             State.exception = SIG_CR16_EXIT; /* exit trap */
+             break;
+           }
+          else
+           SET_PC (PC + (curr_ins_size * 2)); /* For word instructions.  */
+        }
+
 #if 0
+      /* Check for a breakpoint trap on this instruction.  This
+         overrides any pending branches or loops */
       if (PSR_DB && PC == DBS)
-	{
-	  SET_BPC (PC);
-	  SET_BPSR (PSR);
-	  SET_PC (SDBT_VECTOR_START);
-	}
+        {
+          SET_BPC (PC);
+          SET_BPSR (PSR);
+          SET_PC (SDBT_VECTOR_START);
+        }
 #endif
 
       /* Writeback all the DATA / PC changes */
@@ -1104,10 +1232,10 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
 
 #ifdef NEED_UI_LOOP_HOOK
       if (deprecated_ui_loop_hook != NULL && ui_loop_hook_counter-- < 0)
-	{
-	  ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL;
-	  deprecated_ui_loop_hook (0);
-	}
+        {
+          ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL;
+          deprecated_ui_loop_hook (0);
+        }
 #endif /* NEED_UI_LOOP_HOOK */
     }
   while ( !State.exception && !stop_simulator);
@@ -1133,99 +1261,99 @@ sim_info (SIM_DESC sd, int verbose)
   char buf4[40];
   char buf5[40];
 #if 0
-  unsigned long left		= ins_type_counters[ (int)INS_LEFT ] + ins_type_counters[ (int)INS_LEFT_COND_EXE ];
-  unsigned long left_nops	= ins_type_counters[ (int)INS_LEFT_NOPS ];
-  unsigned long left_parallel	= ins_type_counters[ (int)INS_LEFT_PARALLEL ];
-  unsigned long left_cond	= ins_type_counters[ (int)INS_LEFT_COND_TEST ];
-  unsigned long left_total	= left + left_parallel + left_cond + left_nops;
-
-  unsigned long right		= ins_type_counters[ (int)INS_RIGHT ] + ins_type_counters[ (int)INS_RIGHT_COND_EXE ];
-  unsigned long right_nops	= ins_type_counters[ (int)INS_RIGHT_NOPS ];
-  unsigned long right_parallel	= ins_type_counters[ (int)INS_RIGHT_PARALLEL ];
-  unsigned long right_cond	= ins_type_counters[ (int)INS_RIGHT_COND_TEST ];
-  unsigned long right_total	= right + right_parallel + right_cond + right_nops;
-
-  unsigned long unknown		= ins_type_counters[ (int)INS_UNKNOWN ];
-  unsigned long ins_long	= ins_type_counters[ (int)INS_LONG ];
-  unsigned long parallel	= ins_type_counters[ (int)INS_PARALLEL ];
-  unsigned long leftright	= ins_type_counters[ (int)INS_LEFTRIGHT ];
-  unsigned long rightleft	= ins_type_counters[ (int)INS_RIGHTLEFT ];
-  unsigned long cond_true	= ins_type_counters[ (int)INS_COND_TRUE ];
-  unsigned long cond_false	= ins_type_counters[ (int)INS_COND_FALSE ];
-  unsigned long cond_jump	= ins_type_counters[ (int)INS_COND_JUMP ];
-  unsigned long cycles		= ins_type_counters[ (int)INS_CYCLES ];
-  unsigned long total		= (unknown + left_total + right_total + ins_long);
-
-  int size			= strlen (add_commas (buf1, sizeof (buf1), total));
-  int parallel_size		= strlen (add_commas (buf1, sizeof (buf1),
-						      (left_parallel > right_parallel) ? left_parallel : right_parallel));
-  int cond_size			= strlen (add_commas (buf1, sizeof (buf1), (left_cond > right_cond) ? left_cond : right_cond));
-  int nop_size			= strlen (add_commas (buf1, sizeof (buf1), (left_nops > right_nops) ? left_nops : right_nops));
-  int normal_size		= strlen (add_commas (buf1, sizeof (buf1), (left > right) ? left : right));
+  unsigned long left                = ins_type_counters[ (int)INS_LEFT ] + ins_type_counters[ (int)INS_LEFT_COND_EXE ];
+  unsigned long left_nops        = ins_type_counters[ (int)INS_LEFT_NOPS ];
+  unsigned long left_parallel        = ins_type_counters[ (int)INS_LEFT_PARALLEL ];
+  unsigned long left_cond        = ins_type_counters[ (int)INS_LEFT_COND_TEST ];
+  unsigned long left_total        = left + left_parallel + left_cond + left_nops;
+
+  unsigned long right                = ins_type_counters[ (int)INS_RIGHT ] + ins_type_counters[ (int)INS_RIGHT_COND_EXE ];
+  unsigned long right_nops        = ins_type_counters[ (int)INS_RIGHT_NOPS ];
+  unsigned long right_parallel        = ins_type_counters[ (int)INS_RIGHT_PARALLEL ];
+  unsigned long right_cond        = ins_type_counters[ (int)INS_RIGHT_COND_TEST ];
+  unsigned long right_total        = right + right_parallel + right_cond + right_nops;
+
+  unsigned long unknown                = ins_type_counters[ (int)INS_UNKNOWN ];
+  unsigned long ins_long        = ins_type_counters[ (int)INS_LONG ];
+  unsigned long parallel        = ins_type_counters[ (int)INS_PARALLEL ];
+  unsigned long leftright        = ins_type_counters[ (int)INS_LEFTRIGHT ];
+  unsigned long rightleft        = ins_type_counters[ (int)INS_RIGHTLEFT ];
+  unsigned long cond_true        = ins_type_counters[ (int)INS_COND_TRUE ];
+  unsigned long cond_false        = ins_type_counters[ (int)INS_COND_FALSE ];
+  unsigned long cond_jump        = ins_type_counters[ (int)INS_COND_JUMP ];
+  unsigned long cycles                = ins_type_counters[ (int)INS_CYCLES ];
+  unsigned long total                = (unknown + left_total + right_total + ins_long);
+
+  int size                        = strlen (add_commas (buf1, sizeof (buf1), total));
+  int parallel_size                = strlen (add_commas (buf1, sizeof (buf1),
+                                                      (left_parallel > right_parallel) ? left_parallel : right_parallel));
+  int cond_size                        = strlen (add_commas (buf1, sizeof (buf1), (left_cond > right_cond) ? left_cond : right_cond));
+  int nop_size                        = strlen (add_commas (buf1, sizeof (buf1), (left_nops > right_nops) ? left_nops : right_nops));
+  int normal_size                = strlen (add_commas (buf1, sizeof (buf1), (left > right) ? left : right));
 
   (*cr16_callback->printf_filtered) (cr16_callback,
-				     "executed %*s left  instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
-				     size, add_commas (buf1, sizeof (buf1), left_total),
-				     normal_size, add_commas (buf2, sizeof (buf2), left),
-				     parallel_size, add_commas (buf3, sizeof (buf3), left_parallel),
-				     cond_size, add_commas (buf4, sizeof (buf4), left_cond),
-				     nop_size, add_commas (buf5, sizeof (buf5), left_nops));
+                                     "executed %*s left  instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
+                                     size, add_commas (buf1, sizeof (buf1), left_total),
+                                     normal_size, add_commas (buf2, sizeof (buf2), left),
+                                     parallel_size, add_commas (buf3, sizeof (buf3), left_parallel),
+                                     cond_size, add_commas (buf4, sizeof (buf4), left_cond),
+                                     nop_size, add_commas (buf5, sizeof (buf5), left_nops));
 
   (*cr16_callback->printf_filtered) (cr16_callback,
-				     "executed %*s right instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
-				     size, add_commas (buf1, sizeof (buf1), right_total),
-				     normal_size, add_commas (buf2, sizeof (buf2), right),
-				     parallel_size, add_commas (buf3, sizeof (buf3), right_parallel),
-				     cond_size, add_commas (buf4, sizeof (buf4), right_cond),
-				     nop_size, add_commas (buf5, sizeof (buf5), right_nops));
+                                     "executed %*s right instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
+                                     size, add_commas (buf1, sizeof (buf1), right_total),
+                                     normal_size, add_commas (buf2, sizeof (buf2), right),
+                                     parallel_size, add_commas (buf3, sizeof (buf3), right_parallel),
+                                     cond_size, add_commas (buf4, sizeof (buf4), right_cond),
+                                     nop_size, add_commas (buf5, sizeof (buf5), right_nops));
 
   if (ins_long)
     (*cr16_callback->printf_filtered) (cr16_callback,
-				       "executed %*s long instruction(s)\n",
-				       size, add_commas (buf1, sizeof (buf1), ins_long));
+                                       "executed %*s long instruction(s)\n",
+                                       size, add_commas (buf1, sizeof (buf1), ins_long));
 
   if (parallel)
     (*cr16_callback->printf_filtered) (cr16_callback,
-				       "executed %*s parallel instruction(s)\n",
-				       size, add_commas (buf1, sizeof (buf1), parallel));
+                                       "executed %*s parallel instruction(s)\n",
+                                       size, add_commas (buf1, sizeof (buf1), parallel));
 
   if (leftright)
     (*cr16_callback->printf_filtered) (cr16_callback,
-				       "executed %*s instruction(s) encoded L->R\n",
-				       size, add_commas (buf1, sizeof (buf1), leftright));
+                                       "executed %*s instruction(s) encoded L->R\n",
+                                       size, add_commas (buf1, sizeof (buf1), leftright));
 
   if (rightleft)
     (*cr16_callback->printf_filtered) (cr16_callback,
-				       "executed %*s instruction(s) encoded R->L\n",
-				       size, add_commas (buf1, sizeof (buf1), rightleft));
+                                       "executed %*s instruction(s) encoded R->L\n",
+                                       size, add_commas (buf1, sizeof (buf1), rightleft));
 
   if (unknown)
     (*cr16_callback->printf_filtered) (cr16_callback,
-				       "executed %*s unknown instruction(s)\n",
-				       size, add_commas (buf1, sizeof (buf1), unknown));
+                                       "executed %*s unknown instruction(s)\n",
+                                       size, add_commas (buf1, sizeof (buf1), unknown));
 
   if (cond_true)
     (*cr16_callback->printf_filtered) (cr16_callback,
-				       "executed %*s instruction(s) due to EXExxx condition being true\n",
-				       size, add_commas (buf1, sizeof (buf1), cond_true));
+                                       "executed %*s instruction(s) due to EXExxx condition being true\n",
+                                       size, add_commas (buf1, sizeof (buf1), cond_true));
 
   if (cond_false)
     (*cr16_callback->printf_filtered) (cr16_callback,
-				       "skipped  %*s instruction(s) due to EXExxx condition being false\n",
-				       size, add_commas (buf1, sizeof (buf1), cond_false));
+                                       "skipped  %*s instruction(s) due to EXExxx condition being false\n",
+                                       size, add_commas (buf1, sizeof (buf1), cond_false));
 
   if (cond_jump)
     (*cr16_callback->printf_filtered) (cr16_callback,
-				       "skipped  %*s instruction(s) due to conditional branch succeeding\n",
-				       size, add_commas (buf1, sizeof (buf1), cond_jump));
+                                       "skipped  %*s instruction(s) due to conditional branch succeeding\n",
+                                       size, add_commas (buf1, sizeof (buf1), cond_jump));
 
   (*cr16_callback->printf_filtered) (cr16_callback,
-				     "executed %*s cycle(s)\n",
-				     size, add_commas (buf1, sizeof (buf1), cycles));
+                                     "executed %*s cycle(s)\n",
+                                     size, add_commas (buf1, sizeof (buf1), cycles));
 
   (*cr16_callback->printf_filtered) (cr16_callback,
-				     "executed %*s total instructions\n",
-				     size, add_commas (buf1, sizeof (buf1), total));
+                                     "executed %*s total instructions\n",
+                                     size, add_commas (buf1, sizeof (buf1), total));
 #endif
 }
 
@@ -1278,12 +1406,12 @@ sim_stop_reason (sd, reason, sigrc)
 
   switch (State.exception)
     {
-    case SIG_CR16_STOP:			/* stop instruction */
+    case SIG_CR16_STOP:                        /* stop instruction */
       *reason = sim_stopped;
       *sigrc = 0;
       break;
 
-    case SIG_CR16_EXIT:			/* exit trap */
+    case SIG_CR16_EXIT:                        /* exit trap */
       *reason = sim_exited;
       *sigrc = GPR (2);
       break;
@@ -1298,12 +1426,12 @@ sim_stop_reason (sd, reason, sigrc)
 //      *sigrc = TARGET_SIGNAL_IAD;
 //      break;
 
-    default:				/* some signal */
+    default:                                /* some signal */
       *reason = sim_stopped;
       if (stop_simulator && !State.exception)
-	*sigrc = TARGET_SIGNAL_INT;
+        *sigrc = TARGET_SIGNAL_INT;
       else
-	*sigrc = State.exception;
+        *sigrc = State.exception;
       break;
     }
 
@@ -1439,8 +1567,8 @@ sim_load (SIM_DESC sd, char *prog, struct bfd *abfd, int from_tty)
       prog_bfd_was_opened_p = 0;
     }
   prog_bfd = sim_load_file (sd, myname, cr16_callback, prog, abfd,
-			    sim_kind == SIM_OPEN_DEBUG,
-			    1/*LMA*/, sim_write);
+                            sim_kind == SIM_OPEN_DEBUG,
+                            1/*LMA*/, sim_write);
   if (prog_bfd == NULL)
     return SIM_RC_FAIL;
   prog_bfd_was_opened_p = abfd == NULL;