aboutsummaryrefslogtreecommitdiff
path: root/sim
diff options
context:
space:
mode:
authorAngela Marie Thomas <angela@cygnus>1996-12-25 06:14:26 +0000
committerAngela Marie Thomas <angela@cygnus>1996-12-25 06:14:26 +0000
commit280f90e1a0d74e0b38ea6385a41609dacd5e18af (patch)
tree1ea2f86ffa028a1adcb4c38d8dcbf0a787f09884 /sim
parente98c90e6ce94b3db2a0cac52b65ad615d31e4d53 (diff)
downloadgdb-280f90e1a0d74e0b38ea6385a41609dacd5e18af.zip
gdb-280f90e1a0d74e0b38ea6385a41609dacd5e18af.tar.gz
gdb-280f90e1a0d74e0b38ea6385a41609dacd5e18af.tar.bz2
add flush_cache PMON routine
Diffstat (limited to 'sim')
-rw-r--r--sim/mips/ChangeLog5
-rw-r--r--sim/mips/interp.c7
2 files changed, 12 insertions, 0 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 53b65cb..c4f7709 100644
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -28,6 +28,11 @@ Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
(INDELAYSLOT, INJALDELAYSLOT): Define.
(simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
+Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
+
+ * interp.c (sim_open): add flush_cache as a PMON routine
+ (sim_monitor): handle flush_cache by ignoring it
+
Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
* gencode.c (build_instruction): Use !ByteSwapMem instead of
diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index c344f0c..345ce33 100644
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -816,6 +816,10 @@ Re-compile simulator with \"-DPROFILE\" to enable this option.\n");
case 8: /* cliexit */
value = 17;
break;
+
+ case 11: /* flush_cache */
+ value = 28;
+ break;
}
/* FIXME - should monitor_base be SIM_ADDR?? */
value = ((unsigned int)monitor_base + (value * 8));
@@ -1649,6 +1653,9 @@ sim_monitor(reason)
rcexit = (unsigned int)(A0 & 0xFFFFFFFF);
break;
+ case 28 : /* PMON flush_cache */
+ break;
+
case 55: /* void get_mem_info(unsigned int *ptr) */
/* in: A0 = pointer to three word memory location */
/* out: [A0 + 0] = size */