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authorAndrew Cagney <cagney@redhat.com>2000-05-01 07:06:10 +0000
committerAndrew Cagney <cagney@redhat.com>2000-05-01 07:06:10 +0000
commitdd37a34b6fb4b92552fd195ebf1b33c350c675a7 (patch)
tree8d06540d1c5717dd29ed136c466f6766b8775153 /sim
parentdff14200823269f8fa673de4c4a8d8b5ff3bf7a2 (diff)
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* mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
Diffstat (limited to 'sim')
-rw-r--r--sim/mips/ChangeLog4
-rw-r--r--sim/mips/mips.igen3
2 files changed, 6 insertions, 1 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 799159c..c5236a4 100644
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,7 @@
+Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
+
Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
* interp.c (decode_coproc): Output long using %lx and not %s.
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index 3589b31..e83f561 100644
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -3064,7 +3064,8 @@
{
if (STATE_VERBOSE_P(SD))
sim_io_eprintf (SD,
- "Warning: PC 0x%x: DMxC1 32-bit use of odd FPR number\n", CIA);
+ "Warning: PC 0x%lx: DMxC1 32-bit use of odd FPR number\n",
+ (long) CIA);
GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
}
}