diff options
| author | Chris Demetriou <cgd@google.com> | 2001-02-08 05:22:04 +0000 |
|---|---|---|
| committer | Chris Demetriou <cgd@google.com> | 2001-02-08 05:22:04 +0000 |
| commit | 56b48a7a9bec7a6d217d3ad4ff8458cb57e4a511 (patch) | |
| tree | 2d47fcd37889e46ec09bd4acc50afaf21752ffac /sim | |
| parent | 72290732e94ff7ab2dcd66e6bc8f1c1c7aa92fd8 (diff) | |
| download | gdb-56b48a7a9bec7a6d217d3ad4ff8458cb57e4a511.zip gdb-56b48a7a9bec7a6d217d3ad4ff8458cb57e4a511.tar.gz gdb-56b48a7a9bec7a6d217d3ad4ff8458cb57e4a511.tar.bz2 | |
2001-02-08 Ben Elliston <bje@redhat.com>
* sim-main.c (load_memory): Pass cia to sim_core_read* functions.
(store_memory): Likewise, pass cia to sim_core_write*.
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/mips/ChangeLog | 5 | ||||
| -rw-r--r-- | sim/mips/sim-main.c | 52 |
2 files changed, 23 insertions, 34 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index 5273dbf..8a3e458 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,8 @@ +2001-02-08 Ben Elliston <bje@redhat.com> + + * sim-main.c (load_memory): Pass cia to sim_core_read* functions. + (store_memory): Likewise, pass cia to sim_core_write*. + 2000-10-19 Frank Ch. Eigler <fche@redhat.com> On advice from Chris G. Demetriou <cgd@sibyte.com>: diff --git a/sim/mips/sim-main.c b/sim/mips/sim-main.c index 48a37ae..7b3e6c6 100644 --- a/sim/mips/sim-main.c +++ b/sim/mips/sim-main.c @@ -165,42 +165,34 @@ load_memory (SIM_DESC SD, { case AccessLength_QUADWORD : { - unsigned_16 val = sim_core_read_aligned_16 (CPU, NULL_CIA, read_map, pAddr); + unsigned_16 val = sim_core_read_aligned_16 (CPU, cia, read_map, pAddr); value1 = VH8_16 (val); value = VL8_16 (val); break; } case AccessLength_DOUBLEWORD : - value = sim_core_read_aligned_8 (CPU, NULL_CIA, - read_map, pAddr); + value = sim_core_read_aligned_8 (CPU, cia, read_map, pAddr); break; case AccessLength_SEPTIBYTE : - value = sim_core_read_misaligned_7 (CPU, NULL_CIA, - read_map, pAddr); + value = sim_core_read_misaligned_7 (CPU, cia, read_map, pAddr); break; case AccessLength_SEXTIBYTE : - value = sim_core_read_misaligned_6 (CPU, NULL_CIA, - read_map, pAddr); + value = sim_core_read_misaligned_6 (CPU, cia, read_map, pAddr); break; case AccessLength_QUINTIBYTE : - value = sim_core_read_misaligned_5 (CPU, NULL_CIA, - read_map, pAddr); + value = sim_core_read_misaligned_5 (CPU, cia, read_map, pAddr); break; case AccessLength_WORD : - value = sim_core_read_aligned_4 (CPU, NULL_CIA, - read_map, pAddr); + value = sim_core_read_aligned_4 (CPU, cia, read_map, pAddr); break; case AccessLength_TRIPLEBYTE : - value = sim_core_read_misaligned_3 (CPU, NULL_CIA, - read_map, pAddr); + value = sim_core_read_misaligned_3 (CPU, cia, read_map, pAddr); break; case AccessLength_HALFWORD : - value = sim_core_read_aligned_2 (CPU, NULL_CIA, - read_map, pAddr); + value = sim_core_read_aligned_2 (CPU, cia, read_map, pAddr); break; case AccessLength_BYTE : - value = sim_core_read_aligned_1 (CPU, NULL_CIA, - read_map, pAddr); + value = sim_core_read_aligned_1 (CPU, cia, read_map, pAddr); break; default: abort (); @@ -303,40 +295,32 @@ store_memory (SIM_DESC SD, case AccessLength_QUADWORD : { unsigned_16 val = U16_8 (MemElem1, MemElem); - sim_core_write_aligned_16 (CPU, NULL_CIA, write_map, pAddr, val); + sim_core_write_aligned_16 (CPU, cia, write_map, pAddr, val); break; } case AccessLength_DOUBLEWORD : - sim_core_write_aligned_8 (CPU, NULL_CIA, - write_map, pAddr, MemElem); + sim_core_write_aligned_8 (CPU, cia, write_map, pAddr, MemElem); break; case AccessLength_SEPTIBYTE : - sim_core_write_misaligned_7 (CPU, NULL_CIA, - write_map, pAddr, MemElem); + sim_core_write_misaligned_7 (CPU, cia, write_map, pAddr, MemElem); break; case AccessLength_SEXTIBYTE : - sim_core_write_misaligned_6 (CPU, NULL_CIA, - write_map, pAddr, MemElem); + sim_core_write_misaligned_6 (CPU, cia, write_map, pAddr, MemElem); break; case AccessLength_QUINTIBYTE : - sim_core_write_misaligned_5 (CPU, NULL_CIA, - write_map, pAddr, MemElem); + sim_core_write_misaligned_5 (CPU, cia, write_map, pAddr, MemElem); break; case AccessLength_WORD : - sim_core_write_aligned_4 (CPU, NULL_CIA, - write_map, pAddr, MemElem); + sim_core_write_aligned_4 (CPU, cia, write_map, pAddr, MemElem); break; case AccessLength_TRIPLEBYTE : - sim_core_write_misaligned_3 (CPU, NULL_CIA, - write_map, pAddr, MemElem); + sim_core_write_misaligned_3 (CPU, cia, write_map, pAddr, MemElem); break; case AccessLength_HALFWORD : - sim_core_write_aligned_2 (CPU, NULL_CIA, - write_map, pAddr, MemElem); + sim_core_write_aligned_2 (CPU, cia, write_map, pAddr, MemElem); break; case AccessLength_BYTE : - sim_core_write_aligned_1 (CPU, NULL_CIA, - write_map, pAddr, MemElem); + sim_core_write_aligned_1 (CPU, cia, write_map, pAddr, MemElem); break; default: abort (); |